xhci-pci: Only run d3cold avoidance quirk for s2idle
Donghun reports that a notebook that has an AMD Ryzen 5700U but supports S3 has problems with USB after resuming from suspend. The issue was bisected down to commitd1658268e4
("usb: pci-quirks: disable D3cold on xhci suspend for s2idle on AMD Renoir"). As this issue only happens on S3, narrow the broken D3cold quirk to only run in s2idle. Fixes:d1658268e4
("usb: pci-quirks: disable D3cold on xhci suspend for s2idle on AMD Renoir") Reported-and-tested-by: Donghun Yoon <donghun.yoon@lge.com> Cc: stable@vger.kernel.org Signed-off-by: Mario Limonciello <mario.limonciello@amd.com> Signed-off-by: Mathias Nyman <mathias.nyman@linux.intel.com> Link: https://lore.kernel.org/r/20230515134059.161110-2-mathias.nyman@linux.intel.com Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
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a398d5eac6
Коммит
2a821fc313
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@ -13,6 +13,7 @@
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#include <linux/module.h>
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#include <linux/acpi.h>
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#include <linux/reset.h>
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#include <linux/suspend.h>
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#include "xhci.h"
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#include "xhci-trace.h"
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@ -387,7 +388,7 @@ static void xhci_pci_quirks(struct device *dev, struct xhci_hcd *xhci)
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if (pdev->vendor == PCI_VENDOR_ID_AMD &&
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pdev->device == PCI_DEVICE_ID_AMD_RENOIR_XHCI)
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xhci->quirks |= XHCI_BROKEN_D3COLD;
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xhci->quirks |= XHCI_BROKEN_D3COLD_S2I;
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if (pdev->vendor == PCI_VENDOR_ID_INTEL) {
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xhci->quirks |= XHCI_LPM_SUPPORT;
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@ -801,9 +802,16 @@ static int xhci_pci_suspend(struct usb_hcd *hcd, bool do_wakeup)
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* Systems with the TI redriver that loses port status change events
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* need to have the registers polled during D3, so avoid D3cold.
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*/
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if (xhci->quirks & (XHCI_COMP_MODE_QUIRK | XHCI_BROKEN_D3COLD))
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if (xhci->quirks & XHCI_COMP_MODE_QUIRK)
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pci_d3cold_disable(pdev);
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#ifdef CONFIG_SUSPEND
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/* d3cold is broken, but only when s2idle is used */
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if (pm_suspend_target_state == PM_SUSPEND_TO_IDLE &&
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xhci->quirks & (XHCI_BROKEN_D3COLD_S2I))
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pci_d3cold_disable(pdev);
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#endif
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if (xhci->quirks & XHCI_PME_STUCK_QUIRK)
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xhci_pme_quirk(hcd);
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@ -1901,7 +1901,7 @@ struct xhci_hcd {
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#define XHCI_DISABLE_SPARSE BIT_ULL(38)
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#define XHCI_SG_TRB_CACHE_SIZE_QUIRK BIT_ULL(39)
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#define XHCI_NO_SOFT_RETRY BIT_ULL(40)
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#define XHCI_BROKEN_D3COLD BIT_ULL(41)
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#define XHCI_BROKEN_D3COLD_S2I BIT_ULL(41)
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#define XHCI_EP_CTX_BROKEN_DCS BIT_ULL(42)
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#define XHCI_SUSPEND_RESUME_CLKS BIT_ULL(43)
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#define XHCI_RESET_TO_DEFAULT BIT_ULL(44)
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