drm/i915: Add support for Generic MIPI panel driver
This driver makes use of the generic panel information from the VBT. Panel information is classified into two - panel configuration and panel power sequence which is unique to each panel. The generic driver uses the panel configuration and sequence parsed from VBT block #52 and #53 v2: Address review comments by Jani - Move all of the things in driver c file from header - Make all functions static - Make use of video/mipi_display.c instead of redefining - Null checks during sequence execution v3: Address review comments by Damien - Rename the panel driver file as intel_dsi_panel_vbt.c - Fix style changes as suggested - Correct comments for lp->hs and hs->lp count calculations - General updating comments to have more clarity - using max() instead of ternary operator - Fix names (ui_num, ui_den) while using UI in calculations - compute max of lp_to_hs switch and hs_to_lp switch while computing hs_lp_switch_count Signed-off-by: Shobhit Kumar <shobhit.kumar@intel.com> Reviewed-by: Damien Lespiau <damien.lespiau@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
This commit is contained in:
Shobhit Kumar
Daniel Vetter
Родитель
d6e3cca31e
Коммит
2ab8b458c6
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@ -62,6 +62,7 @@ i915-y += dvo_ch7017.o \
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intel_dsi_cmd.o \
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intel_dsi_cmd.o \
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intel_dsi.o \
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intel_dsi.o \
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intel_dsi_pll.o \
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intel_dsi_pll.o \
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intel_dsi_panel_vbt.o \
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intel_dvo.o \
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intel_dvo.o \
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intel_hdmi.o \
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intel_hdmi.o \
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intel_i2c.o \
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intel_i2c.o \
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@ -35,6 +35,11 @@
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/* the sub-encoders aka panel drivers */
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/* the sub-encoders aka panel drivers */
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static const struct intel_dsi_device intel_dsi_devices[] = {
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static const struct intel_dsi_device intel_dsi_devices[] = {
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{
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.panel_id = MIPI_DSI_GENERIC_PANEL_ID,
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.name = "vbt-generic-dsi-vid-mode-display",
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.dev_ops = &vbt_generic_dsi_display_ops,
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},
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};
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};
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static void band_gap_reset(struct drm_i915_private *dev_priv)
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static void band_gap_reset(struct drm_i915_private *dev_priv)
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@ -133,4 +133,6 @@ static inline struct intel_dsi *enc_to_intel_dsi(struct drm_encoder *encoder)
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extern void vlv_enable_dsi_pll(struct intel_encoder *encoder);
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extern void vlv_enable_dsi_pll(struct intel_encoder *encoder);
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extern void vlv_disable_dsi_pll(struct intel_encoder *encoder);
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extern void vlv_disable_dsi_pll(struct intel_encoder *encoder);
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extern struct intel_dsi_dev_ops vbt_generic_dsi_display_ops;
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#endif /* _INTEL_DSI_H */
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#endif /* _INTEL_DSI_H */
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@ -0,0 +1,589 @@
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/*
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* Copyright © 2014 Intel Corporation
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice (including the next
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* paragraph) shall be included in all copies or substantial portions of the
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* Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*
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* Author: Shobhit Kumar <shobhit.kumar@intel.com>
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*
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*/
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#include <drm/drmP.h>
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#include <drm/drm_crtc.h>
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#include <drm/drm_edid.h>
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#include <drm/i915_drm.h>
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#include <linux/slab.h>
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#include <video/mipi_display.h>
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#include <asm/intel-mid.h>
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#include <video/mipi_display.h>
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#include "i915_drv.h"
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#include "intel_drv.h"
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#include "intel_dsi.h"
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#include "intel_dsi_cmd.h"
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#define MIPI_TRANSFER_MODE_SHIFT 0
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#define MIPI_VIRTUAL_CHANNEL_SHIFT 1
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#define MIPI_PORT_SHIFT 3
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#define PREPARE_CNT_MAX 0x3F
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#define EXIT_ZERO_CNT_MAX 0x3F
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#define CLK_ZERO_CNT_MAX 0xFF
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#define TRAIL_CNT_MAX 0x1F
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#define NS_KHZ_RATIO 1000000
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#define GPI0_NC_0_HV_DDI0_HPD 0x4130
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#define GPIO_NC_0_HV_DDI0_PAD 0x4138
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#define GPIO_NC_1_HV_DDI0_DDC_SDA 0x4120
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#define GPIO_NC_1_HV_DDI0_DDC_SDA_PAD 0x4128
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#define GPIO_NC_2_HV_DDI0_DDC_SCL 0x4110
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#define GPIO_NC_2_HV_DDI0_DDC_SCL_PAD 0x4118
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#define GPIO_NC_3_PANEL0_VDDEN 0x4140
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#define GPIO_NC_3_PANEL0_VDDEN_PAD 0x4148
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#define GPIO_NC_4_PANEL0_BLKEN 0x4150
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#define GPIO_NC_4_PANEL0_BLKEN_PAD 0x4158
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#define GPIO_NC_5_PANEL0_BLKCTL 0x4160
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#define GPIO_NC_5_PANEL0_BLKCTL_PAD 0x4168
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#define GPIO_NC_6_PCONF0 0x4180
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#define GPIO_NC_6_PAD 0x4188
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#define GPIO_NC_7_PCONF0 0x4190
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#define GPIO_NC_7_PAD 0x4198
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#define GPIO_NC_8_PCONF0 0x4170
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#define GPIO_NC_8_PAD 0x4178
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#define GPIO_NC_9_PCONF0 0x4100
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#define GPIO_NC_9_PAD 0x4108
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#define GPIO_NC_10_PCONF0 0x40E0
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#define GPIO_NC_10_PAD 0x40E8
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#define GPIO_NC_11_PCONF0 0x40F0
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#define GPIO_NC_11_PAD 0x40F8
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struct gpio_table {
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u16 function_reg;
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u16 pad_reg;
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u8 init;
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};
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static struct gpio_table gtable[] = {
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{ GPI0_NC_0_HV_DDI0_HPD, GPIO_NC_0_HV_DDI0_PAD, 0 },
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{ GPIO_NC_1_HV_DDI0_DDC_SDA, GPIO_NC_1_HV_DDI0_DDC_SDA_PAD, 0 },
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{ GPIO_NC_2_HV_DDI0_DDC_SCL, GPIO_NC_2_HV_DDI0_DDC_SCL_PAD, 0 },
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{ GPIO_NC_3_PANEL0_VDDEN, GPIO_NC_3_PANEL0_VDDEN_PAD, 0 },
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{ GPIO_NC_4_PANEL0_BLKEN, GPIO_NC_4_PANEL0_BLKEN_PAD, 0 },
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{ GPIO_NC_5_PANEL0_BLKCTL, GPIO_NC_5_PANEL0_BLKCTL_PAD, 0 },
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{ GPIO_NC_6_PCONF0, GPIO_NC_6_PAD, 0 },
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{ GPIO_NC_7_PCONF0, GPIO_NC_7_PAD, 0 },
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{ GPIO_NC_8_PCONF0, GPIO_NC_8_PAD, 0 },
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{ GPIO_NC_9_PCONF0, GPIO_NC_9_PAD, 0 },
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{ GPIO_NC_10_PCONF0, GPIO_NC_10_PAD, 0},
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{ GPIO_NC_11_PCONF0, GPIO_NC_11_PAD, 0}
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};
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static u8 *mipi_exec_send_packet(struct intel_dsi *intel_dsi, u8 *data)
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{
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u8 type, byte, mode, vc, port;
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u16 len;
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byte = *data++;
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mode = (byte >> MIPI_TRANSFER_MODE_SHIFT) & 0x1;
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vc = (byte >> MIPI_VIRTUAL_CHANNEL_SHIFT) & 0x3;
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port = (byte >> MIPI_PORT_SHIFT) & 0x3;
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/* LP or HS mode */
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intel_dsi->hs = mode;
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/* get packet type and increment the pointer */
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type = *data++;
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len = *((u16 *) data);
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data += 2;
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switch (type) {
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case MIPI_DSI_GENERIC_SHORT_WRITE_0_PARAM:
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dsi_vc_generic_write_0(intel_dsi, vc);
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break;
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case MIPI_DSI_GENERIC_SHORT_WRITE_1_PARAM:
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dsi_vc_generic_write_1(intel_dsi, vc, *data);
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break;
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case MIPI_DSI_GENERIC_SHORT_WRITE_2_PARAM:
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dsi_vc_generic_write_2(intel_dsi, vc, *data, *(data + 1));
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break;
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case MIPI_DSI_GENERIC_READ_REQUEST_0_PARAM:
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case MIPI_DSI_GENERIC_READ_REQUEST_1_PARAM:
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case MIPI_DSI_GENERIC_READ_REQUEST_2_PARAM:
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DRM_DEBUG_DRIVER("Generic Read not yet implemented or used\n");
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break;
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case MIPI_DSI_GENERIC_LONG_WRITE:
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dsi_vc_generic_write(intel_dsi, vc, data, len);
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break;
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case MIPI_DSI_DCS_SHORT_WRITE:
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dsi_vc_dcs_write_0(intel_dsi, vc, *data);
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break;
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case MIPI_DSI_DCS_SHORT_WRITE_PARAM:
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dsi_vc_dcs_write_1(intel_dsi, vc, *data, *(data + 1));
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break;
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case MIPI_DSI_DCS_READ:
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DRM_DEBUG_DRIVER("DCS Read not yet implemented or used\n");
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break;
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case MIPI_DSI_DCS_LONG_WRITE:
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dsi_vc_dcs_write(intel_dsi, vc, data, len);
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break;
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};
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data += len;
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return data;
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}
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static u8 *mipi_exec_delay(struct intel_dsi *intel_dsi, u8 *data)
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{
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u32 delay = *((u32 *) data);
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usleep_range(delay, delay + 10);
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data += 4;
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return data;
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}
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static u8 *mipi_exec_gpio(struct intel_dsi *intel_dsi, u8 *data)
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{
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u8 gpio, action;
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u16 function, pad;
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u32 val;
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struct drm_device *dev = intel_dsi->base.base.dev;
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struct drm_i915_private *dev_priv = dev->dev_private;
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gpio = *data++;
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/* pull up/down */
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action = *data++;
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function = gtable[gpio].function_reg;
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pad = gtable[gpio].pad_reg;
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mutex_lock(&dev_priv->dpio_lock);
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if (!gtable[gpio].init) {
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/* program the function */
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/* FIXME: remove constant below */
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vlv_gpio_nc_write(dev_priv, function, 0x2000CC00);
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gtable[gpio].init = 1;
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}
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val = 0x4 | action;
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/* pull up/down */
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vlv_gpio_nc_write(dev_priv, pad, val);
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mutex_unlock(&dev_priv->dpio_lock);
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return data;
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}
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typedef u8 * (*fn_mipi_elem_exec)(struct intel_dsi *intel_dsi, u8 *data);
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static const fn_mipi_elem_exec exec_elem[] = {
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NULL, /* reserved */
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mipi_exec_send_packet,
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mipi_exec_delay,
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mipi_exec_gpio,
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NULL, /* status read; later */
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};
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/*
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* MIPI Sequence from VBT #53 parsing logic
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* We have already separated each seqence during bios parsing
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* Following is generic execution function for any sequence
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*/
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static const char * const seq_name[] = {
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"UNDEFINED",
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"MIPI_SEQ_ASSERT_RESET",
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"MIPI_SEQ_INIT_OTP",
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"MIPI_SEQ_DISPLAY_ON",
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"MIPI_SEQ_DISPLAY_OFF",
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"MIPI_SEQ_DEASSERT_RESET"
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};
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static void generic_exec_sequence(struct intel_dsi *intel_dsi, char *sequence)
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{
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u8 *data = sequence;
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fn_mipi_elem_exec mipi_elem_exec;
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int index;
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if (!sequence)
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return;
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DRM_DEBUG_DRIVER("Starting MIPI sequence - %s\n", seq_name[*data]);
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/* go to the first element of the sequence */
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data++;
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/* parse each byte till we reach end of sequence byte - 0x00 */
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while (1) {
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index = *data;
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mipi_elem_exec = exec_elem[index];
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if (!mipi_elem_exec) {
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DRM_ERROR("Unsupported MIPI element, skipping sequence execution\n");
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return;
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}
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/* goto element payload */
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data++;
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/* execute the element specific rotines */
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data = mipi_elem_exec(intel_dsi, data);
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/*
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* After processing the element, data should point to
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* next element or end of sequence
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* check if have we reached end of sequence
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*/
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if (*data == 0x00)
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break;
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}
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}
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static bool generic_init(struct intel_dsi_device *dsi)
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{
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struct intel_dsi *intel_dsi = container_of(dsi, struct intel_dsi, dev);
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struct drm_device *dev = intel_dsi->base.base.dev;
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struct drm_i915_private *dev_priv = dev->dev_private;
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struct mipi_config *mipi_config = dev_priv->vbt.dsi.config;
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struct mipi_pps_data *pps = dev_priv->vbt.dsi.pps;
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struct drm_display_mode *mode = dev_priv->vbt.lfp_lvds_vbt_mode;
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u32 bits_per_pixel = 24;
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u32 tlpx_ns, extra_byte_count, bitrate, tlpx_ui;
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u32 ui_num, ui_den;
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u32 prepare_cnt, exit_zero_cnt, clk_zero_cnt, trail_cnt;
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u32 ths_prepare_ns, tclk_trail_ns;
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u32 tclk_prepare_clkzero, ths_prepare_hszero;
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u32 lp_to_hs_switch, hs_to_lp_switch;
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DRM_DEBUG_KMS("\n");
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intel_dsi->eotp_pkt = mipi_config->eot_pkt_disabled ? 0 : 1;
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intel_dsi->clock_stop = mipi_config->enable_clk_stop ? 1 : 0;
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intel_dsi->lane_count = mipi_config->lane_cnt + 1;
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intel_dsi->pixel_format = mipi_config->videomode_color_format << 7;
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if (intel_dsi->pixel_format == VID_MODE_FORMAT_RGB666)
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bits_per_pixel = 18;
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else if (intel_dsi->pixel_format == VID_MODE_FORMAT_RGB565)
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bits_per_pixel = 16;
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bitrate = (mode->clock * bits_per_pixel) / intel_dsi->lane_count;
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intel_dsi->operation_mode = mipi_config->is_cmd_mode;
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intel_dsi->video_mode_format = mipi_config->video_transfer_mode;
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intel_dsi->escape_clk_div = mipi_config->byte_clk_sel;
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intel_dsi->lp_rx_timeout = mipi_config->lp_rx_timeout;
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intel_dsi->turn_arnd_val = mipi_config->turn_around_timeout;
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||||||
|
intel_dsi->rst_timer_val = mipi_config->device_reset_timer;
|
||||||
|
intel_dsi->init_count = mipi_config->master_init_timer;
|
||||||
|
intel_dsi->bw_timer = mipi_config->dbi_bw_timer;
|
||||||
|
intel_dsi->video_frmt_cfg_bits = mipi_config->bta_enabled ? DISABLE_VIDEO_BTA : 0;
|
||||||
|
|
||||||
|
switch (intel_dsi->escape_clk_div) {
|
||||||
|
case 0:
|
||||||
|
tlpx_ns = 50;
|
||||||
|
break;
|
||||||
|
case 1:
|
||||||
|
tlpx_ns = 100;
|
||||||
|
break;
|
||||||
|
|
||||||
|
case 2:
|
||||||
|
tlpx_ns = 200;
|
||||||
|
break;
|
||||||
|
default:
|
||||||
|
tlpx_ns = 50;
|
||||||
|
break;
|
||||||
|
}
|
||||||
|
|
||||||
|
switch (intel_dsi->lane_count) {
|
||||||
|
case 1:
|
||||||
|
case 2:
|
||||||
|
extra_byte_count = 2;
|
||||||
|
break;
|
||||||
|
case 3:
|
||||||
|
extra_byte_count = 4;
|
||||||
|
break;
|
||||||
|
case 4:
|
||||||
|
default:
|
||||||
|
extra_byte_count = 3;
|
||||||
|
break;
|
||||||
|
}
|
||||||
|
|
||||||
|
/*
|
||||||
|
* ui(s) = 1/f [f in hz]
|
||||||
|
* ui(ns) = 10^9 / (f*10^6) [f in Mhz] -> 10^3/f(Mhz)
|
||||||
|
*/
|
||||||
|
|
||||||
|
/* in Kbps */
|
||||||
|
ui_num = NS_KHZ_RATIO;
|
||||||
|
ui_den = bitrate;
|
||||||
|
|
||||||
|
tclk_prepare_clkzero = mipi_config->tclk_prepare_clkzero;
|
||||||
|
ths_prepare_hszero = mipi_config->ths_prepare_hszero;
|
||||||
|
|
||||||
|
/*
|
||||||
|
* B060
|
||||||
|
* LP byte clock = TLPX/ (8UI)
|
||||||
|
*/
|
||||||
|
intel_dsi->lp_byte_clk = DIV_ROUND_UP(tlpx_ns * ui_den, 8 * ui_num);
|
||||||
|
|
||||||
|
/* count values in UI = (ns value) * (bitrate / (2 * 10^6))
|
||||||
|
*
|
||||||
|
* Since txddrclkhs_i is 2xUI, all the count values programmed in
|
||||||
|
* DPHY param register are divided by 2
|
||||||
|
*
|
||||||
|
* prepare count
|
||||||
|
*/
|
||||||
|
ths_prepare_ns = max(mipi_config->ths_prepare, mipi_config->tclk_prepare);
|
||||||
|
prepare_cnt = DIV_ROUND_UP(ths_prepare_ns * ui_den, ui_num * 2);
|
||||||
|
|
||||||
|
/* exit zero count */
|
||||||
|
exit_zero_cnt = DIV_ROUND_UP(
|
||||||
|
(ths_prepare_hszero - ths_prepare_ns) * ui_den,
|
||||||
|
ui_num * 2
|
||||||
|
);
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Exit zero is unified val ths_zero and ths_exit
|
||||||
|
* minimum value for ths_exit = 110ns
|
||||||
|
* min (exit_zero_cnt * 2) = 110/UI
|
||||||
|
* exit_zero_cnt = 55/UI
|
||||||
|
*/
|
||||||
|
if (exit_zero_cnt < (55 * ui_den / ui_num))
|
||||||
|
if ((55 * ui_den) % ui_num)
|
||||||
|
exit_zero_cnt += 1;
|
||||||
|
|
||||||
|
/* clk zero count */
|
||||||
|
clk_zero_cnt = DIV_ROUND_UP(
|
||||||
|
(tclk_prepare_clkzero - ths_prepare_ns)
|
||||||
|
* ui_den, 2 * ui_num);
|
||||||
|
|
||||||
|
/* trail count */
|
||||||
|
tclk_trail_ns = max(mipi_config->tclk_trail, mipi_config->ths_trail);
|
||||||
|
trail_cnt = DIV_ROUND_UP(tclk_trail_ns * ui_den, 2 * ui_num);
|
||||||
|
|
||||||
|
if (prepare_cnt > PREPARE_CNT_MAX ||
|
||||||
|
exit_zero_cnt > EXIT_ZERO_CNT_MAX ||
|
||||||
|
clk_zero_cnt > CLK_ZERO_CNT_MAX ||
|
||||||
|
trail_cnt > TRAIL_CNT_MAX)
|
||||||
|
DRM_DEBUG_DRIVER("Values crossing maximum limits, restricting to max values\n");
|
||||||
|
|
||||||
|
if (prepare_cnt > PREPARE_CNT_MAX)
|
||||||
|
prepare_cnt = PREPARE_CNT_MAX;
|
||||||
|
|
||||||
|
if (exit_zero_cnt > EXIT_ZERO_CNT_MAX)
|
||||||
|
exit_zero_cnt = EXIT_ZERO_CNT_MAX;
|
||||||
|
|
||||||
|
if (clk_zero_cnt > CLK_ZERO_CNT_MAX)
|
||||||
|
clk_zero_cnt = CLK_ZERO_CNT_MAX;
|
||||||
|
|
||||||
|
if (trail_cnt > TRAIL_CNT_MAX)
|
||||||
|
trail_cnt = TRAIL_CNT_MAX;
|
||||||
|
|
||||||
|
/* B080 */
|
||||||
|
intel_dsi->dphy_reg = exit_zero_cnt << 24 | trail_cnt << 16 |
|
||||||
|
clk_zero_cnt << 8 | prepare_cnt;
|
||||||
|
|
||||||
|
/*
|
||||||
|
* LP to HS switch count = 4TLPX + PREP_COUNT * 2 + EXIT_ZERO_COUNT * 2
|
||||||
|
* + 10UI + Extra Byte Count
|
||||||
|
*
|
||||||
|
* HS to LP switch count = THS-TRAIL + 2TLPX + Extra Byte Count
|
||||||
|
* Extra Byte Count is calculated according to number of lanes.
|
||||||
|
* High Low Switch Count is the Max of LP to HS and
|
||||||
|
* HS to LP switch count
|
||||||
|
*
|
||||||
|
*/
|
||||||
|
tlpx_ui = DIV_ROUND_UP(tlpx_ns * ui_den, ui_num);
|
||||||
|
|
||||||
|
/* B044 */
|
||||||
|
/* FIXME:
|
||||||
|
* The comment above does not match with the code */
|
||||||
|
lp_to_hs_switch = DIV_ROUND_UP(4 * tlpx_ui + prepare_cnt * 2 +
|
||||||
|
exit_zero_cnt * 2 + 10, 8);
|
||||||
|
|
||||||
|
hs_to_lp_switch = DIV_ROUND_UP(mipi_config->ths_trail + 2 * tlpx_ui, 8);
|
||||||
|
|
||||||
|
intel_dsi->hs_to_lp_count = max(lp_to_hs_switch, hs_to_lp_switch);
|
||||||
|
intel_dsi->hs_to_lp_count += extra_byte_count;
|
||||||
|
|
||||||
|
/* B088 */
|
||||||
|
/* LP -> HS for clock lanes
|
||||||
|
* LP clk sync + LP11 + LP01 + tclk_prepare + tclk_zero +
|
||||||
|
* extra byte count
|
||||||
|
* 2TPLX + 1TLPX + 1 TPLX(in ns) + prepare_cnt * 2 + clk_zero_cnt *
|
||||||
|
* 2(in UI) + extra byte count
|
||||||
|
* In byteclks = (4TLPX + prepare_cnt * 2 + clk_zero_cnt *2 (in UI)) /
|
||||||
|
* 8 + extra byte count
|
||||||
|
*/
|
||||||
|
intel_dsi->clk_lp_to_hs_count =
|
||||||
|
DIV_ROUND_UP(
|
||||||
|
4 * tlpx_ui + prepare_cnt * 2 +
|
||||||
|
clk_zero_cnt * 2,
|
||||||
|
8);
|
||||||
|
|
||||||
|
intel_dsi->clk_lp_to_hs_count += extra_byte_count;
|
||||||
|
|
||||||
|
/* HS->LP for Clock Lanes
|
||||||
|
* Low Power clock synchronisations + 1Tx byteclk + tclk_trail +
|
||||||
|
* Extra byte count
|
||||||
|
* 2TLPX + 8UI + (trail_count*2)(in UI) + Extra byte count
|
||||||
|
* In byteclks = (2*TLpx(in UI) + trail_count*2 +8)(in UI)/8 +
|
||||||
|
* Extra byte count
|
||||||
|
*/
|
||||||
|
intel_dsi->clk_hs_to_lp_count =
|
||||||
|
DIV_ROUND_UP(2 * tlpx_ui + trail_cnt * 2 + 8,
|
||||||
|
8);
|
||||||
|
intel_dsi->clk_hs_to_lp_count += extra_byte_count;
|
||||||
|
|
||||||
|
DRM_DEBUG_KMS("Eot %s\n", intel_dsi->eotp_pkt ? "enabled" : "disabled");
|
||||||
|
DRM_DEBUG_KMS("Clockstop %s\n", intel_dsi->clock_stop ?
|
||||||
|
"disabled" : "enabled");
|
||||||
|
DRM_DEBUG_KMS("Mode %s\n", intel_dsi->operation_mode ? "command" : "video");
|
||||||
|
DRM_DEBUG_KMS("Pixel Format %d\n", intel_dsi->pixel_format);
|
||||||
|
DRM_DEBUG_KMS("TLPX %d\n", intel_dsi->escape_clk_div);
|
||||||
|
DRM_DEBUG_KMS("LP RX Timeout 0x%x\n", intel_dsi->lp_rx_timeout);
|
||||||
|
DRM_DEBUG_KMS("Turnaround Timeout 0x%x\n", intel_dsi->turn_arnd_val);
|
||||||
|
DRM_DEBUG_KMS("Init Count 0x%x\n", intel_dsi->init_count);
|
||||||
|
DRM_DEBUG_KMS("HS to LP Count 0x%x\n", intel_dsi->hs_to_lp_count);
|
||||||
|
DRM_DEBUG_KMS("LP Byte Clock %d\n", intel_dsi->lp_byte_clk);
|
||||||
|
DRM_DEBUG_KMS("DBI BW Timer 0x%x\n", intel_dsi->bw_timer);
|
||||||
|
DRM_DEBUG_KMS("LP to HS Clock Count 0x%x\n", intel_dsi->clk_lp_to_hs_count);
|
||||||
|
DRM_DEBUG_KMS("HS to LP Clock Count 0x%x\n", intel_dsi->clk_hs_to_lp_count);
|
||||||
|
DRM_DEBUG_KMS("BTA %s\n",
|
||||||
|
intel_dsi->video_frmt_cfg_bits & DISABLE_VIDEO_BTA ?
|
||||||
|
"disabled" : "enabled");
|
||||||
|
|
||||||
|
/* delays in VBT are in unit of 100us, so need to convert
|
||||||
|
* here in ms
|
||||||
|
* Delay (100us) * 100 /1000 = Delay / 10 (ms) */
|
||||||
|
intel_dsi->backlight_off_delay = pps->bl_disable_delay / 10;
|
||||||
|
intel_dsi->backlight_on_delay = pps->bl_enable_delay / 10;
|
||||||
|
intel_dsi->panel_on_delay = pps->panel_on_delay / 10;
|
||||||
|
intel_dsi->panel_off_delay = pps->panel_off_delay / 10;
|
||||||
|
intel_dsi->panel_pwr_cycle_delay = pps->panel_power_cycle_delay / 10;
|
||||||
|
|
||||||
|
return true;
|
||||||
|
}
|
||||||
|
|
||||||
|
static int generic_mode_valid(struct intel_dsi_device *dsi,
|
||||||
|
struct drm_display_mode *mode)
|
||||||
|
{
|
||||||
|
return MODE_OK;
|
||||||
|
}
|
||||||
|
|
||||||
|
static bool generic_mode_fixup(struct intel_dsi_device *dsi,
|
||||||
|
const struct drm_display_mode *mode,
|
||||||
|
struct drm_display_mode *adjusted_mode) {
|
||||||
|
return true;
|
||||||
|
}
|
||||||
|
|
||||||
|
static void generic_panel_reset(struct intel_dsi_device *dsi)
|
||||||
|
{
|
||||||
|
struct intel_dsi *intel_dsi = container_of(dsi, struct intel_dsi, dev);
|
||||||
|
struct drm_device *dev = intel_dsi->base.base.dev;
|
||||||
|
struct drm_i915_private *dev_priv = dev->dev_private;
|
||||||
|
|
||||||
|
char *sequence = dev_priv->vbt.dsi.sequence[MIPI_SEQ_ASSERT_RESET];
|
||||||
|
|
||||||
|
generic_exec_sequence(intel_dsi, sequence);
|
||||||
|
}
|
||||||
|
|
||||||
|
static void generic_disable_panel_power(struct intel_dsi_device *dsi)
|
||||||
|
{
|
||||||
|
struct intel_dsi *intel_dsi = container_of(dsi, struct intel_dsi, dev);
|
||||||
|
struct drm_device *dev = intel_dsi->base.base.dev;
|
||||||
|
struct drm_i915_private *dev_priv = dev->dev_private;
|
||||||
|
|
||||||
|
char *sequence = dev_priv->vbt.dsi.sequence[MIPI_SEQ_DEASSERT_RESET];
|
||||||
|
|
||||||
|
generic_exec_sequence(intel_dsi, sequence);
|
||||||
|
}
|
||||||
|
|
||||||
|
static void generic_send_otp_cmds(struct intel_dsi_device *dsi)
|
||||||
|
{
|
||||||
|
struct intel_dsi *intel_dsi = container_of(dsi, struct intel_dsi, dev);
|
||||||
|
struct drm_device *dev = intel_dsi->base.base.dev;
|
||||||
|
struct drm_i915_private *dev_priv = dev->dev_private;
|
||||||
|
|
||||||
|
char *sequence = dev_priv->vbt.dsi.sequence[MIPI_SEQ_INIT_OTP];
|
||||||
|
|
||||||
|
generic_exec_sequence(intel_dsi, sequence);
|
||||||
|
}
|
||||||
|
|
||||||
|
static void generic_enable(struct intel_dsi_device *dsi)
|
||||||
|
{
|
||||||
|
struct intel_dsi *intel_dsi = container_of(dsi, struct intel_dsi, dev);
|
||||||
|
struct drm_device *dev = intel_dsi->base.base.dev;
|
||||||
|
struct drm_i915_private *dev_priv = dev->dev_private;
|
||||||
|
|
||||||
|
char *sequence = dev_priv->vbt.dsi.sequence[MIPI_SEQ_DISPLAY_ON];
|
||||||
|
|
||||||
|
generic_exec_sequence(intel_dsi, sequence);
|
||||||
|
}
|
||||||
|
|
||||||
|
static void generic_disable(struct intel_dsi_device *dsi)
|
||||||
|
{
|
||||||
|
struct intel_dsi *intel_dsi = container_of(dsi, struct intel_dsi, dev);
|
||||||
|
struct drm_device *dev = intel_dsi->base.base.dev;
|
||||||
|
struct drm_i915_private *dev_priv = dev->dev_private;
|
||||||
|
|
||||||
|
char *sequence = dev_priv->vbt.dsi.sequence[MIPI_SEQ_DISPLAY_OFF];
|
||||||
|
|
||||||
|
generic_exec_sequence(intel_dsi, sequence);
|
||||||
|
}
|
||||||
|
|
||||||
|
static enum drm_connector_status generic_detect(struct intel_dsi_device *dsi)
|
||||||
|
{
|
||||||
|
return connector_status_connected;
|
||||||
|
}
|
||||||
|
|
||||||
|
static bool generic_get_hw_state(struct intel_dsi_device *dev)
|
||||||
|
{
|
||||||
|
return true;
|
||||||
|
}
|
||||||
|
|
||||||
|
static struct drm_display_mode *generic_get_modes(struct intel_dsi_device *dsi)
|
||||||
|
{
|
||||||
|
struct intel_dsi *intel_dsi = container_of(dsi, struct intel_dsi, dev);
|
||||||
|
struct drm_device *dev = intel_dsi->base.base.dev;
|
||||||
|
struct drm_i915_private *dev_priv = dev->dev_private;
|
||||||
|
|
||||||
|
dev_priv->vbt.lfp_lvds_vbt_mode->type |= DRM_MODE_TYPE_PREFERRED;
|
||||||
|
return dev_priv->vbt.lfp_lvds_vbt_mode;
|
||||||
|
}
|
||||||
|
|
||||||
|
static void generic_destroy(struct intel_dsi_device *dsi) { }
|
||||||
|
|
||||||
|
/* Callbacks. We might not need them all. */
|
||||||
|
struct intel_dsi_dev_ops vbt_generic_dsi_display_ops = {
|
||||||
|
.init = generic_init,
|
||||||
|
.mode_valid = generic_mode_valid,
|
||||||
|
.mode_fixup = generic_mode_fixup,
|
||||||
|
.panel_reset = generic_panel_reset,
|
||||||
|
.disable_panel_power = generic_disable_panel_power,
|
||||||
|
.send_otp_cmds = generic_send_otp_cmds,
|
||||||
|
.enable = generic_enable,
|
||||||
|
.disable = generic_disable,
|
||||||
|
.detect = generic_detect,
|
||||||
|
.get_hw_state = generic_get_hw_state,
|
||||||
|
.get_modes = generic_get_modes,
|
||||||
|
.destroy = generic_destroy,
|
||||||
|
};
|
||||||
Загрузка…
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