audio: tlv320aic26: fix PLL register configuration
The current PLL configuration code for the tlc320aic26 codec appears to assume a hardcoded system clock of 12 MHz. Use the clock value provided by the DAI_OPS API for the calculation. Tested using a MityDSP-L138 platform providing a 24.576 MHz clock. Signed-off-by: Michael Williamson <michael.williamson@criticallink.com> Acked-by: Mark Brown <broonie@opensource.wolfsonmicro.com> Signed-off-by: Liam Girdwood <lrg@ti.com>
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4a787a3ff3
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2aba76f014
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@ -161,10 +161,18 @@ static int aic26_hw_params(struct snd_pcm_substream *substream,
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dev_dbg(&aic26->spi->dev, "bad format\n"); return -EINVAL;
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dev_dbg(&aic26->spi->dev, "bad format\n"); return -EINVAL;
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}
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}
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/* Configure PLL */
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/**
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* Configure PLL
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* fsref = (mclk * PLLM) / 2048
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* where PLLM = J.DDDD (DDDD register ranges from 0 to 9999, decimal)
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*/
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pval = 1;
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pval = 1;
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jval = (fsref == 44100) ? 7 : 8;
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/* compute J portion of multiplier */
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dval = (fsref == 44100) ? 5264 : 1920;
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jval = fsref / (aic26->mclk / 2048);
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/* compute fractional DDDD component of multiplier */
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dval = fsref - (jval * (aic26->mclk / 2048));
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dval = (10000 * dval) / (aic26->mclk / 2048);
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dev_dbg(&aic26->spi->dev, "Setting PLLM to %d.%04d\n", jval, dval);
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qval = 0;
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qval = 0;
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reg = 0x8000 | qval << 11 | pval << 8 | jval << 2;
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reg = 0x8000 | qval << 11 | pval << 8 | jval << 2;
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aic26_reg_write(codec, AIC26_REG_PLL_PROG1, reg);
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aic26_reg_write(codec, AIC26_REG_PLL_PROG1, reg);
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