drm/i915: Use RMW to update chicken bits in gen7_enable_fbc()

gen7_enable_fbc() may write to some registers which we've already
touched, so use RMW so that we don't undo any previous updates.

Also note that we implemnt WaFbcAsynchFlipDisableFbcQueue:bdw.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Damien Lespiau <damien.lespiau@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
This commit is contained in:
Ville Syrjälä 2014-03-05 13:05:46 +02:00 коммит произвёл Daniel Vetter
Родитель c7c6562268
Коммит 2adb6db8d9
1 изменённых файлов: 5 добавлений и 2 удалений

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@ -294,10 +294,13 @@ static void gen7_enable_fbc(struct drm_crtc *crtc)
if (IS_IVYBRIDGE(dev)) { if (IS_IVYBRIDGE(dev)) {
/* WaFbcAsynchFlipDisableFbcQueue:ivb */ /* WaFbcAsynchFlipDisableFbcQueue:ivb */
I915_WRITE(ILK_DISPLAY_CHICKEN1, ILK_FBCQ_DIS); I915_WRITE(ILK_DISPLAY_CHICKEN1,
I915_READ(ILK_DISPLAY_CHICKEN1) |
ILK_FBCQ_DIS);
} else { } else {
/* WaFbcAsynchFlipDisableFbcQueue:hsw */ /* WaFbcAsynchFlipDisableFbcQueue:hsw,bdw */
I915_WRITE(HSW_PIPE_SLICE_CHICKEN_1(intel_crtc->pipe), I915_WRITE(HSW_PIPE_SLICE_CHICKEN_1(intel_crtc->pipe),
I915_READ(HSW_PIPE_SLICE_CHICKEN_1(intel_crtc->pipe)) |
HSW_BYPASS_FBC_QUEUE); HSW_BYPASS_FBC_QUEUE);
} }