ioat3: hardware version 3.2 register / descriptor definitions
ioat3.2 adds raid5 and raid6 offload capabilities. Signed-off-by: Tom Picard <tom.s.picard@intel.com> Signed-off-by: Dan Williams <dan.j.williams@intel.com>
This commit is contained in:
Dan Williams
Родитель
128f2d567f
Коммит
2aec048cdc
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@ -155,7 +155,7 @@ ioat_is_complete(struct dma_chan *c, dma_cookie_t cookie,
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/**
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* struct ioat_desc_sw - wrapper around hardware descriptor
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* @hw: hardware DMA descriptor
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* @hw: hardware DMA descriptor (for memcpy)
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* @node: this descriptor will either be on the free list,
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* or attached to a transaction list (async_tx.tx_list)
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* @txd: the generic software descriptor for all engines
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@ -114,8 +114,32 @@ static inline u16 ioat2_xferlen_to_descs(struct ioat2_dma_chan *ioat, size_t len
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return num_descs;
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}
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/**
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* struct ioat_ring_ent - wrapper around hardware descriptor
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* @hw: hardware DMA descriptor (for memcpy)
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* @fill: hardware fill descriptor
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* @xor: hardware xor descriptor
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* @xor_ex: hardware xor extension descriptor
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* @pq: hardware pq descriptor
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* @pq_ex: hardware pq extension descriptor
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* @pqu: hardware pq update descriptor
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* @raw: hardware raw (un-typed) descriptor
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* @txd: the generic software descriptor for all engines
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* @len: total transaction length for unmap
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* @id: identifier for debug
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*/
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struct ioat_ring_ent {
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struct ioat_dma_descriptor *hw;
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union {
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struct ioat_dma_descriptor *hw;
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struct ioat_fill_descriptor *fill;
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struct ioat_xor_descriptor *xor;
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struct ioat_xor_ext_descriptor *xor_ex;
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struct ioat_pq_descriptor *pq;
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struct ioat_pq_ext_descriptor *pq_ex;
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struct ioat_pq_update_descriptor *pqu;
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struct ioat_raw_descriptor *raw;
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};
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struct dma_async_tx_descriptor txd;
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size_t len;
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#ifdef DEBUG
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@ -37,6 +37,7 @@
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#define IOAT_VER_1_2 0x12 /* Version 1.2 */
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#define IOAT_VER_2_0 0x20 /* Version 2.0 */
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#define IOAT_VER_3_0 0x30 /* Version 3.0 */
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#define IOAT_VER_3_2 0x32 /* Version 3.2 */
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struct ioat_dma_descriptor {
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uint32_t size;
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@ -55,6 +56,7 @@ struct ioat_dma_descriptor {
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unsigned int dest_dca:1;
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unsigned int hint:1;
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unsigned int rsvd2:13;
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#define IOAT_OP_COPY 0x00
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unsigned int op:8;
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} ctl_f;
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};
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@ -70,4 +72,144 @@ struct ioat_dma_descriptor {
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};
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uint64_t user2;
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};
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struct ioat_fill_descriptor {
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uint32_t size;
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union {
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uint32_t ctl;
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struct {
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unsigned int int_en:1;
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unsigned int rsvd:1;
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unsigned int dest_snoop_dis:1;
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unsigned int compl_write:1;
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unsigned int fence:1;
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unsigned int rsvd2:2;
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unsigned int dest_brk:1;
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unsigned int bundle:1;
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unsigned int rsvd4:15;
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#define IOAT_OP_FILL 0x01
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unsigned int op:8;
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} ctl_f;
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};
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uint64_t src_data;
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uint64_t dst_addr;
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uint64_t next;
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uint64_t rsv1;
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uint64_t next_dst_addr;
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uint64_t user1;
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uint64_t user2;
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};
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struct ioat_xor_descriptor {
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uint32_t size;
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union {
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uint32_t ctl;
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struct {
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unsigned int int_en:1;
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unsigned int src_snoop_dis:1;
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unsigned int dest_snoop_dis:1;
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unsigned int compl_write:1;
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unsigned int fence:1;
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unsigned int src_cnt:3;
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unsigned int bundle:1;
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unsigned int dest_dca:1;
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unsigned int hint:1;
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unsigned int rsvd:13;
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#define IOAT_OP_XOR 0x87
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#define IOAT_OP_XOR_VAL 0x88
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unsigned int op:8;
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} ctl_f;
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};
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uint64_t src_addr;
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uint64_t dst_addr;
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uint64_t next;
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uint64_t src_addr2;
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uint64_t src_addr3;
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uint64_t src_addr4;
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uint64_t src_addr5;
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};
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struct ioat_xor_ext_descriptor {
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uint64_t src_addr6;
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uint64_t src_addr7;
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uint64_t src_addr8;
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uint64_t next;
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uint64_t rsvd[4];
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};
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struct ioat_pq_descriptor {
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uint32_t size;
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union {
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uint32_t ctl;
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struct {
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unsigned int int_en:1;
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unsigned int src_snoop_dis:1;
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unsigned int dest_snoop_dis:1;
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unsigned int compl_write:1;
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unsigned int fence:1;
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unsigned int src_cnt:3;
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unsigned int bundle:1;
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unsigned int dest_dca:1;
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unsigned int hint:1;
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unsigned int p_disable:1;
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unsigned int q_disable:1;
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unsigned int rsvd:11;
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#define IOAT_OP_PQ 0x89
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#define IOAT_OP_PQ_VAL 0x8a
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unsigned int op:8;
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} ctl_f;
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};
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uint64_t src_addr;
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uint64_t p_addr;
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uint64_t next;
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uint64_t src_addr2;
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uint64_t src_addr3;
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uint8_t coef[8];
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uint64_t q_addr;
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};
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struct ioat_pq_ext_descriptor {
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uint64_t src_addr4;
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uint64_t src_addr5;
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uint64_t src_addr6;
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uint64_t next;
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uint64_t src_addr7;
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uint64_t src_addr8;
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uint64_t rsvd[2];
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};
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struct ioat_pq_update_descriptor {
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uint32_t size;
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union {
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uint32_t ctl;
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struct {
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unsigned int int_en:1;
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unsigned int src_snoop_dis:1;
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unsigned int dest_snoop_dis:1;
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unsigned int compl_write:1;
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unsigned int fence:1;
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unsigned int src_cnt:3;
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unsigned int bundle:1;
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unsigned int dest_dca:1;
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unsigned int hint:1;
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unsigned int p_disable:1;
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unsigned int q_disable:1;
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unsigned int rsvd:3;
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unsigned int coef:8;
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#define IOAT_OP_PQ_UP 0x8b
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unsigned int op:8;
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} ctl_f;
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};
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uint64_t src_addr;
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uint64_t p_addr;
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uint64_t next;
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uint64_t src_addr2;
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uint64_t p_src;
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uint64_t q_src;
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uint64_t q_addr;
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};
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struct ioat_raw_descriptor {
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uint64_t field[8];
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};
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#endif
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@ -64,6 +64,20 @@
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#define IOAT_DEVICE_STATUS_OFFSET 0x0E /* 16-bit */
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#define IOAT_DEVICE_STATUS_DEGRADED_MODE 0x0001
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#define IOAT_DEVICE_MMIO_RESTRICTED 0x0002
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#define IOAT_DEVICE_MEMORY_BYPASS 0x0004
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#define IOAT_DEVICE_ADDRESS_REMAPPING 0x0008
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#define IOAT_DMA_CAP_OFFSET 0x10 /* 32-bit */
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#define IOAT_CAP_PAGE_BREAK 0x00000001
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#define IOAT_CAP_CRC 0x00000002
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#define IOAT_CAP_SKIP_MARKER 0x00000004
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#define IOAT_CAP_DCA 0x00000010
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#define IOAT_CAP_CRC_MOVE 0x00000020
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#define IOAT_CAP_FILL_BLOCK 0x00000040
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#define IOAT_CAP_APIC 0x00000080
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#define IOAT_CAP_XOR 0x00000100
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#define IOAT_CAP_PQ 0x00000200
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#define IOAT_CHANNEL_MMIO_SIZE 0x80 /* Each Channel MMIO space is this size */
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@ -224,6 +238,9 @@
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#define IOAT_CHANERR_INT_CONFIGURATION_ERR 0x2000
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#define IOAT_CHANERR_SOFT_ERR 0x4000
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#define IOAT_CHANERR_UNAFFILIATED_ERR 0x8000
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#define IOAT_CHANERR_XOR_P_OR_CRC_ERR 0x10000
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#define IOAT_CHANERR_XOR_Q_ERR 0x20000
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#define IOAT_CHANERR_DESCRIPTOR_COUNT_ERR 0x40000
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#define IOAT_CHANERR_MASK_OFFSET 0x2C /* 32-bit Channel Error Register */
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