[SCSI] aic7xxx: Update type check in aicasm grammar
The function type_check() in aicasm grammar code was never used properly due to a bug. This patch fixes it up and ensures it's only called if appropriate. In addition the unused 16bit instruction are disabled, but left in the code for reference. Signed-off-by: Hannes Reinecke <hare@suse.de> Signed-off-by: James Bottomley <James.Bottomley@HansenPartnership.com>
This commit is contained in:
Hannes Reinecke
James Bottomley
Родитель
542bd1377a
Коммит
2b48aed182
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@ -101,11 +101,12 @@ static void format_3_instr(int opcode, symbol_ref_t *src,
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expression_t *immed, symbol_ref_t *address);
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static void test_readable_symbol(symbol_t *symbol);
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static void test_writable_symbol(symbol_t *symbol);
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static void type_check(symbol_t *symbol, expression_t *expression, int and_op);
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static void type_check(symbol_ref_t *sym, expression_t *expression, int and_op);
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static void make_expression(expression_t *immed, int value);
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static void add_conditional(symbol_t *symbol);
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static void add_version(const char *verstring);
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static int is_download_const(expression_t *immed);
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static int is_location_address(symbol_t *symbol);
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void yyerror(const char *string);
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#define SRAM_SYMNAME "SRAM_BASE"
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@ -192,10 +193,10 @@ void yyerror(const char *string);
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%token <value> T_OR
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/* 16 bit extensions */
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%token <value> T_OR16 T_AND16 T_XOR16 T_ADD16
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%token <value> T_ADC16 T_MVI16 T_TEST16 T_CMP16 T_CMPXCHG
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/* 16 bit extensions, not implemented
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* %token <value> T_OR16 T_AND16 T_XOR16 T_ADD16
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* %token <value> T_ADC16 T_MVI16 T_TEST16 T_CMP16 T_CMPXCHG
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*/
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%token T_RET
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%token T_NOP
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@ -214,7 +215,7 @@ void yyerror(const char *string);
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%type <expression> expression immediate immediate_or_a
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%type <value> export ret f1_opcode f2_opcode f4_opcode jmp_jc_jnc_call jz_jnz je_jne
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%type <value> export ret f1_opcode f2_opcode jmp_jc_jnc_call jz_jnz je_jne
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%type <value> mode_value mode_list macro_arglist
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@ -313,13 +314,13 @@ reg_definition:
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stop("Register multiply defined", EX_DATAERR);
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/* NOTREACHED */
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}
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cur_symbol = $1;
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cur_symbol = $1;
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cur_symbol->type = cur_symtype;
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initialize_symbol(cur_symbol);
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}
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reg_attribute_list
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'}'
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{
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{
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/*
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* Default to allowing everything in for registers
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* with no bit or mask definitions.
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@ -349,7 +350,7 @@ reg_attribute_list:
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| reg_attribute_list reg_attribute
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;
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reg_attribute:
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reg_attribute:
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reg_address
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| size
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| access_mode
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@ -641,14 +642,14 @@ expression:
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&($1.referenced_syms),
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&($3.referenced_syms));
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}
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| expression T_EXPR_LSHIFT expression
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| expression T_EXPR_LSHIFT expression
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{
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$$.value = $1.value << $3.value;
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symlist_merge(&$$.referenced_syms,
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&$1.referenced_syms,
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&$3.referenced_syms);
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}
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| expression T_EXPR_RSHIFT expression
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| expression T_EXPR_RSHIFT expression
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{
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$$.value = $1.value >> $3.value;
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symlist_merge(&$$.referenced_syms,
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@ -714,7 +715,7 @@ expression:
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;
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constant:
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T_CONST T_SYMBOL expression
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T_CONST T_SYMBOL expression
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{
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if ($2->type != UNINITIALIZED) {
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stop("Re-definition of symbol as a constant",
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@ -1311,14 +1312,18 @@ f2_opcode:
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| T_ROR { $$ = AIC_OP_ROR; }
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;
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f4_opcode:
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T_OR16 { $$ = AIC_OP_OR16; }
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| T_AND16 { $$ = AIC_OP_AND16; }
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| T_XOR16 { $$ = AIC_OP_XOR16; }
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| T_ADD16 { $$ = AIC_OP_ADD16; }
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| T_ADC16 { $$ = AIC_OP_ADC16; }
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| T_MVI16 { $$ = AIC_OP_MVI16; }
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;
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/*
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* 16bit opcodes, not used
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*
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*f4_opcode:
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* T_OR16 { $$ = AIC_OP_OR16; }
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*| T_AND16 { $$ = AIC_OP_AND16; }
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*| T_XOR16 { $$ = AIC_OP_XOR16; }
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*| T_ADD16 { $$ = AIC_OP_ADD16; }
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*| T_ADC16 { $$ = AIC_OP_ADC16; }
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*| T_MVI16 { $$ = AIC_OP_MVI16; }
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*;
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*/
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code:
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f2_opcode destination ',' expression opt_source ret ';'
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@ -1357,6 +1362,7 @@ code:
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code:
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T_OR reg_symbol ',' immediate jmp_jc_jnc_call address ';'
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{
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type_check(&$2, &$4, AIC_OP_OR);
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format_3_instr($5, &$2, &$4, &$6);
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}
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;
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@ -1528,7 +1534,7 @@ initialize_symbol(symbol_t *symbol)
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sizeof(struct cond_info));
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break;
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case MACRO:
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symbol->info.macroinfo =
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symbol->info.macroinfo =
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(struct macro_info *)malloc(sizeof(struct macro_info));
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if (symbol->info.macroinfo == NULL) {
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stop("Can't create macro info", EX_SOFTWARE);
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@ -1552,7 +1558,6 @@ add_macro_arg(const char *argtext, int argnum)
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struct macro_arg *marg;
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int i;
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int retval;
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if (cur_symbol == NULL || cur_symbol->type != MACRO) {
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stop("Invalid current symbol for adding macro arg",
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@ -1633,8 +1638,10 @@ format_1_instr(int opcode, symbol_ref_t *dest, expression_t *immed,
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test_writable_symbol(dest->symbol);
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test_readable_symbol(src->symbol);
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/* Ensure that immediate makes sense for this destination */
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type_check(dest->symbol, immed, opcode);
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if (!is_location_address(dest->symbol)) {
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/* Ensure that immediate makes sense for this destination */
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type_check(dest, immed, opcode);
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}
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/* Allocate sequencer space for the instruction and fill it out */
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instr = seq_alloc();
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@ -1766,9 +1773,6 @@ format_3_instr(int opcode, symbol_ref_t *src,
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/* Test register permissions */
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test_readable_symbol(src->symbol);
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/* Ensure that immediate makes sense for this source */
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type_check(src->symbol, immed, opcode);
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/* Allocate sequencer space for the instruction and fill it out */
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instr = seq_alloc();
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f3_instr = &instr->format.format3;
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@ -1797,7 +1801,6 @@ format_3_instr(int opcode, symbol_ref_t *src,
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static void
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test_readable_symbol(symbol_t *symbol)
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{
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if ((symbol->info.rinfo->modes & (0x1 << src_mode)) == 0) {
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snprintf(errbuf, sizeof(errbuf),
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"Register %s unavailable in source reg mode %d",
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@ -1815,7 +1818,6 @@ test_readable_symbol(symbol_t *symbol)
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static void
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test_writable_symbol(symbol_t *symbol)
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{
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if ((symbol->info.rinfo->modes & (0x1 << dst_mode)) == 0) {
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snprintf(errbuf, sizeof(errbuf),
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"Register %s unavailable in destination reg mode %d",
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@ -1831,25 +1833,34 @@ test_writable_symbol(symbol_t *symbol)
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}
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static void
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type_check(symbol_t *symbol, expression_t *expression, int opcode)
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type_check(symbol_ref_t *sym, expression_t *expression, int opcode)
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{
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symbol_t *symbol = sym->symbol;
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symbol_node_t *node;
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int and_op;
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int8_t value, mask;
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and_op = FALSE;
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if (opcode == AIC_OP_AND || opcode == AIC_OP_JNZ || opcode == AIC_OP_JZ)
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and_op = TRUE;
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/*
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* Make sure that we aren't attempting to write something
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* that hasn't been defined. If this is an and operation,
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* this is a mask, so "undefined" bits are okay.
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*/
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if (and_op == FALSE
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&& (expression->value & ~symbol->info.rinfo->valid_bitmask) != 0) {
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if (opcode == AIC_OP_AND || opcode == AIC_OP_JNZ ||
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opcode == AIC_OP_JZ || opcode == AIC_OP_JNE ||
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opcode == AIC_OP_BMOV)
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and_op = TRUE;
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/*
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* Defaulting to 8 bit logic
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*/
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mask = (int8_t)~symbol->info.rinfo->valid_bitmask;
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value = (int8_t)expression->value;
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if (and_op == FALSE && (mask & value) != 0 ) {
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snprintf(errbuf, sizeof(errbuf),
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"Invalid bit(s) 0x%x in immediate written to %s",
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expression->value & ~symbol->info.rinfo->valid_bitmask,
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(mask & value),
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symbol->name);
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stop(errbuf, EX_DATAERR);
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/* NOTREACHED */
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@ -1959,3 +1970,13 @@ is_download_const(expression_t *immed)
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return (FALSE);
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}
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static int
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is_location_address(symbol_t *sym)
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{
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if (sym->type == SCBLOC ||
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sym->type == SRAMLOC)
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return (TRUE);
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return (FALSE);
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}
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@ -228,15 +228,15 @@ ret { return T_RET; }
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nop { return T_NOP; }
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/* ARP2 16bit extensions */
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or16 { return T_OR16; }
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and16 { return T_AND16; }
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xor16 { return T_XOR16; }
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add16 { return T_ADD16; }
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adc16 { return T_ADC16; }
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mvi16 { return T_MVI16; }
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test16 { return T_TEST16; }
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cmp16 { return T_CMP16; }
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cmpxchg { return T_CMPXCHG; }
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/* or16 { return T_OR16; } */
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/* and16 { return T_AND16; }*/
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/* xor16 { return T_XOR16; }*/
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/* add16 { return T_ADD16; }*/
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/* adc16 { return T_ADC16; }*/
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/* mvi16 { return T_MVI16; }*/
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/* test16 { return T_TEST16; }*/
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/* cmp16 { return T_CMP16; }*/
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/* cmpxchg { return T_CMPXCHG; }*/
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/* Allowed Symbols */
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\<\< { return T_EXPR_LSHIFT; }
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