gpio: ws16c48: Implement and utilize register structures
Reduce magic numbers and improve code readability by implementing and utilizing named register data structures. Reviewed-by: Linus Walleij <linus.walleij@linaro.org> Cc: Paul Demetrotion <pdemetrotion@winsystems.com> Signed-off-by: William Breathitt Gray <william.gray@linaro.org> Signed-off-by: Bartosz Golaszewski <brgl@bgdev.pl>
This commit is contained in:
William Breathitt Gray
Bartosz Golaszewski
Родитель
c4371c5639
Коммит
2c05a0f29f
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@ -4,7 +4,6 @@
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* Copyright (C) 2016 William Breathitt Gray
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*/
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#include <linux/bitmap.h>
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#include <linux/bitops.h>
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#include <linux/device.h>
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#include <linux/errno.h>
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#include <linux/gpio/driver.h>
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@ -17,8 +16,9 @@
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#include <linux/module.h>
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#include <linux/moduleparam.h>
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#include <linux/spinlock.h>
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#include <linux/types.h>
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#define WS16C48_EXTENT 16
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#define WS16C48_EXTENT 10
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#define MAX_NUM_WS16C48 max_num_isa_dev(WS16C48_EXTENT)
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static unsigned int base[MAX_NUM_WS16C48];
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@ -30,6 +30,20 @@ static unsigned int irq[MAX_NUM_WS16C48];
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module_param_hw_array(irq, uint, irq, NULL, 0);
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MODULE_PARM_DESC(irq, "WinSystems WS16C48 interrupt line numbers");
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/**
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* struct ws16c48_reg - device register structure
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* @port: Port 0 through 5 I/O
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* @int_pending: Interrupt Pending
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* @page_lock: Register page (Bits 7-6) and I/O port lock (Bits 5-0)
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* @pol_enab_int_id: Interrupt polarity, enable, and ID
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*/
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struct ws16c48_reg {
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u8 port[6];
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u8 int_pending;
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u8 page_lock;
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u8 pol_enab_int_id[3];
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};
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/**
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* struct ws16c48_gpio - GPIO device private data structure
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* @chip: instance of the gpio_chip
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@ -38,7 +52,7 @@ MODULE_PARM_DESC(irq, "WinSystems WS16C48 interrupt line numbers");
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* @lock: synchronization lock to prevent I/O race conditions
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* @irq_mask: I/O bits affected by interrupts
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* @flow_mask: IRQ flow type mask for the respective I/O bits
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* @base: base port address of the GPIO device
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* @reg: I/O address offset for the device registers
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*/
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struct ws16c48_gpio {
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struct gpio_chip chip;
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@ -47,7 +61,7 @@ struct ws16c48_gpio {
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raw_spinlock_t lock;
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unsigned long irq_mask;
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unsigned long flow_mask;
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void __iomem *base;
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struct ws16c48_reg __iomem *reg;
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};
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static int ws16c48_gpio_get_direction(struct gpio_chip *chip, unsigned offset)
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@ -73,7 +87,7 @@ static int ws16c48_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
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ws16c48gpio->io_state[port] |= mask;
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ws16c48gpio->out_state[port] &= ~mask;
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iowrite8(ws16c48gpio->out_state[port], ws16c48gpio->base + port);
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iowrite8(ws16c48gpio->out_state[port], ws16c48gpio->reg->port + port);
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raw_spin_unlock_irqrestore(&ws16c48gpio->lock, flags);
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@ -95,7 +109,7 @@ static int ws16c48_gpio_direction_output(struct gpio_chip *chip,
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ws16c48gpio->out_state[port] |= mask;
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else
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ws16c48gpio->out_state[port] &= ~mask;
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iowrite8(ws16c48gpio->out_state[port], ws16c48gpio->base + port);
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iowrite8(ws16c48gpio->out_state[port], ws16c48gpio->reg->port + port);
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raw_spin_unlock_irqrestore(&ws16c48gpio->lock, flags);
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@ -118,7 +132,7 @@ static int ws16c48_gpio_get(struct gpio_chip *chip, unsigned offset)
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return -EINVAL;
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}
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port_state = ioread8(ws16c48gpio->base + port);
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port_state = ioread8(ws16c48gpio->reg->port + port);
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raw_spin_unlock_irqrestore(&ws16c48gpio->lock, flags);
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@ -131,14 +145,16 @@ static int ws16c48_gpio_get_multiple(struct gpio_chip *chip,
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struct ws16c48_gpio *const ws16c48gpio = gpiochip_get_data(chip);
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unsigned long offset;
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unsigned long gpio_mask;
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void __iomem *port_addr;
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size_t index;
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u8 __iomem *port_addr;
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unsigned long port_state;
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/* clear bits array to a clean slate */
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bitmap_zero(bits, chip->ngpio);
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for_each_set_clump8(offset, gpio_mask, mask, chip->ngpio) {
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port_addr = ws16c48gpio->base + offset / 8;
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index = offset / 8;
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port_addr = ws16c48gpio->reg->port + index;
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port_state = ioread8(port_addr) & gpio_mask;
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bitmap_set_value8(bits, port_state, offset);
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@ -166,7 +182,7 @@ static void ws16c48_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
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ws16c48gpio->out_state[port] |= mask;
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else
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ws16c48gpio->out_state[port] &= ~mask;
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iowrite8(ws16c48gpio->out_state[port], ws16c48gpio->base + port);
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iowrite8(ws16c48gpio->out_state[port], ws16c48gpio->reg->port + port);
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raw_spin_unlock_irqrestore(&ws16c48gpio->lock, flags);
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}
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@ -178,13 +194,13 @@ static void ws16c48_gpio_set_multiple(struct gpio_chip *chip,
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unsigned long offset;
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unsigned long gpio_mask;
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size_t index;
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void __iomem *port_addr;
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u8 __iomem *port_addr;
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unsigned long bitmask;
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unsigned long flags;
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for_each_set_clump8(offset, gpio_mask, mask, chip->ngpio) {
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index = offset / 8;
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port_addr = ws16c48gpio->base + index;
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port_addr = ws16c48gpio->reg->port + index;
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/* mask out GPIO configured for input */
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gpio_mask &= ~ws16c48gpio->io_state[index];
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@ -219,10 +235,15 @@ static void ws16c48_irq_ack(struct irq_data *data)
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port_state = ws16c48gpio->irq_mask >> (8*port);
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iowrite8(0x80, ws16c48gpio->base + 7);
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iowrite8(port_state & ~mask, ws16c48gpio->base + 8 + port);
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iowrite8(port_state | mask, ws16c48gpio->base + 8 + port);
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iowrite8(0xC0, ws16c48gpio->base + 7);
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/* Select Register Page 2; Unlock all I/O ports */
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iowrite8(0x80, &ws16c48gpio->reg->page_lock);
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/* Clear pending interrupt */
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iowrite8(port_state & ~mask, ws16c48gpio->reg->pol_enab_int_id + port);
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iowrite8(port_state | mask, ws16c48gpio->reg->pol_enab_int_id + port);
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/* Select Register Page 3; Unlock all I/O ports */
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iowrite8(0xC0, &ws16c48gpio->reg->page_lock);
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raw_spin_unlock_irqrestore(&ws16c48gpio->lock, flags);
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}
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@ -235,6 +256,7 @@ static void ws16c48_irq_mask(struct irq_data *data)
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const unsigned long mask = BIT(offset);
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const unsigned port = offset / 8;
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unsigned long flags;
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unsigned long port_state;
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/* only the first 3 ports support interrupts */
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if (port > 2)
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@ -243,10 +265,16 @@ static void ws16c48_irq_mask(struct irq_data *data)
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raw_spin_lock_irqsave(&ws16c48gpio->lock, flags);
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ws16c48gpio->irq_mask &= ~mask;
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port_state = ws16c48gpio->irq_mask >> (8 * port);
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iowrite8(0x80, ws16c48gpio->base + 7);
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iowrite8(ws16c48gpio->irq_mask >> (8*port), ws16c48gpio->base + 8 + port);
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iowrite8(0xC0, ws16c48gpio->base + 7);
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/* Select Register Page 2; Unlock all I/O ports */
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iowrite8(0x80, &ws16c48gpio->reg->page_lock);
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/* Disable interrupt */
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iowrite8(port_state, ws16c48gpio->reg->pol_enab_int_id + port);
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/* Select Register Page 3; Unlock all I/O ports */
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iowrite8(0xC0, &ws16c48gpio->reg->page_lock);
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raw_spin_unlock_irqrestore(&ws16c48gpio->lock, flags);
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}
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@ -259,6 +287,7 @@ static void ws16c48_irq_unmask(struct irq_data *data)
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const unsigned long mask = BIT(offset);
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const unsigned port = offset / 8;
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unsigned long flags;
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unsigned long port_state;
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/* only the first 3 ports support interrupts */
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if (port > 2)
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@ -267,10 +296,16 @@ static void ws16c48_irq_unmask(struct irq_data *data)
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raw_spin_lock_irqsave(&ws16c48gpio->lock, flags);
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ws16c48gpio->irq_mask |= mask;
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port_state = ws16c48gpio->irq_mask >> (8 * port);
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iowrite8(0x80, ws16c48gpio->base + 7);
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iowrite8(ws16c48gpio->irq_mask >> (8*port), ws16c48gpio->base + 8 + port);
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iowrite8(0xC0, ws16c48gpio->base + 7);
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/* Select Register Page 2; Unlock all I/O ports */
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iowrite8(0x80, &ws16c48gpio->reg->page_lock);
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/* Enable interrupt */
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iowrite8(port_state, ws16c48gpio->reg->pol_enab_int_id + port);
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/* Select Register Page 3; Unlock all I/O ports */
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iowrite8(0xC0, &ws16c48gpio->reg->page_lock);
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raw_spin_unlock_irqrestore(&ws16c48gpio->lock, flags);
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}
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@ -283,6 +318,7 @@ static int ws16c48_irq_set_type(struct irq_data *data, unsigned flow_type)
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const unsigned long mask = BIT(offset);
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const unsigned port = offset / 8;
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unsigned long flags;
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unsigned long port_state;
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/* only the first 3 ports support interrupts */
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if (port > 2)
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@ -304,9 +340,16 @@ static int ws16c48_irq_set_type(struct irq_data *data, unsigned flow_type)
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return -EINVAL;
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}
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iowrite8(0x40, ws16c48gpio->base + 7);
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iowrite8(ws16c48gpio->flow_mask >> (8*port), ws16c48gpio->base + 8 + port);
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iowrite8(0xC0, ws16c48gpio->base + 7);
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port_state = ws16c48gpio->flow_mask >> (8 * port);
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/* Select Register Page 1; Unlock all I/O ports */
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iowrite8(0x40, &ws16c48gpio->reg->page_lock);
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/* Set interrupt polarity */
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iowrite8(port_state, ws16c48gpio->reg->pol_enab_int_id + port);
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/* Select Register Page 3; Unlock all I/O ports */
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iowrite8(0xC0, &ws16c48gpio->reg->page_lock);
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raw_spin_unlock_irqrestore(&ws16c48gpio->lock, flags);
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@ -325,25 +368,26 @@ static irqreturn_t ws16c48_irq_handler(int irq, void *dev_id)
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{
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struct ws16c48_gpio *const ws16c48gpio = dev_id;
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struct gpio_chip *const chip = &ws16c48gpio->chip;
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struct ws16c48_reg __iomem *const reg = ws16c48gpio->reg;
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unsigned long int_pending;
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unsigned long port;
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unsigned long int_id;
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unsigned long gpio;
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int_pending = ioread8(ws16c48gpio->base + 6) & 0x7;
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int_pending = ioread8(®->int_pending) & 0x7;
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if (!int_pending)
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return IRQ_NONE;
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/* loop until all pending interrupts are handled */
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do {
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for_each_set_bit(port, &int_pending, 3) {
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int_id = ioread8(ws16c48gpio->base + 8 + port);
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int_id = ioread8(reg->pol_enab_int_id + port);
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for_each_set_bit(gpio, &int_id, 8)
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generic_handle_domain_irq(chip->irq.domain,
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gpio + 8*port);
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}
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int_pending = ioread8(ws16c48gpio->base + 6) & 0x7;
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int_pending = ioread8(®->int_pending) & 0x7;
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} while (int_pending);
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return IRQ_HANDLED;
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@ -369,12 +413,16 @@ static int ws16c48_irq_init_hw(struct gpio_chip *gc)
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{
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struct ws16c48_gpio *const ws16c48gpio = gpiochip_get_data(gc);
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/* Disable IRQ by default */
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iowrite8(0x80, ws16c48gpio->base + 7);
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iowrite8(0, ws16c48gpio->base + 8);
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iowrite8(0, ws16c48gpio->base + 9);
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iowrite8(0, ws16c48gpio->base + 10);
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iowrite8(0xC0, ws16c48gpio->base + 7);
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/* Select Register Page 2; Unlock all I/O ports */
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iowrite8(0x80, &ws16c48gpio->reg->page_lock);
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/* Disable interrupts for all lines */
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iowrite8(0, &ws16c48gpio->reg->pol_enab_int_id[0]);
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iowrite8(0, &ws16c48gpio->reg->pol_enab_int_id[1]);
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iowrite8(0, &ws16c48gpio->reg->pol_enab_int_id[2]);
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/* Select Register Page 3; Unlock all I/O ports */
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iowrite8(0xC0, &ws16c48gpio->reg->page_lock);
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return 0;
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}
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@ -396,8 +444,8 @@ static int ws16c48_probe(struct device *dev, unsigned int id)
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return -EBUSY;
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}
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ws16c48gpio->base = devm_ioport_map(dev, base[id], WS16C48_EXTENT);
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if (!ws16c48gpio->base)
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ws16c48gpio->reg = devm_ioport_map(dev, base[id], WS16C48_EXTENT);
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if (!ws16c48gpio->reg)
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return -ENOMEM;
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ws16c48gpio->chip.label = name;
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