clk: pxa: Remove CLK_IS_ROOT
This flag is a no-op now. Remove usage of the flag. Acked-by: Robert Jarzmik <robert.jarzmik@free.fr> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
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Родитель
615b34de1f
Коммит
2c63935dd6
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@ -200,12 +200,10 @@ static void __init pxa25x_register_core(void)
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static void __init pxa25x_register_plls(void)
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{
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clk_register_fixed_rate(NULL, "osc_3_6864mhz", NULL,
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CLK_GET_RATE_NOCACHE | CLK_IS_ROOT,
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3686400);
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CLK_GET_RATE_NOCACHE, 3686400);
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clk_register_fixed_rate(NULL, "osc_32_768khz", NULL,
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CLK_GET_RATE_NOCACHE | CLK_IS_ROOT,
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32768);
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clk_register_fixed_rate(NULL, "clk_dummy", NULL, CLK_IS_ROOT, 0);
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CLK_GET_RATE_NOCACHE, 32768);
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clk_register_fixed_rate(NULL, "clk_dummy", NULL, 0, 0);
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clk_register_fixed_factor(NULL, "ppll_95_85mhz", "osc_3_6864mhz",
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0, 26, 1);
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clk_register_fixed_factor(NULL, "ppll_147_46mhz", "osc_3_6864mhz",
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@ -208,12 +208,12 @@ MUX_RO_RATE_RO_OPS(clk_pxa27x_lcd_base, "lcd_base");
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static void __init pxa27x_register_plls(void)
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{
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clk_register_fixed_rate(NULL, "osc_13mhz", NULL,
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CLK_GET_RATE_NOCACHE | CLK_IS_ROOT,
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CLK_GET_RATE_NOCACHE,
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13 * MHz);
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clk_register_fixed_rate(NULL, "osc_32_768khz", NULL,
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CLK_GET_RATE_NOCACHE | CLK_IS_ROOT,
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CLK_GET_RATE_NOCACHE,
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32768 * KHz);
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clk_register_fixed_rate(NULL, "clk_dummy", NULL, CLK_IS_ROOT, 0);
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clk_register_fixed_rate(NULL, "clk_dummy", NULL, 0, 0);
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clk_register_fixed_factor(NULL, "ppll_312mhz", "osc_13mhz", 0, 24, 1);
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}
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@ -284,15 +284,15 @@ static void __init pxa3xx_register_core(void)
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static void __init pxa3xx_register_plls(void)
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{
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clk_register_fixed_rate(NULL, "osc_13mhz", NULL,
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CLK_GET_RATE_NOCACHE | CLK_IS_ROOT,
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CLK_GET_RATE_NOCACHE,
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13 * MHz);
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clk_register_fixed_rate(NULL, "osc_32_768khz", NULL,
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CLK_GET_RATE_NOCACHE | CLK_IS_ROOT,
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CLK_GET_RATE_NOCACHE,
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32768);
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clk_register_fixed_rate(NULL, "ring_osc_120mhz", NULL,
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CLK_GET_RATE_NOCACHE | CLK_IS_ROOT,
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CLK_GET_RATE_NOCACHE,
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120 * MHz);
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clk_register_fixed_rate(NULL, "clk_dummy", NULL, CLK_IS_ROOT, 0);
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clk_register_fixed_rate(NULL, "clk_dummy", NULL, 0, 0);
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clk_register_fixed_factor(NULL, "spll_624mhz", "osc_13mhz", 0, 48, 1);
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clk_register_fixed_factor(NULL, "ring_osc_60mhz", "ring_osc_120mhz",
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0, 1, 2);
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