powerpc/40x: Rework 40x PTE access and TLB miss
Commit1bc54c0311("powerpc: rework 4xx PTE access and TLB miss") reworked 44x PTE access to avoid atomic pte updates, and left 8xx, 40x and fsl booke with atomic pte updates. Commit6cfd8990e2("powerpc: rework FSL Book-E PTE access and TLB miss") removed atomic pte updates on fsl booke. It went away on 8xx with commitddfc20a3b9("powerpc/8xx: Remove PTE_ATOMIC_UPDATES"). 40x is the last platform setting PTE_ATOMIC_UPDATES. Rework PTE access and TLB miss to remove PTE_ATOMIC_UPDATES for 40x: - Always handle DSI as a fault. - Bail out of TLB miss handler when CONFIG_SWAP is set and _PAGE_ACCESSED is not set. - Bail out of ITLB miss handler when _PAGE_EXEC is not set. - Only set WR bit when both _PAGE_RW and _PAGE_DIRTY are set. - Remove _PAGE_HWWRITE - Don't require PTE_ATOMIC_UPDATES anymore Reported-by: kbuild test robot <lkp@intel.com> Signed-off-by: Christophe Leroy <christophe.leroy@c-s.fr> Signed-off-by: Michael Ellerman <mpe@ellerman.id.au> Link: https://lore.kernel.org/r/99a0fcd337ef67088140d1647d75fea026a70413.1590079968.git.christophe.leroy@csgroup.eu
This commit is contained in:
Christophe Leroy
Michael Ellerman
Родитель
f16dca3e30
Коммит
2c74e2586b
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@ -44,9 +44,8 @@
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#define _PAGE_WRITETHRU 0x008 /* W: caching is write-through */
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#define _PAGE_USER 0x010 /* matches one of the zone permission bits */
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#define _PAGE_SPECIAL 0x020 /* software: Special page */
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#define _PAGE_RW 0x040 /* software: Writes permitted */
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#define _PAGE_DIRTY 0x080 /* software: dirty page */
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#define _PAGE_HWWRITE 0x100 /* hardware: Dirty & RW, set in exception */
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#define _PAGE_RW 0x100 /* hardware: WR, anded with dirty in exception */
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#define _PAGE_EXEC 0x200 /* hardware: EX permission */
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#define _PAGE_ACCESSED 0x400 /* software: R: page referenced */
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@ -58,8 +57,8 @@
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#define _PAGE_KERNEL_RO 0
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#define _PAGE_KERNEL_ROX _PAGE_EXEC
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#define _PAGE_KERNEL_RW (_PAGE_DIRTY | _PAGE_RW | _PAGE_HWWRITE)
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#define _PAGE_KERNEL_RWX (_PAGE_DIRTY | _PAGE_RW | _PAGE_HWWRITE | _PAGE_EXEC)
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#define _PAGE_KERNEL_RW (_PAGE_DIRTY | _PAGE_RW)
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#define _PAGE_KERNEL_RWX (_PAGE_DIRTY | _PAGE_RW | _PAGE_EXEC)
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#define _PMD_PRESENT 0x400 /* PMD points to page of PTEs */
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#define _PMD_PRESENT_MASK _PMD_PRESENT
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@ -85,21 +84,5 @@
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#define PAGE_READONLY __pgprot(_PAGE_BASE | _PAGE_USER)
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#define PAGE_READONLY_X __pgprot(_PAGE_BASE | _PAGE_USER | _PAGE_EXEC)
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#ifndef __ASSEMBLY__
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static inline pte_t pte_wrprotect(pte_t pte)
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{
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return __pte(pte_val(pte) & ~(_PAGE_RW | _PAGE_HWWRITE));
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}
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#define pte_wrprotect pte_wrprotect
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static inline pte_t pte_mkclean(pte_t pte)
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{
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return __pte(pte_val(pte) & ~(_PAGE_DIRTY | _PAGE_HWWRITE));
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}
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#define pte_mkclean pte_mkclean
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#endif
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#endif /* __KERNEL__ */
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#endif /* _ASM_POWERPC_NOHASH_32_PTE_40x_H */
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@ -130,12 +130,10 @@ static inline pte_t pte_exprotect(pte_t pte)
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return __pte(pte_val(pte) & ~_PAGE_EXEC);
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}
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#ifndef pte_mkclean
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static inline pte_t pte_mkclean(pte_t pte)
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{
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return __pte(pte_val(pte) & ~_PAGE_DIRTY);
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}
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#endif
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static inline pte_t pte_mkold(pte_t pte)
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{
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@ -176,135 +176,16 @@ _ENTRY(saved_ksp_limit)
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* 0x0300 - Data Storage Exception
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* This happens for just a few reasons. U0 set (but we don't do that),
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* or zone protection fault (user violation, write to protected page).
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* If this is just an update of modified status, we do that quickly
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* and exit. Otherwise, we call heavywight functions to do the work.
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* The other Data TLB exceptions bail out to this point
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* if they can't resolve the lightweight TLB fault.
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*/
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START_EXCEPTION(0x0300, DataStorage)
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mtspr SPRN_SPRG_SCRATCH0, r10 /* Save some working registers */
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mtspr SPRN_SPRG_SCRATCH1, r11
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#ifdef CONFIG_403GCX
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stw r12, 0(r0)
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stw r9, 4(r0)
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mfcr r11
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mfspr r12, SPRN_PID
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stw r11, 8(r0)
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stw r12, 12(r0)
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#else
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mtspr SPRN_SPRG_SCRATCH3, r12
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mtspr SPRN_SPRG_SCRATCH4, r9
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mfcr r11
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mfspr r12, SPRN_PID
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mtspr SPRN_SPRG_SCRATCH6, r11
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mtspr SPRN_SPRG_SCRATCH5, r12
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#endif
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/* First, check if it was a zone fault (which means a user
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* tried to access a kernel or read-protected page - always
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* a SEGV). All other faults here must be stores, so no
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* need to check ESR_DST as well. */
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mfspr r10, SPRN_ESR
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andis. r10, r10, ESR_DIZ@h
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bne 2f
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mfspr r10, SPRN_DEAR /* Get faulting address */
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/* If we are faulting a kernel address, we have to use the
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* kernel page tables.
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*/
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lis r11, PAGE_OFFSET@h
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cmplw r10, r11
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blt+ 3f
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lis r11, swapper_pg_dir@h
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ori r11, r11, swapper_pg_dir@l
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li r9, 0
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mtspr SPRN_PID, r9 /* TLB will have 0 TID */
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b 4f
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/* Get the PGD for the current thread.
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*/
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3:
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mfspr r11,SPRN_SPRG_THREAD
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lwz r11,PGDIR(r11)
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4:
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tophys(r11, r11)
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rlwimi r11, r10, 12, 20, 29 /* Create L1 (pgdir/pmd) address */
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lwz r11, 0(r11) /* Get L1 entry */
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rlwinm. r12, r11, 0, 0, 19 /* Extract L2 (pte) base address */
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beq 2f /* Bail if no table */
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rlwimi r12, r10, 22, 20, 29 /* Compute PTE address */
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lwz r11, 0(r12) /* Get Linux PTE */
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andi. r9, r11, _PAGE_RW /* Is it writeable? */
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beq 2f /* Bail if not */
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/* Update 'changed'.
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*/
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ori r11, r11, _PAGE_DIRTY|_PAGE_ACCESSED|_PAGE_HWWRITE
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stw r11, 0(r12) /* Update Linux page table */
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/* Most of the Linux PTE is ready to load into the TLB LO.
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* We set ZSEL, where only the LS-bit determines user access.
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* We set execute, because we don't have the granularity to
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* properly set this at the page level (Linux problem).
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* If shared is set, we cause a zero PID->TID load.
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* Many of these bits are software only. Bits we don't set
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* here we (properly should) assume have the appropriate value.
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*/
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li r12, 0x0ce2
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andc r11, r11, r12 /* Make sure 20, 21 are zero */
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/* find the TLB index that caused the fault. It has to be here.
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*/
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tlbsx r9, 0, r10
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tlbwe r11, r9, TLB_DATA /* Load TLB LO */
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/* Done...restore registers and get out of here.
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*/
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#ifdef CONFIG_403GCX
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lwz r12, 12(r0)
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lwz r11, 8(r0)
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mtspr SPRN_PID, r12
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mtcr r11
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lwz r9, 4(r0)
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lwz r12, 0(r0)
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#else
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mfspr r12, SPRN_SPRG_SCRATCH5
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mfspr r11, SPRN_SPRG_SCRATCH6
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mtspr SPRN_PID, r12
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mtcr r11
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mfspr r9, SPRN_SPRG_SCRATCH4
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mfspr r12, SPRN_SPRG_SCRATCH3
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#endif
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mfspr r11, SPRN_SPRG_SCRATCH1
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mfspr r10, SPRN_SPRG_SCRATCH0
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PPC405_ERR77_SYNC
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rfi /* Should sync shadow TLBs */
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b . /* prevent prefetch past rfi */
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2:
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/* The bailout. Restore registers to pre-exception conditions
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* and call the heavyweights to help us out.
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*/
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#ifdef CONFIG_403GCX
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lwz r12, 12(r0)
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lwz r11, 8(r0)
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mtspr SPRN_PID, r12
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mtcr r11
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lwz r9, 4(r0)
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lwz r12, 0(r0)
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#else
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mfspr r12, SPRN_SPRG_SCRATCH5
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mfspr r11, SPRN_SPRG_SCRATCH6
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mtspr SPRN_PID, r12
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mtcr r11
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mfspr r9, SPRN_SPRG_SCRATCH4
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mfspr r12, SPRN_SPRG_SCRATCH3
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#endif
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mfspr r11, SPRN_SPRG_SCRATCH1
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mfspr r10, SPRN_SPRG_SCRATCH0
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b DataAccess
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EXCEPTION_PROLOG
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mfspr r5, SPRN_ESR /* Grab the ESR, save it, pass arg3 */
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stw r5, _ESR(r11)
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mfspr r4, SPRN_DEAR /* Grab the DEAR, save it, pass arg2 */
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stw r4, _DEAR(r11)
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EXC_XFER_LITE(0x300, handle_page_fault)
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/*
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* 0x0400 - Instruction Storage Exception
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@ -415,11 +296,17 @@ _ENTRY(saved_ksp_limit)
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rlwimi r12, r10, 22, 20, 29 /* Compute PTE address */
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lwz r11, 0(r12) /* Get Linux PTE */
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andi. r9, r11, _PAGE_PRESENT
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beq 5f
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#ifdef CONFIG_SWAP
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li r9, _PAGE_PRESENT | _PAGE_ACCESSED
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#else
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li r9, _PAGE_PRESENT
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#endif
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andc. r9, r9, r11 /* Check permission */
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bne 5f
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ori r11, r11, _PAGE_ACCESSED
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stw r11, 0(r12)
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rlwinm r9, r11, 1, _PAGE_RW /* dirty => rw */
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and r9, r9, r11 /* hwwrite = dirty & rw */
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rlwimi r11, r9, 0, _PAGE_RW /* replace rw by hwwrite */
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/* Create TLB tag. This is the faulting address plus a static
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* set of bits. These are size, valid, E, U0.
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@ -463,7 +350,7 @@ _ENTRY(saved_ksp_limit)
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#endif
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mfspr r11, SPRN_SPRG_SCRATCH1
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mfspr r10, SPRN_SPRG_SCRATCH0
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b DataAccess
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b DataStorage
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/* 0x1200 - Instruction TLB Miss Exception
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* Nearly the same as above, except we get our information from different
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@ -515,11 +402,17 @@ _ENTRY(saved_ksp_limit)
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rlwimi r12, r10, 22, 20, 29 /* Compute PTE address */
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lwz r11, 0(r12) /* Get Linux PTE */
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andi. r9, r11, _PAGE_PRESENT
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beq 5f
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#ifdef CONFIG_SWAP
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li r9, _PAGE_PRESENT | _PAGE_ACCESSED | _PAGE_EXEC
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#else
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li r9, _PAGE_PRESENT | _PAGE_EXEC
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#endif
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andc. r9, r9, r11 /* Check permission */
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bne 5f
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ori r11, r11, _PAGE_ACCESSED
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stw r11, 0(r12)
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rlwinm r9, r11, 1, _PAGE_RW /* dirty => rw */
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and r9, r9, r11 /* hwwrite = dirty & rw */
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rlwimi r11, r9, 0, _PAGE_RW /* replace rw by hwwrite */
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/* Create TLB tag. This is the faulting address plus a static
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* set of bits. These are size, valid, E, U0.
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@ -669,18 +562,6 @@ WDTException:
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(MSR_KERNEL & ~(MSR_ME|MSR_DE|MSR_CE)),
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crit_transfer_to_handler, ret_from_crit_exc)
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/*
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* The other Data TLB exceptions bail out to this point
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* if they can't resolve the lightweight TLB fault.
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*/
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DataAccess:
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EXCEPTION_PROLOG
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mfspr r5,SPRN_ESR /* Grab the ESR, save it, pass arg3 */
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stw r5,_ESR(r11)
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mfspr r4,SPRN_DEAR /* Grab the DEAR, save it, pass arg2 */
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stw r4, _DEAR(r11)
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EXC_XFER_LITE(0x300, handle_page_fault)
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/* Other PowerPC processors, namely those derived from the 6xx-series
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* have vectors from 0x2100 through 0x2F00 defined, but marked as reserved.
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* However, for the 4xx-series processors these are neither defined nor
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@ -102,7 +102,7 @@ unsigned long __init mmu_mapin_ram(unsigned long base, unsigned long top)
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while (s >= LARGE_PAGE_SIZE_16M) {
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pmd_t *pmdp;
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unsigned long val = p | _PMD_SIZE_16M | _PAGE_EXEC | _PAGE_HWWRITE;
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unsigned long val = p | _PMD_SIZE_16M | _PAGE_EXEC | _PAGE_RW;
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pmdp = pmd_ptr_k(v);
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*pmdp++ = __pmd(val);
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@ -117,7 +117,7 @@ unsigned long __init mmu_mapin_ram(unsigned long base, unsigned long top)
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while (s >= LARGE_PAGE_SIZE_4M) {
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pmd_t *pmdp;
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unsigned long val = p | _PMD_SIZE_4M | _PAGE_EXEC | _PAGE_HWWRITE;
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unsigned long val = p | _PMD_SIZE_4M | _PAGE_EXEC | _PAGE_RW;
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pmdp = pmd_ptr_k(v);
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*pmdp = __pmd(val);
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