selftests: kvm: Add basic Hyper-V clocksources tests
Introduce a new selftest for Hyper-V clocksources (MSR-based reference TSC and TSC page). As a starting point, test the following: 1) Reference TSC is 1Ghz clock. 2) Reference TSC and TSC page give the same reading. 3) TSC page gets updated upon KVM_SET_CLOCK call. 4) TSC page does not get updated when guest opted for reenlightenment. 5) Disabled TSC page doesn't get updated. Signed-off-by: Vitaly Kuznetsov <vkuznets@redhat.com> Message-Id: <20210318140949.1065740-1-vkuznets@redhat.com> [Add a host-side test using TSC + KVM_GET_MSR too. - Paolo] Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
This commit is contained in:
Vitaly Kuznetsov
Paolo Bonzini
Родитель
0469f2f7ab
Коммит
2c7f76b4c4
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@ -9,6 +9,7 @@
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/x86_64/evmcs_test
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/x86_64/get_cpuid_test
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/x86_64/kvm_pv_test
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/x86_64/hyperv_clock
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/x86_64/hyperv_cpuid
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/x86_64/mmio_warning_test
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/x86_64/platform_info_test
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@ -41,6 +41,7 @@ LIBKVM_s390x = lib/s390x/processor.c lib/s390x/ucall.c lib/s390x/diag318_test_ha
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TEST_GEN_PROGS_x86_64 = x86_64/cr4_cpuid_sync_test
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TEST_GEN_PROGS_x86_64 += x86_64/evmcs_test
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TEST_GEN_PROGS_x86_64 += x86_64/get_cpuid_test
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TEST_GEN_PROGS_x86_64 += x86_64/hyperv_clock
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TEST_GEN_PROGS_x86_64 += x86_64/hyperv_cpuid
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TEST_GEN_PROGS_x86_64 += x86_64/kvm_pv_test
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TEST_GEN_PROGS_x86_64 += x86_64/mmio_warning_test
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@ -0,0 +1,260 @@
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// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Copyright (C) 2021, Red Hat, Inc.
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*
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* Tests for Hyper-V clocksources
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*/
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#include "test_util.h"
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#include "kvm_util.h"
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#include "processor.h"
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struct ms_hyperv_tsc_page {
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volatile u32 tsc_sequence;
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u32 reserved1;
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volatile u64 tsc_scale;
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volatile s64 tsc_offset;
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} __packed;
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#define HV_X64_MSR_GUEST_OS_ID 0x40000000
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#define HV_X64_MSR_TIME_REF_COUNT 0x40000020
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#define HV_X64_MSR_REFERENCE_TSC 0x40000021
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#define HV_X64_MSR_TSC_FREQUENCY 0x40000022
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#define HV_X64_MSR_REENLIGHTENMENT_CONTROL 0x40000106
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#define HV_X64_MSR_TSC_EMULATION_CONTROL 0x40000107
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/* Simplified mul_u64_u64_shr() */
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static inline u64 mul_u64_u64_shr64(u64 a, u64 b)
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{
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union {
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u64 ll;
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struct {
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u32 low, high;
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} l;
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} rm, rn, rh, a0, b0;
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u64 c;
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a0.ll = a;
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b0.ll = b;
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rm.ll = (u64)a0.l.low * b0.l.high;
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rn.ll = (u64)a0.l.high * b0.l.low;
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rh.ll = (u64)a0.l.high * b0.l.high;
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rh.l.low = c = rm.l.high + rn.l.high + rh.l.low;
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rh.l.high = (c >> 32) + rh.l.high;
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return rh.ll;
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}
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static inline void nop_loop(void)
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{
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int i;
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for (i = 0; i < 1000000; i++)
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asm volatile("nop");
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}
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static inline void check_tsc_msr_rdtsc(void)
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{
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u64 tsc_freq, r1, r2, t1, t2;
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s64 delta_ns;
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tsc_freq = rdmsr(HV_X64_MSR_TSC_FREQUENCY);
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GUEST_ASSERT(tsc_freq > 0);
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/* First, check MSR-based clocksource */
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r1 = rdtsc();
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t1 = rdmsr(HV_X64_MSR_TIME_REF_COUNT);
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nop_loop();
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r2 = rdtsc();
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t2 = rdmsr(HV_X64_MSR_TIME_REF_COUNT);
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GUEST_ASSERT(r2 > r1 && t2 > t1);
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/* HV_X64_MSR_TIME_REF_COUNT is in 100ns */
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delta_ns = ((t2 - t1) * 100) - ((r2 - r1) * 1000000000 / tsc_freq);
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if (delta_ns < 0)
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delta_ns = -delta_ns;
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/* 1% tolerance */
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GUEST_ASSERT(delta_ns * 100 < (t2 - t1) * 100);
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}
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static inline void check_tsc_msr_tsc_page(struct ms_hyperv_tsc_page *tsc_page)
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{
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u64 r1, r2, t1, t2;
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/* Compare TSC page clocksource with HV_X64_MSR_TIME_REF_COUNT */
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t1 = mul_u64_u64_shr64(rdtsc(), tsc_page->tsc_scale) + tsc_page->tsc_offset;
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r1 = rdmsr(HV_X64_MSR_TIME_REF_COUNT);
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/* 10 ms tolerance */
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GUEST_ASSERT(r1 >= t1 && r1 - t1 < 100000);
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nop_loop();
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t2 = mul_u64_u64_shr64(rdtsc(), tsc_page->tsc_scale) + tsc_page->tsc_offset;
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r2 = rdmsr(HV_X64_MSR_TIME_REF_COUNT);
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GUEST_ASSERT(r2 >= t1 && r2 - t2 < 100000);
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}
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static void guest_main(struct ms_hyperv_tsc_page *tsc_page, vm_paddr_t tsc_page_gpa)
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{
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u64 tsc_scale, tsc_offset;
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/* Set Guest OS id to enable Hyper-V emulation */
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GUEST_SYNC(1);
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wrmsr(HV_X64_MSR_GUEST_OS_ID, (u64)0x8100 << 48);
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GUEST_SYNC(2);
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check_tsc_msr_rdtsc();
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GUEST_SYNC(3);
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/* Set up TSC page is disabled state, check that it's clean */
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wrmsr(HV_X64_MSR_REFERENCE_TSC, tsc_page_gpa);
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GUEST_ASSERT(tsc_page->tsc_sequence == 0);
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GUEST_ASSERT(tsc_page->tsc_scale == 0);
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GUEST_ASSERT(tsc_page->tsc_offset == 0);
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GUEST_SYNC(4);
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/* Set up TSC page is enabled state */
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wrmsr(HV_X64_MSR_REFERENCE_TSC, tsc_page_gpa | 0x1);
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GUEST_ASSERT(tsc_page->tsc_sequence != 0);
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GUEST_SYNC(5);
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check_tsc_msr_tsc_page(tsc_page);
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GUEST_SYNC(6);
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tsc_offset = tsc_page->tsc_offset;
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/* Call KVM_SET_CLOCK from userspace, check that TSC page was updated */
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GUEST_SYNC(7);
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GUEST_ASSERT(tsc_page->tsc_offset != tsc_offset);
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nop_loop();
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/*
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* Enable Re-enlightenment and check that TSC page stays constant across
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* KVM_SET_CLOCK.
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*/
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wrmsr(HV_X64_MSR_REENLIGHTENMENT_CONTROL, 0x1 << 16 | 0xff);
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wrmsr(HV_X64_MSR_TSC_EMULATION_CONTROL, 0x1);
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tsc_offset = tsc_page->tsc_offset;
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tsc_scale = tsc_page->tsc_scale;
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GUEST_SYNC(8);
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GUEST_ASSERT(tsc_page->tsc_offset == tsc_offset);
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GUEST_ASSERT(tsc_page->tsc_scale == tsc_scale);
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GUEST_SYNC(9);
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check_tsc_msr_tsc_page(tsc_page);
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/*
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* Disable re-enlightenment and TSC page, check that KVM doesn't update
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* it anymore.
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*/
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wrmsr(HV_X64_MSR_REENLIGHTENMENT_CONTROL, 0);
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wrmsr(HV_X64_MSR_TSC_EMULATION_CONTROL, 0);
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wrmsr(HV_X64_MSR_REFERENCE_TSC, 0);
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memset(tsc_page, 0, sizeof(*tsc_page));
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GUEST_SYNC(10);
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GUEST_ASSERT(tsc_page->tsc_sequence == 0);
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GUEST_ASSERT(tsc_page->tsc_offset == 0);
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GUEST_ASSERT(tsc_page->tsc_scale == 0);
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GUEST_DONE();
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}
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#define VCPU_ID 0
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static void host_check_tsc_msr_rdtsc(struct kvm_vm *vm)
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{
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u64 tsc_freq, r1, r2, t1, t2;
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s64 delta_ns;
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tsc_freq = vcpu_get_msr(vm, VCPU_ID, HV_X64_MSR_TSC_FREQUENCY);
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TEST_ASSERT(tsc_freq > 0, "TSC frequency must be nonzero");
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/* First, check MSR-based clocksource */
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r1 = rdtsc();
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t1 = vcpu_get_msr(vm, VCPU_ID, HV_X64_MSR_TIME_REF_COUNT);
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nop_loop();
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r2 = rdtsc();
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t2 = vcpu_get_msr(vm, VCPU_ID, HV_X64_MSR_TIME_REF_COUNT);
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TEST_ASSERT(t2 > t1, "Time reference MSR is not monotonic (%ld <= %ld)", t1, t2);
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/* HV_X64_MSR_TIME_REF_COUNT is in 100ns */
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delta_ns = ((t2 - t1) * 100) - ((r2 - r1) * 1000000000 / tsc_freq);
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if (delta_ns < 0)
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delta_ns = -delta_ns;
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/* 1% tolerance */
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TEST_ASSERT(delta_ns * 100 < (t2 - t1) * 100,
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"Elapsed time does not match (MSR=%ld, TSC=%ld)",
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(t2 - t1) * 100, (r2 - r1) * 1000000000 / tsc_freq);
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}
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int main(void)
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{
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struct kvm_vm *vm;
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struct kvm_run *run;
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struct ucall uc;
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vm_vaddr_t tsc_page_gva;
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int stage;
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vm = vm_create_default(VCPU_ID, 0, guest_main);
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run = vcpu_state(vm, VCPU_ID);
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vcpu_set_hv_cpuid(vm, VCPU_ID);
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tsc_page_gva = vm_vaddr_alloc(vm, getpagesize(), 0x10000, 0, 0);
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memset(addr_gpa2hva(vm, tsc_page_gva), 0x0, getpagesize());
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TEST_ASSERT((addr_gva2gpa(vm, tsc_page_gva) & (getpagesize() - 1)) == 0,
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"TSC page has to be page aligned\n");
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vcpu_args_set(vm, VCPU_ID, 2, tsc_page_gva, addr_gva2gpa(vm, tsc_page_gva));
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host_check_tsc_msr_rdtsc(vm);
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for (stage = 1;; stage++) {
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_vcpu_run(vm, VCPU_ID);
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TEST_ASSERT(run->exit_reason == KVM_EXIT_IO,
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"Stage %d: unexpected exit reason: %u (%s),\n",
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stage, run->exit_reason,
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exit_reason_str(run->exit_reason));
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switch (get_ucall(vm, VCPU_ID, &uc)) {
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case UCALL_ABORT:
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TEST_FAIL("%s at %s:%ld", (const char *)uc.args[0],
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__FILE__, uc.args[1]);
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/* NOT REACHED */
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case UCALL_SYNC:
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break;
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case UCALL_DONE:
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/* Keep in sync with guest_main() */
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TEST_ASSERT(stage == 11, "Testing ended prematurely, stage %d\n",
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stage);
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goto out;
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default:
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TEST_FAIL("Unknown ucall %lu", uc.cmd);
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}
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TEST_ASSERT(!strcmp((const char *)uc.args[0], "hello") &&
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uc.args[1] == stage,
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"Stage %d: Unexpected register values vmexit, got %lx",
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stage, (ulong)uc.args[1]);
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/* Reset kvmclock triggering TSC page update */
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if (stage == 7 || stage == 8 || stage == 10) {
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struct kvm_clock_data clock = {0};
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vm_ioctl(vm, KVM_SET_CLOCK, &clock);
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}
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}
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out:
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kvm_vm_free(vm);
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}
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