drm/bridge/sii8620: initial support for eCBUS-S mode
The Single-ended eCBUS Mode (eCBUS-S) mode provides 60 Mb/s full-duplex bidirectional traffic for three channels: - CBUS data (CBUS1 channel), - High-bandwidth MHL data (eMSC channel), - tunneling data (T-CBUS channel). It is required to fully support MHL3 dongles. Signed-off-by: Andrzej Hajda <a.hajda@samsung.com> Signed-off-by: Archit Taneja <architt@codeaurora.org> Link: http://patchwork.freedesktop.org/patch/msgid/1485935272-17337-6-git-send-email-a.hajda@samsung.com
This commit is contained in:
Andrzej Hajda
Archit Taneja
Родитель
0c2d18756b
Коммит
2c8fb853c0
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@ -104,6 +104,7 @@ static void sii8620_fetch_edid(struct sii8620 *ctx);
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static void sii8620_set_upstream_edid(struct sii8620 *ctx);
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static void sii8620_enable_hpd(struct sii8620 *ctx);
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static void sii8620_mhl_disconnected(struct sii8620 *ctx);
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static void sii8620_disconnect(struct sii8620 *ctx);
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static int sii8620_clear_error(struct sii8620 *ctx)
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{
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@ -1016,13 +1017,44 @@ static void sii8620_mhl_init(struct sii8620 *ctx)
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sii8620_mt_set_int(ctx, MHL_INT_REG(RCHANGE), MHL_INT_RC_DCAP_CHG);
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}
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static void sii8620_emsc_enable(struct sii8620 *ctx)
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{
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u8 reg;
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sii8620_setbits(ctx, REG_GENCTL, BIT_GENCTL_EMSC_EN
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| BIT_GENCTL_CLR_EMSC_RFIFO
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| BIT_GENCTL_CLR_EMSC_XFIFO, ~0);
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sii8620_setbits(ctx, REG_GENCTL, BIT_GENCTL_CLR_EMSC_RFIFO
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| BIT_GENCTL_CLR_EMSC_XFIFO, 0);
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sii8620_setbits(ctx, REG_COMMECNT, BIT_COMMECNT_I2C_TO_EMSC_EN, ~0);
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reg = sii8620_readb(ctx, REG_EMSCINTR);
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sii8620_write(ctx, REG_EMSCINTR, reg);
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sii8620_write(ctx, REG_EMSCINTRMASK, BIT_EMSCINTR_SPI_DVLD);
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}
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static int sii8620_wait_for_fsm_state(struct sii8620 *ctx, u8 state)
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{
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int i;
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for (i = 0; i < 10; ++i) {
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u8 s = sii8620_readb(ctx, REG_COC_STAT_0);
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if ((s & MSK_COC_STAT_0_FSM_STATE) == state)
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return 0;
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if (!(s & BIT_COC_STAT_0_PLL_LOCKED))
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return -EBUSY;
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usleep_range(4000, 6000);
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}
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return -ETIMEDOUT;
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}
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static void sii8620_set_mode(struct sii8620 *ctx, enum sii8620_mode mode)
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{
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int ret;
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if (ctx->mode == mode)
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return;
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ctx->mode = mode;
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switch (mode) {
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case CM_MHL1:
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sii8620_write_seq_static(ctx,
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@ -1032,11 +1064,46 @@ static void sii8620_set_mode(struct sii8620 *ctx, enum sii8620_mode mode)
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| BIT_DPD_OSC_EN,
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REG_COC_INTR_MASK, 0
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);
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ctx->mode = mode;
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break;
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case CM_MHL3:
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sii8620_write(ctx, REG_M3_CTRL, VAL_M3_CTRL_MHL3_VALUE);
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ctx->mode = mode;
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return;
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case CM_ECBUS_S:
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sii8620_emsc_enable(ctx);
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sii8620_write_seq_static(ctx,
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REG_TTXSPINUMS, 4,
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REG_TRXSPINUMS, 4,
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REG_TTXHSICNUMS, 0x14,
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REG_TRXHSICNUMS, 0x14,
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REG_TTXTOTNUMS, 0x18,
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REG_TRXTOTNUMS, 0x18,
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REG_PWD_SRST, BIT_PWD_SRST_COC_DOC_RST
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| BIT_PWD_SRST_CBUS_RST_SW_EN,
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REG_MHL_COC_CTL1, 0xbd,
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REG_PWD_SRST, BIT_PWD_SRST_CBUS_RST_SW_EN,
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REG_COC_CTLB, 0x01,
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REG_COC_CTL0, 0x5c,
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REG_COC_CTL14, 0x03,
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REG_COC_CTL15, 0x80,
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REG_MHL_DP_CTL6, BIT_MHL_DP_CTL6_DP_TAP1_SGN
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| BIT_MHL_DP_CTL6_DP_TAP1_EN
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| BIT_MHL_DP_CTL6_DT_PREDRV_FEEDCAP_EN,
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REG_MHL_DP_CTL8, 0x03
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);
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ret = sii8620_wait_for_fsm_state(ctx, 0x03);
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sii8620_write_seq_static(ctx,
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REG_COC_CTL14, 0x00,
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REG_COC_CTL15, 0x80
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);
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if (!ret)
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sii8620_write(ctx, REG_CBUS3_CNVT, 0x85);
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else
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sii8620_disconnect(ctx);
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return;
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case CM_DISCONNECTED:
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ctx->mode = mode;
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break;
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default:
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dev_err(ctx->dev, "%s mode %d not supported\n", __func__, mode);
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@ -1229,12 +1296,45 @@ static void sii8620_msc_mr_write_stat(struct sii8620 *ctx)
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sii8620_status_changed_path(ctx);
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}
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static void sii8620_ecbus_up(struct sii8620 *ctx, int ret)
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{
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if (ret < 0)
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return;
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sii8620_set_mode(ctx, CM_ECBUS_S);
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}
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static void sii8620_got_ecbus_speed(struct sii8620 *ctx, int ret)
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{
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if (ret < 0)
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return;
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sii8620_mt_write_stat(ctx, MHL_XDS_REG(CURR_ECBUS_MODE),
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MHL_XDS_ECBUS_S | MHL_XDS_SLOT_MODE_8BIT);
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sii8620_mt_rap(ctx, MHL_RAP_CBUS_MODE_UP);
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sii8620_mt_set_cont(ctx, sii8620_ecbus_up);
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}
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static void sii8620_msc_mr_set_int(struct sii8620 *ctx)
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{
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u8 ints[MHL_INT_SIZE];
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sii8620_read_buf(ctx, REG_MHL_INT_0, ints, MHL_INT_SIZE);
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sii8620_write_buf(ctx, REG_MHL_INT_0, ints, MHL_INT_SIZE);
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if (ints[MHL_INT_RCHANGE] & MHL_INT_RC_DCAP_CHG) {
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switch (ctx->mode) {
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case CM_MHL3:
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sii8620_mt_read_xdevcap_reg(ctx, MHL_XDC_ECBUS_SPEEDS);
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sii8620_mt_set_cont(ctx, sii8620_got_ecbus_speed);
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break;
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case CM_ECBUS_S:
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sii8620_mt_read_devcap(ctx, true);
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break;
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default:
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break;
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}
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}
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}
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static struct sii8620_mt_msg *sii8620_msc_msg_first(struct sii8620 *ctx)
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@ -841,6 +841,8 @@
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#define MSK_MHL_DP_CTL7_DT_DRV_VBIAS_CASCTL 0xf0
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#define MSK_MHL_DP_CTL7_DT_DRV_IREF_CTL 0x0f
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#define REG_MHL_DP_CTL8 0x0352
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/* Tx Zone Ctl1, default value: 0x00 */
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#define REG_TX_ZONE_CTL1 0x0361
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#define VAL_TX_ZONE_CTL1_TX_ZONE_CTRL_MODE 0x08
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@ -1088,6 +1090,9 @@
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/* CoC Status, default value: 0x00 */
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#define REG_COC_STAT_0 0x0700
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#define BIT_COC_STAT_0_PLL_LOCKED BIT(7)
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#define MSK_COC_STAT_0_FSM_STATE 0x0f
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#define REG_COC_STAT_1 0x0701
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#define REG_COC_STAT_2 0x0702
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#define REG_COC_STAT_3 0x0703
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