powerpc/powernv: Capture actag information for the device
In the opencapi protocol, host memory contexts are referenced by a 'actag'. During setup, a driver must tell the device how many actags it can used, and what values are acceptable. On POWER9, the NPU can handle 64 actags per link, so they must be shared between all the PCI functions of the link. To get a global picture of how many actags are used by each AFU of every function, we capture some data at the end of PCI enumeration, so that actags can be shared fairly if needed. This is not powernv specific per say, but rather a consequence of the opencapi configuration specification being quite general. The number of available actags on POWER9 makes it more likely to be hit. This is somewhat mitigated by the fact that existing AFUs are coded by requesting a reasonable count of actags and existing devices carry only one AFU. Signed-off-by: Frederic Barrat <fbarrat@linux.vnet.ibm.com> Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
This commit is contained in:
Frederic Barrat
Michael Ellerman
Родитель
6914c75711
Коммит
2cb3d64b26
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@ -9,6 +9,10 @@
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#define PNV_OCXL_TL_BITS_PER_RATE 4
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#define PNV_OCXL_TL_RATE_BUF_SIZE ((PNV_OCXL_TL_MAX_TEMPLATE+1) * PNV_OCXL_TL_BITS_PER_RATE / 8)
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extern int pnv_ocxl_get_actag(struct pci_dev *dev, u16 *base, u16 *enabled,
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u16 *supported);
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extern int pnv_ocxl_get_pasid_count(struct pci_dev *dev, int *count);
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extern int pnv_ocxl_get_tl_cap(struct pci_dev *dev, long *cap,
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char *rate_buf, int rate_buf_size);
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extern int pnv_ocxl_set_tl_conf(struct pci_dev *dev, long cap,
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@ -2,13 +2,318 @@
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// Copyright 2017 IBM Corp.
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#include <asm/pnv-ocxl.h>
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#include <asm/opal.h>
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#include <misc/ocxl-config.h>
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#include "pci.h"
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#define PNV_OCXL_TL_P9_RECV_CAP 0x000000000000000Full
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#define PNV_OCXL_ACTAG_MAX 64
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/* PASIDs are 20-bit, but on P9, NPU can only handle 15 bits */
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#define PNV_OCXL_PASID_BITS 15
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#define PNV_OCXL_PASID_MAX ((1 << PNV_OCXL_PASID_BITS) - 1)
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#define AFU_PRESENT (1 << 31)
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#define AFU_INDEX_MASK 0x3F000000
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#define AFU_INDEX_SHIFT 24
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#define ACTAG_MASK 0xFFF
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struct actag_range {
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u16 start;
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u16 count;
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};
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struct npu_link {
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struct list_head list;
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int domain;
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int bus;
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int dev;
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u16 fn_desired_actags[8];
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struct actag_range fn_actags[8];
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bool assignment_done;
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};
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static struct list_head links_list = LIST_HEAD_INIT(links_list);
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static DEFINE_MUTEX(links_list_lock);
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/*
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* opencapi actags handling:
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*
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* When sending commands, the opencapi device references the memory
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* context it's targeting with an 'actag', which is really an alias
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* for a (BDF, pasid) combination. When it receives a command, the NPU
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* must do a lookup of the actag to identify the memory context. The
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* hardware supports a finite number of actags per link (64 for
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* POWER9).
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*
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* The device can carry multiple functions, and each function can have
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* multiple AFUs. Each AFU advertises in its config space the number
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* of desired actags. The host must configure in the config space of
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* the AFU how many actags the AFU is really allowed to use (which can
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* be less than what the AFU desires).
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*
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* When a PCI function is probed by the driver, it has no visibility
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* about the other PCI functions and how many actags they'd like,
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* which makes it impossible to distribute actags fairly among AFUs.
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*
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* Unfortunately, the only way to know how many actags a function
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* desires is by looking at the data for each AFU in the config space
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* and add them up. Similarly, the only way to know how many actags
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* all the functions of the physical device desire is by adding the
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* previously computed function counts. Then we can match that against
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* what the hardware supports.
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*
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* To get a comprehensive view, we use a 'pci fixup': at the end of
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* PCI enumeration, each function counts how many actags its AFUs
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* desire and we save it in a 'npu_link' structure, shared between all
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* the PCI functions of a same device. Therefore, when the first
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* function is probed by the driver, we can get an idea of the total
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* count of desired actags for the device, and assign the actags to
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* the AFUs, by pro-rating if needed.
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*/
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static int find_dvsec_from_pos(struct pci_dev *dev, int dvsec_id, int pos)
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{
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int vsec = pos;
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u16 vendor, id;
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while ((vsec = pci_find_next_ext_capability(dev, vsec,
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OCXL_EXT_CAP_ID_DVSEC))) {
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pci_read_config_word(dev, vsec + OCXL_DVSEC_VENDOR_OFFSET,
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&vendor);
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pci_read_config_word(dev, vsec + OCXL_DVSEC_ID_OFFSET, &id);
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if (vendor == PCI_VENDOR_ID_IBM && id == dvsec_id)
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return vsec;
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}
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return 0;
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}
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static int find_dvsec_afu_ctrl(struct pci_dev *dev, u8 afu_idx)
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{
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int vsec = 0;
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u8 idx;
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while ((vsec = find_dvsec_from_pos(dev, OCXL_DVSEC_AFU_CTRL_ID,
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vsec))) {
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pci_read_config_byte(dev, vsec + OCXL_DVSEC_AFU_CTRL_AFU_IDX,
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&idx);
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if (idx == afu_idx)
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return vsec;
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}
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return 0;
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}
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static int get_max_afu_index(struct pci_dev *dev, int *afu_idx)
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{
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int pos;
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u32 val;
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pos = find_dvsec_from_pos(dev, OCXL_DVSEC_FUNC_ID, 0);
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if (!pos)
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return -ESRCH;
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pci_read_config_dword(dev, pos + OCXL_DVSEC_FUNC_OFF_INDEX, &val);
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if (val & AFU_PRESENT)
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*afu_idx = (val & AFU_INDEX_MASK) >> AFU_INDEX_SHIFT;
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else
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*afu_idx = -1;
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return 0;
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}
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static int get_actag_count(struct pci_dev *dev, int afu_idx, int *actag)
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{
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int pos;
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u16 actag_sup;
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pos = find_dvsec_afu_ctrl(dev, afu_idx);
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if (!pos)
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return -ESRCH;
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pci_read_config_word(dev, pos + OCXL_DVSEC_AFU_CTRL_ACTAG_SUP,
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&actag_sup);
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*actag = actag_sup & ACTAG_MASK;
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return 0;
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}
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static struct npu_link *find_link(struct pci_dev *dev)
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{
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struct npu_link *link;
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list_for_each_entry(link, &links_list, list) {
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/* The functions of a device all share the same link */
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if (link->domain == pci_domain_nr(dev->bus) &&
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link->bus == dev->bus->number &&
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link->dev == PCI_SLOT(dev->devfn)) {
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return link;
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}
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}
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/* link doesn't exist yet. Allocate one */
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link = kzalloc(sizeof(struct npu_link), GFP_KERNEL);
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if (!link)
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return NULL;
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link->domain = pci_domain_nr(dev->bus);
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link->bus = dev->bus->number;
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link->dev = PCI_SLOT(dev->devfn);
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list_add(&link->list, &links_list);
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return link;
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}
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static void pnv_ocxl_fixup_actag(struct pci_dev *dev)
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{
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struct pci_controller *hose = pci_bus_to_host(dev->bus);
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struct pnv_phb *phb = hose->private_data;
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struct npu_link *link;
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int rc, afu_idx = -1, i, actag;
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if (!machine_is(powernv))
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return;
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if (phb->type != PNV_PHB_NPU_OCAPI)
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return;
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mutex_lock(&links_list_lock);
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link = find_link(dev);
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if (!link) {
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dev_warn(&dev->dev, "couldn't update actag information\n");
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mutex_unlock(&links_list_lock);
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return;
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}
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/*
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* Check how many actags are desired for the AFUs under that
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* function and add it to the count for the link
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*/
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rc = get_max_afu_index(dev, &afu_idx);
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if (rc) {
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/* Most likely an invalid config space */
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dev_dbg(&dev->dev, "couldn't find AFU information\n");
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afu_idx = -1;
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}
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link->fn_desired_actags[PCI_FUNC(dev->devfn)] = 0;
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for (i = 0; i <= afu_idx; i++) {
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/*
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* AFU index 'holes' are allowed. So don't fail if we
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* can't read the actag info for an index
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*/
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rc = get_actag_count(dev, i, &actag);
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if (rc)
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continue;
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link->fn_desired_actags[PCI_FUNC(dev->devfn)] += actag;
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}
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dev_dbg(&dev->dev, "total actags for function: %d\n",
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link->fn_desired_actags[PCI_FUNC(dev->devfn)]);
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mutex_unlock(&links_list_lock);
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}
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DECLARE_PCI_FIXUP_HEADER(PCI_ANY_ID, PCI_ANY_ID, pnv_ocxl_fixup_actag);
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static u16 assign_fn_actags(u16 desired, u16 total)
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{
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u16 count;
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if (total <= PNV_OCXL_ACTAG_MAX)
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count = desired;
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else
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count = PNV_OCXL_ACTAG_MAX * desired / total;
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return count;
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}
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static void assign_actags(struct npu_link *link)
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{
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u16 actag_count, range_start = 0, total_desired = 0;
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int i;
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for (i = 0; i < 8; i++)
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total_desired += link->fn_desired_actags[i];
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for (i = 0; i < 8; i++) {
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if (link->fn_desired_actags[i]) {
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actag_count = assign_fn_actags(
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link->fn_desired_actags[i],
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total_desired);
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link->fn_actags[i].start = range_start;
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link->fn_actags[i].count = actag_count;
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range_start += actag_count;
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WARN_ON(range_start >= PNV_OCXL_ACTAG_MAX);
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}
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pr_debug("link %x:%x:%x fct %d actags: start=%d count=%d (desired=%d)\n",
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link->domain, link->bus, link->dev, i,
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link->fn_actags[i].start, link->fn_actags[i].count,
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link->fn_desired_actags[i]);
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}
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link->assignment_done = true;
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}
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int pnv_ocxl_get_actag(struct pci_dev *dev, u16 *base, u16 *enabled,
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u16 *supported)
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{
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struct npu_link *link;
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mutex_lock(&links_list_lock);
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link = find_link(dev);
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if (!link) {
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dev_err(&dev->dev, "actag information not found\n");
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mutex_unlock(&links_list_lock);
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return -ENODEV;
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}
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/*
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* On p9, we only have 64 actags per link, so they must be
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* shared by all the functions of the same adapter. We counted
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* the desired actag counts during PCI enumeration, so that we
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* can allocate a pro-rated number of actags to each function.
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*/
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if (!link->assignment_done)
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assign_actags(link);
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*base = link->fn_actags[PCI_FUNC(dev->devfn)].start;
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*enabled = link->fn_actags[PCI_FUNC(dev->devfn)].count;
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*supported = link->fn_desired_actags[PCI_FUNC(dev->devfn)];
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mutex_unlock(&links_list_lock);
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return 0;
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}
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EXPORT_SYMBOL_GPL(pnv_ocxl_get_actag);
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int pnv_ocxl_get_pasid_count(struct pci_dev *dev, int *count)
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{
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struct npu_link *link;
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int i, rc = -EINVAL;
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/*
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* The number of PASIDs (process address space ID) which can
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* be used by a function depends on how many functions exist
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* on the device. The NPU needs to be configured to know how
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* many bits are available to PASIDs and how many are to be
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* used by the function BDF indentifier.
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*
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* We only support one AFU-carrying function for now.
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*/
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mutex_lock(&links_list_lock);
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link = find_link(dev);
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if (!link) {
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dev_err(&dev->dev, "actag information not found\n");
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mutex_unlock(&links_list_lock);
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return -ENODEV;
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}
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for (i = 0; i < 8; i++)
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if (link->fn_desired_actags[i] && (i == PCI_FUNC(dev->devfn))) {
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*count = PNV_OCXL_PASID_MAX;
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rc = 0;
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break;
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}
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mutex_unlock(&links_list_lock);
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dev_dbg(&dev->dev, "%d PASIDs available for function\n",
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rc ? 0 : *count);
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return rc;
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}
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EXPORT_SYMBOL_GPL(pnv_ocxl_get_pasid_count);
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static void set_templ_rate(unsigned int templ, unsigned int rate, char *buf)
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{
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@ -0,0 +1,45 @@
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// SPDX-License-Identifier: GPL-2.0+
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// Copyright 2017 IBM Corp.
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#ifndef _OCXL_CONFIG_H_
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#define _OCXL_CONFIG_H_
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/*
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* This file lists the various constants used to read the
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* configuration space of an opencapi adapter.
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*
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* It follows the specification for opencapi 3.0
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*/
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#define OCXL_EXT_CAP_ID_DVSEC 0x23
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#define OCXL_DVSEC_VENDOR_OFFSET 0x4
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#define OCXL_DVSEC_ID_OFFSET 0x8
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#define OCXL_DVSEC_TL_ID 0xF000
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#define OCXL_DVSEC_TL_BACKOFF_TIMERS 0x10
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#define OCXL_DVSEC_TL_RECV_CAP 0x18
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#define OCXL_DVSEC_TL_SEND_CAP 0x20
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#define OCXL_DVSEC_TL_RECV_RATE 0x30
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#define OCXL_DVSEC_TL_SEND_RATE 0x50
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#define OCXL_DVSEC_FUNC_ID 0xF001
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#define OCXL_DVSEC_FUNC_OFF_INDEX 0x08
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#define OCXL_DVSEC_FUNC_OFF_ACTAG 0x0C
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#define OCXL_DVSEC_AFU_INFO_ID 0xF003
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#define OCXL_DVSEC_AFU_INFO_AFU_IDX 0x0A
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#define OCXL_DVSEC_AFU_INFO_OFF 0x0C
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#define OCXL_DVSEC_AFU_INFO_DATA 0x10
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#define OCXL_DVSEC_AFU_CTRL_ID 0xF004
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#define OCXL_DVSEC_AFU_CTRL_AFU_IDX 0x0A
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#define OCXL_DVSEC_AFU_CTRL_TERM_PASID 0x0C
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#define OCXL_DVSEC_AFU_CTRL_ENABLE 0x0F
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#define OCXL_DVSEC_AFU_CTRL_PASID_SUP 0x10
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#define OCXL_DVSEC_AFU_CTRL_PASID_EN 0x11
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#define OCXL_DVSEC_AFU_CTRL_PASID_BASE 0x14
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#define OCXL_DVSEC_AFU_CTRL_ACTAG_SUP 0x18
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#define OCXL_DVSEC_AFU_CTRL_ACTAG_EN 0x1A
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#define OCXL_DVSEC_AFU_CTRL_ACTAG_BASE 0x1C
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#define OCXL_DVSEC_VENDOR_ID 0xF0F0
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#define OCXL_DVSEC_VENDOR_CFG_VERS 0x0C
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#define OCXL_DVSEC_VENDOR_TLX_VERS 0x10
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#define OCXL_DVSEC_VENDOR_DLX_VERS 0x20
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#endif /* _OCXL_CONFIG_H_ */
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