[PATCH] skge: add mii ioctl support
Basic MII ioctl support for skge driver. Signed-off-by: Stephen Hemminger <shemminger@osdl.org> Signed-off-by: Jeff Garzik <jgarzik@pobox.com>
This commit is contained in:
Stephen Hemminger
Jeff Garzik
Родитель
7e86306113
Коммит
2cd8e5d365
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@ -37,6 +37,7 @@
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#include <linux/delay.h>
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#include <linux/crc32.h>
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#include <linux/dma-mapping.h>
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#include <linux/mii.h>
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#include <asm/irq.h>
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#include "skge.h"
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@ -88,8 +89,8 @@ MODULE_DEVICE_TABLE(pci, skge_id_table);
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static int skge_up(struct net_device *dev);
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static int skge_down(struct net_device *dev);
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static void skge_tx_clean(struct skge_port *skge);
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static void xm_phy_write(struct skge_hw *hw, int port, u16 reg, u16 val);
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static void gm_phy_write(struct skge_hw *hw, int port, u16 reg, u16 val);
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static int xm_phy_write(struct skge_hw *hw, int port, u16 reg, u16 val);
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static int gm_phy_write(struct skge_hw *hw, int port, u16 reg, u16 val);
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static void genesis_get_stats(struct skge_port *skge, u64 *data);
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static void yukon_get_stats(struct skge_port *skge, u64 *data);
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static void yukon_init(struct skge_hw *hw, int port);
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@ -883,32 +884,37 @@ static void skge_link_down(struct skge_port *skge)
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printk(KERN_INFO PFX "%s: Link is down.\n", skge->netdev->name);
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}
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static u16 xm_phy_read(struct skge_hw *hw, int port, u16 reg)
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static int __xm_phy_read(struct skge_hw *hw, int port, u16 reg, u16 *val)
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{
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int i;
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u16 v;
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xm_write16(hw, port, XM_PHY_ADDR, reg | hw->phy_addr);
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v = xm_read16(hw, port, XM_PHY_DATA);
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xm_read16(hw, port, XM_PHY_DATA);
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/* Need to wait for external PHY */
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for (i = 0; i < PHY_RETRIES; i++) {
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udelay(1);
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if (xm_read16(hw, port, XM_MMU_CMD)
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& XM_MMU_PHY_RDY)
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if (xm_read16(hw, port, XM_MMU_CMD) & XM_MMU_PHY_RDY)
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goto ready;
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}
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return -ETIMEDOUT;
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ready:
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*val = xm_read16(hw, port, XM_PHY_DATA);
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return 0;
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}
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static u16 xm_phy_read(struct skge_hw *hw, int port, u16 reg)
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{
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u16 v = 0;
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if (__xm_phy_read(hw, port, reg, &v))
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printk(KERN_WARNING PFX "%s: phy read timed out\n",
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hw->dev[port]->name);
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return 0;
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ready:
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v = xm_read16(hw, port, XM_PHY_DATA);
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return v;
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}
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static void xm_phy_write(struct skge_hw *hw, int port, u16 reg, u16 val)
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static int xm_phy_write(struct skge_hw *hw, int port, u16 reg, u16 val)
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{
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int i;
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@ -918,19 +924,11 @@ static void xm_phy_write(struct skge_hw *hw, int port, u16 reg, u16 val)
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goto ready;
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udelay(1);
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}
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printk(KERN_WARNING PFX "%s: phy write failed to come ready\n",
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hw->dev[port]->name);
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return -EIO;
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ready:
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xm_write16(hw, port, XM_PHY_DATA, val);
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for (i = 0; i < PHY_RETRIES; i++) {
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udelay(1);
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if (!(xm_read16(hw, port, XM_MMU_CMD) & XM_MMU_PHY_BUSY))
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return;
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}
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printk(KERN_WARNING PFX "%s: phy write timed out\n",
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hw->dev[port]->name);
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return 0;
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}
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static void genesis_init(struct skge_hw *hw)
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@ -1400,42 +1398,6 @@ static void genesis_mac_intr(struct skge_hw *hw, int port)
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}
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}
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static void gm_phy_write(struct skge_hw *hw, int port, u16 reg, u16 val)
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{
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int i;
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gma_write16(hw, port, GM_SMI_DATA, val);
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gma_write16(hw, port, GM_SMI_CTRL,
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GM_SMI_CT_PHY_AD(hw->phy_addr) | GM_SMI_CT_REG_AD(reg));
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for (i = 0; i < PHY_RETRIES; i++) {
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udelay(1);
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if (!(gma_read16(hw, port, GM_SMI_CTRL) & GM_SMI_CT_BUSY))
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break;
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}
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}
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static u16 gm_phy_read(struct skge_hw *hw, int port, u16 reg)
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{
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int i;
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gma_write16(hw, port, GM_SMI_CTRL,
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GM_SMI_CT_PHY_AD(hw->phy_addr)
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| GM_SMI_CT_REG_AD(reg) | GM_SMI_CT_OP_RD);
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for (i = 0; i < PHY_RETRIES; i++) {
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udelay(1);
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if (gma_read16(hw, port, GM_SMI_CTRL) & GM_SMI_CT_RD_VAL)
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goto ready;
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}
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printk(KERN_WARNING PFX "%s: phy read timeout\n",
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hw->dev[port]->name);
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return 0;
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ready:
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return gma_read16(hw, port, GM_SMI_DATA);
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}
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static void genesis_link_up(struct skge_port *skge)
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{
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struct skge_hw *hw = skge->hw;
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@ -1549,6 +1511,54 @@ static inline void bcom_phy_intr(struct skge_port *skge)
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}
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static int gm_phy_write(struct skge_hw *hw, int port, u16 reg, u16 val)
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{
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int i;
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gma_write16(hw, port, GM_SMI_DATA, val);
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gma_write16(hw, port, GM_SMI_CTRL,
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GM_SMI_CT_PHY_AD(hw->phy_addr) | GM_SMI_CT_REG_AD(reg));
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for (i = 0; i < PHY_RETRIES; i++) {
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udelay(1);
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if (!(gma_read16(hw, port, GM_SMI_CTRL) & GM_SMI_CT_BUSY))
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return 0;
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}
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printk(KERN_WARNING PFX "%s: phy write timeout\n",
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hw->dev[port]->name);
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return -EIO;
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}
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static int __gm_phy_read(struct skge_hw *hw, int port, u16 reg, u16 *val)
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{
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int i;
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gma_write16(hw, port, GM_SMI_CTRL,
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GM_SMI_CT_PHY_AD(hw->phy_addr)
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| GM_SMI_CT_REG_AD(reg) | GM_SMI_CT_OP_RD);
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for (i = 0; i < PHY_RETRIES; i++) {
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udelay(1);
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if (gma_read16(hw, port, GM_SMI_CTRL) & GM_SMI_CT_RD_VAL)
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goto ready;
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}
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return -ETIMEDOUT;
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ready:
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*val = gma_read16(hw, port, GM_SMI_DATA);
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return 0;
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}
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static u16 gm_phy_read(struct skge_hw *hw, int port, u16 reg)
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{
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u16 v = 0;
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if (__gm_phy_read(hw, port, reg, &v))
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printk(KERN_WARNING PFX "%s: phy read timeout\n",
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hw->dev[port]->name);
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return v;
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}
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/* Marvell Phy Initailization */
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static void yukon_init(struct skge_hw *hw, int port)
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{
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@ -1997,6 +2007,51 @@ static void yukon_phy_intr(struct skge_port *skge)
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/* XXX restart autonegotiation? */
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}
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/* Basic MII support */
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static int skge_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
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{
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struct mii_ioctl_data *data = if_mii(ifr);
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struct skge_port *skge = netdev_priv(dev);
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struct skge_hw *hw = skge->hw;
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int err = -EOPNOTSUPP;
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if (!netif_running(dev))
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return -ENODEV; /* Phy still in reset */
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switch(cmd) {
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case SIOCGMIIPHY:
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data->phy_id = hw->phy_addr;
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/* fallthru */
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case SIOCGMIIREG: {
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u16 val = 0;
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spin_lock_bh(&hw->phy_lock);
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if (hw->chip_id == CHIP_ID_GENESIS)
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err = __xm_phy_read(hw, skge->port, data->reg_num & 0x1f, &val);
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else
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err = __gm_phy_read(hw, skge->port, data->reg_num & 0x1f, &val);
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spin_unlock_bh(&hw->phy_lock);
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data->val_out = val;
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break;
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}
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case SIOCSMIIREG:
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if (!capable(CAP_NET_ADMIN))
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return -EPERM;
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spin_lock_bh(&hw->phy_lock);
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if (hw->chip_id == CHIP_ID_GENESIS)
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err = xm_phy_write(hw, skge->port, data->reg_num & 0x1f,
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data->val_in);
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else
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err = gm_phy_write(hw, skge->port, data->reg_num & 0x1f,
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data->val_in);
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spin_unlock_bh(&hw->phy_lock);
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break;
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}
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return err;
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}
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static void skge_ramset(struct skge_hw *hw, u16 q, u32 start, size_t len)
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{
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u32 end;
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@ -3058,6 +3113,7 @@ static struct net_device *skge_devinit(struct skge_hw *hw, int port,
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SET_NETDEV_DEV(dev, &hw->pdev->dev);
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dev->open = skge_up;
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dev->stop = skge_down;
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dev->do_ioctl = skge_ioctl;
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dev->hard_start_xmit = skge_xmit_frame;
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dev->get_stats = skge_get_stats;
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if (hw->chip_id == CHIP_ID_GENESIS)
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