Realtek ARM64 based SoC DT for v4.15
This refactors the RTD1295 DT, preparing for (but not yet adding) RTD1293 and RTD1296. Superfluous reg property entries are dropped. DTs for PROBOX2 AVA and MeLE V9 TV boxes are added. -----BEGIN PGP SIGNATURE----- Version: GnuPG v2 iQIcBAABAgAGBQJZ/aV5AAoJEPou0S0+fgE/NoMQALWahjJ7zU5xB5mrdW1L2qfz Nb1K7dY9PJyVvwReY50U8OLJ0UOkQsmzQ2zK6aKqiiGSfeOjVknwJTbZZZ8/tKY2 0kkkN2TWX5aTodSm0S0NZkfY/+Me6ttlRabdEP06VE3BdyBY5FjThgYGZcXtArQB BMgKyh3ge/imn7AOLbPoi0ByExRfAX80TCHjOIFLXt3zx5OYpHU5XVrepT/Vej/J G+1OXsypgOJRByA8vuKlg1k9dKDLIScHoqyKZwiORJ6JVlXjb/AxO5ThzKR/WK0L 4zAtfkZWZxom5nmUtpiLOnYLVm9SViEa9ncU0HoyMLFwsxrxtkZvKNdsARllAER0 dJO1agWHUn1otdb9egJPB07h/LUsgJWYGxeq5LKpq+MUqpPa1QBhkHVz4F63obni D6VQm3PthxCW/jRD0fj0HVMVKieJO5oUtGTlHLnShjsGCzA73VI9jqDxkO3HFRot bvoPAHLtRXCF+0LQ5OYrNN5yG8aDN68EgltmgZp+nF8dXahaHmn8KKeh1GOHAfXX 8v9h52FxWcU2QWgOvIoORK3ohKey5V6L/fy6++rAwnTTQ6pV2RW2L2xRin5poXBM 5hpolazCpragl0kKCOakZ/WHcUIP61pixGMPz362ipFZw8nTNZW3DcQ7AgFtenH6 TcG1dWHJhWo47Mwk50tP =8sRS -----END PGP SIGNATURE----- Merge tag 'realtek-arm64-dt-for-4.15' of ssh://gitolite.kernel.org/pub/scm/linux/kernel/git/afaerber/linux-realtek into next/dt Pull "Realtek ARM64 based SoC DT for v4.15" from Andreas Färber: This refactors the RTD1295 DT, preparing for (but not yet adding) RTD1293 and RTD1296. Superfluous reg property entries are dropped. DTs for PROBOX2 AVA and MeLE V9 TV boxes are added. * tag 'realtek-arm64-dt-for-4.15' of ssh://gitolite.kernel.org/pub/scm/linux/kernel/git/afaerber/linux-realtek: arm64: dts: realtek: Add MeLE V9 dt-bindings: arm: realtek: Document MeLE V9 dt-bindings: Add vendor prefix for MeLE arm64: dts: realtek: Factor out common RTD129x parts arm64: dts: realtek: Add ProBox2 Ava dt-bindings: arm: realtek: Add ProBox2 AVA dt-bindings: Add vendor prefix for ProBox2 arm64: dts: realtek: Clean up RTD1295 UART reg property
This commit is contained in:
Коммит
2d2cf5283f
|
@ -12,6 +12,8 @@ Required root node properties:
|
|||
|
||||
Root node property compatible must contain, depending on board:
|
||||
|
||||
- MeLE V9: "mele,v9"
|
||||
- ProBox2 AVA: "probox2,ava"
|
||||
- Zidoo X9S: "zidoo,x9s"
|
||||
|
||||
|
||||
|
|
|
@ -199,6 +199,7 @@ mcube mCube
|
|||
meas Measurement Specialties
|
||||
mediatek MediaTek Inc.
|
||||
megachips MegaChips
|
||||
mele Shenzhen MeLE Digital Technology Ltd.
|
||||
melexis Melexis N.V.
|
||||
melfas MELFAS Inc.
|
||||
mellanox Mellanox Technologies
|
||||
|
@ -265,6 +266,7 @@ plathome Plat'Home Co., Ltd.
|
|||
plda PLDA
|
||||
poslab Poslab Technology Co., Ltd.
|
||||
powervr PowerVR (deprecated, use img)
|
||||
probox2 PROBOX2 (by W2COMP Co., Ltd.)
|
||||
pulsedlight PulsedLight, Inc
|
||||
qca Qualcomm Atheros, Inc.
|
||||
qcom Qualcomm Technologies, Inc
|
||||
|
|
|
@ -1,3 +1,5 @@
|
|||
dtb-$(CONFIG_ARCH_REALTEK) += rtd1295-mele-v9.dtb
|
||||
dtb-$(CONFIG_ARCH_REALTEK) += rtd1295-probox2-ava.dtb
|
||||
dtb-$(CONFIG_ARCH_REALTEK) += rtd1295-zidoo-x9s.dtb
|
||||
|
||||
always := $(dtb-y)
|
||||
|
|
|
@ -0,0 +1,31 @@
|
|||
/*
|
||||
* Copyright (c) 2017 Andreas Färber
|
||||
*
|
||||
* SPDX-License-Identifier: (GPL-2.0+ OR MIT)
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
#include "rtd1295.dtsi"
|
||||
|
||||
/ {
|
||||
compatible = "mele,v9", "realtek,rtd1295";
|
||||
model = "MeLE V9";
|
||||
|
||||
memory@0 {
|
||||
device_type = "memory";
|
||||
reg = <0x0 0x80000000>;
|
||||
};
|
||||
|
||||
aliases {
|
||||
serial0 = &uart0;
|
||||
};
|
||||
|
||||
chosen {
|
||||
stdout-path = "serial0:115200n8";
|
||||
};
|
||||
};
|
||||
|
||||
&uart0 {
|
||||
status = "okay";
|
||||
};
|
|
@ -0,0 +1,31 @@
|
|||
/*
|
||||
* Copyright (c) 2017 Andreas Färber
|
||||
*
|
||||
* SPDX-License-Identifier: (GPL-2.0+ OR MIT)
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
#include "rtd1295.dtsi"
|
||||
|
||||
/ {
|
||||
compatible = "probox2,ava", "realtek,rtd1295";
|
||||
model = "PROBOX2 AVA";
|
||||
|
||||
memory@0 {
|
||||
device_type = "memory";
|
||||
reg = <0x0 0x80000000>;
|
||||
};
|
||||
|
||||
aliases {
|
||||
serial0 = &uart0;
|
||||
};
|
||||
|
||||
chosen {
|
||||
stdout-path = "serial0:115200n8";
|
||||
};
|
||||
};
|
||||
|
||||
&uart0 {
|
||||
status = "okay";
|
||||
};
|
|
@ -6,12 +6,6 @@
|
|||
|
||||
/dts-v1/;
|
||||
|
||||
/memreserve/ 0x0000000000000000 0x0000000000030000;
|
||||
/memreserve/ 0x000000000001f000 0x0000000000001000;
|
||||
/memreserve/ 0x0000000000030000 0x00000000000d0000;
|
||||
/memreserve/ 0x0000000001b00000 0x00000000004be000;
|
||||
/memreserve/ 0x0000000001ffe000 0x0000000000004000;
|
||||
|
||||
#include "rtd1295.dtsi"
|
||||
|
||||
/ {
|
||||
|
|
|
@ -6,13 +6,10 @@
|
|||
* SPDX-License-Identifier: (GPL-2.0+ OR MIT)
|
||||
*/
|
||||
|
||||
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
#include "rtd129x.dtsi"
|
||||
|
||||
/ {
|
||||
compatible = "realtek,rtd1295";
|
||||
interrupt-parent = <&gic>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
||||
cpus {
|
||||
#address-cells = <2>;
|
||||
|
@ -62,12 +59,6 @@
|
|||
};
|
||||
};
|
||||
|
||||
arm-pmu {
|
||||
compatible = "arm,cortex-a53-pmu";
|
||||
interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
|
||||
};
|
||||
|
||||
timer {
|
||||
compatible = "arm,armv8-timer";
|
||||
interrupts = <GIC_PPI 13
|
||||
|
@ -79,53 +70,8 @@
|
|||
<GIC_PPI 10
|
||||
(GIC_CPU_MASK_RAW(0xf) | IRQ_TYPE_LEVEL_LOW)>;
|
||||
};
|
||||
|
||||
soc {
|
||||
compatible = "simple-bus";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
/* Exclude up to 2 GiB of RAM */
|
||||
ranges = <0x80000000 0x80000000 0x80000000>;
|
||||
|
||||
uart0: serial@98007800 {
|
||||
compatible = "snps,dw-apb-uart";
|
||||
reg = <0x98007800 0x400>,
|
||||
<0x98007000 0x100>;
|
||||
reg-shift = <2>;
|
||||
reg-io-width = <4>;
|
||||
clock-frequency = <27000000>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
uart1: serial@9801b200 {
|
||||
compatible = "snps,dw-apb-uart";
|
||||
reg = <0x9801b200 0x100>,
|
||||
<0x9801b00c 0x100>;
|
||||
reg-shift = <2>;
|
||||
reg-io-width = <4>;
|
||||
clock-frequency = <432000000>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
uart2: serial@9801b400 {
|
||||
compatible = "snps,dw-apb-uart";
|
||||
reg = <0x9801b400 0x100>,
|
||||
<0x9801b00c 0x100>;
|
||||
reg-shift = <2>;
|
||||
reg-io-width = <4>;
|
||||
clock-frequency = <432000000>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
gic: interrupt-controller@ff011000 {
|
||||
compatible = "arm,gic-400";
|
||||
reg = <0xff011000 0x1000>,
|
||||
<0xff012000 0x2000>,
|
||||
<0xff014000 0x2000>,
|
||||
<0xff016000 0x2000>;
|
||||
interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <3>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&arm_pmu {
|
||||
interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
|
||||
};
|
||||
|
|
|
@ -0,0 +1,72 @@
|
|||
/*
|
||||
* Realtek RTD1293/RTD1295/RTD1296 SoC
|
||||
*
|
||||
* Copyright (c) 2016-2017 Andreas Färber
|
||||
*
|
||||
* SPDX-License-Identifier: (GPL-2.0+ OR MIT)
|
||||
*/
|
||||
|
||||
/memreserve/ 0x0000000000000000 0x0000000000030000;
|
||||
/memreserve/ 0x000000000001f000 0x0000000000001000;
|
||||
/memreserve/ 0x0000000000030000 0x00000000000d0000;
|
||||
/memreserve/ 0x0000000001b00000 0x00000000004be000;
|
||||
/memreserve/ 0x0000000001ffe000 0x0000000000004000;
|
||||
|
||||
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
|
||||
/ {
|
||||
interrupt-parent = <&gic>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
||||
arm_pmu: arm-pmu {
|
||||
compatible = "arm,cortex-a53-pmu";
|
||||
interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
|
||||
soc {
|
||||
compatible = "simple-bus";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
/* Exclude up to 2 GiB of RAM */
|
||||
ranges = <0x80000000 0x80000000 0x80000000>;
|
||||
|
||||
uart0: serial@98007800 {
|
||||
compatible = "snps,dw-apb-uart";
|
||||
reg = <0x98007800 0x400>;
|
||||
reg-shift = <2>;
|
||||
reg-io-width = <4>;
|
||||
clock-frequency = <27000000>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
uart1: serial@9801b200 {
|
||||
compatible = "snps,dw-apb-uart";
|
||||
reg = <0x9801b200 0x100>;
|
||||
reg-shift = <2>;
|
||||
reg-io-width = <4>;
|
||||
clock-frequency = <432000000>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
uart2: serial@9801b400 {
|
||||
compatible = "snps,dw-apb-uart";
|
||||
reg = <0x9801b400 0x100>;
|
||||
reg-shift = <2>;
|
||||
reg-io-width = <4>;
|
||||
clock-frequency = <432000000>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
gic: interrupt-controller@ff011000 {
|
||||
compatible = "arm,gic-400";
|
||||
reg = <0xff011000 0x1000>,
|
||||
<0xff012000 0x2000>,
|
||||
<0xff014000 0x2000>,
|
||||
<0xff016000 0x2000>;
|
||||
interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <3>;
|
||||
};
|
||||
};
|
||||
};
|
Загрузка…
Ссылка в новой задаче