Realtek ARM64 based SoC DT for v4.15

This refactors the RTD1295 DT, preparing for (but not yet adding)
 RTD1293 and RTD1296. Superfluous reg property entries are dropped.
 DTs for PROBOX2 AVA and MeLE V9 TV boxes are added.
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Merge tag 'realtek-arm64-dt-for-4.15' of ssh://gitolite.kernel.org/pub/scm/linux/kernel/git/afaerber/linux-realtek into next/dt

Pull "Realtek ARM64 based SoC DT for v4.15" from Andreas Färber:

This refactors the RTD1295 DT, preparing for (but not yet adding)
RTD1293 and RTD1296. Superfluous reg property entries are dropped.
DTs for PROBOX2 AVA and MeLE V9 TV boxes are added.

* tag 'realtek-arm64-dt-for-4.15' of ssh://gitolite.kernel.org/pub/scm/linux/kernel/git/afaerber/linux-realtek:
  arm64: dts: realtek: Add MeLE V9
  dt-bindings: arm: realtek: Document MeLE V9
  dt-bindings: Add vendor prefix for MeLE
  arm64: dts: realtek: Factor out common RTD129x parts
  arm64: dts: realtek: Add ProBox2 Ava
  dt-bindings: arm: realtek: Add ProBox2 AVA
  dt-bindings: Add vendor prefix for ProBox2
  arm64: dts: realtek: Clean up RTD1295 UART reg property
This commit is contained in:
Arnd Bergmann 2017-11-07 16:08:58 +01:00
Родитель 3ab6dd0416 a9ce6f8545
Коммит 2d2cf5283f
8 изменённых файлов: 145 добавлений и 65 удалений

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@ -12,6 +12,8 @@ Required root node properties:
Root node property compatible must contain, depending on board:
- MeLE V9: "mele,v9"
- ProBox2 AVA: "probox2,ava"
- Zidoo X9S: "zidoo,x9s"

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@ -199,6 +199,7 @@ mcube mCube
meas Measurement Specialties
mediatek MediaTek Inc.
megachips MegaChips
mele Shenzhen MeLE Digital Technology Ltd.
melexis Melexis N.V.
melfas MELFAS Inc.
mellanox Mellanox Technologies
@ -265,6 +266,7 @@ plathome Plat'Home Co., Ltd.
plda PLDA
poslab Poslab Technology Co., Ltd.
powervr PowerVR (deprecated, use img)
probox2 PROBOX2 (by W2COMP Co., Ltd.)
pulsedlight PulsedLight, Inc
qca Qualcomm Atheros, Inc.
qcom Qualcomm Technologies, Inc

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@ -1,3 +1,5 @@
dtb-$(CONFIG_ARCH_REALTEK) += rtd1295-mele-v9.dtb
dtb-$(CONFIG_ARCH_REALTEK) += rtd1295-probox2-ava.dtb
dtb-$(CONFIG_ARCH_REALTEK) += rtd1295-zidoo-x9s.dtb
always := $(dtb-y)

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@ -0,0 +1,31 @@
/*
* Copyright (c) 2017 Andreas Färber
*
* SPDX-License-Identifier: (GPL-2.0+ OR MIT)
*/
/dts-v1/;
#include "rtd1295.dtsi"
/ {
compatible = "mele,v9", "realtek,rtd1295";
model = "MeLE V9";
memory@0 {
device_type = "memory";
reg = <0x0 0x80000000>;
};
aliases {
serial0 = &uart0;
};
chosen {
stdout-path = "serial0:115200n8";
};
};
&uart0 {
status = "okay";
};

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@ -0,0 +1,31 @@
/*
* Copyright (c) 2017 Andreas Färber
*
* SPDX-License-Identifier: (GPL-2.0+ OR MIT)
*/
/dts-v1/;
#include "rtd1295.dtsi"
/ {
compatible = "probox2,ava", "realtek,rtd1295";
model = "PROBOX2 AVA";
memory@0 {
device_type = "memory";
reg = <0x0 0x80000000>;
};
aliases {
serial0 = &uart0;
};
chosen {
stdout-path = "serial0:115200n8";
};
};
&uart0 {
status = "okay";
};

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@ -6,12 +6,6 @@
/dts-v1/;
/memreserve/ 0x0000000000000000 0x0000000000030000;
/memreserve/ 0x000000000001f000 0x0000000000001000;
/memreserve/ 0x0000000000030000 0x00000000000d0000;
/memreserve/ 0x0000000001b00000 0x00000000004be000;
/memreserve/ 0x0000000001ffe000 0x0000000000004000;
#include "rtd1295.dtsi"
/ {

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@ -6,13 +6,10 @@
* SPDX-License-Identifier: (GPL-2.0+ OR MIT)
*/
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include "rtd129x.dtsi"
/ {
compatible = "realtek,rtd1295";
interrupt-parent = <&gic>;
#address-cells = <1>;
#size-cells = <1>;
cpus {
#address-cells = <2>;
@ -62,12 +59,6 @@
};
};
arm-pmu {
compatible = "arm,cortex-a53-pmu";
interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
};
timer {
compatible = "arm,armv8-timer";
interrupts = <GIC_PPI 13
@ -79,53 +70,8 @@
<GIC_PPI 10
(GIC_CPU_MASK_RAW(0xf) | IRQ_TYPE_LEVEL_LOW)>;
};
soc {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
/* Exclude up to 2 GiB of RAM */
ranges = <0x80000000 0x80000000 0x80000000>;
uart0: serial@98007800 {
compatible = "snps,dw-apb-uart";
reg = <0x98007800 0x400>,
<0x98007000 0x100>;
reg-shift = <2>;
reg-io-width = <4>;
clock-frequency = <27000000>;
status = "disabled";
};
uart1: serial@9801b200 {
compatible = "snps,dw-apb-uart";
reg = <0x9801b200 0x100>,
<0x9801b00c 0x100>;
reg-shift = <2>;
reg-io-width = <4>;
clock-frequency = <432000000>;
status = "disabled";
};
uart2: serial@9801b400 {
compatible = "snps,dw-apb-uart";
reg = <0x9801b400 0x100>,
<0x9801b00c 0x100>;
reg-shift = <2>;
reg-io-width = <4>;
clock-frequency = <432000000>;
status = "disabled";
};
gic: interrupt-controller@ff011000 {
compatible = "arm,gic-400";
reg = <0xff011000 0x1000>,
<0xff012000 0x2000>,
<0xff014000 0x2000>,
<0xff016000 0x2000>;
interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
interrupt-controller;
#interrupt-cells = <3>;
};
};
};
&arm_pmu {
interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
};

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@ -0,0 +1,72 @@
/*
* Realtek RTD1293/RTD1295/RTD1296 SoC
*
* Copyright (c) 2016-2017 Andreas Färber
*
* SPDX-License-Identifier: (GPL-2.0+ OR MIT)
*/
/memreserve/ 0x0000000000000000 0x0000000000030000;
/memreserve/ 0x000000000001f000 0x0000000000001000;
/memreserve/ 0x0000000000030000 0x00000000000d0000;
/memreserve/ 0x0000000001b00000 0x00000000004be000;
/memreserve/ 0x0000000001ffe000 0x0000000000004000;
#include <dt-bindings/interrupt-controller/arm-gic.h>
/ {
interrupt-parent = <&gic>;
#address-cells = <1>;
#size-cells = <1>;
arm_pmu: arm-pmu {
compatible = "arm,cortex-a53-pmu";
interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
};
soc {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
/* Exclude up to 2 GiB of RAM */
ranges = <0x80000000 0x80000000 0x80000000>;
uart0: serial@98007800 {
compatible = "snps,dw-apb-uart";
reg = <0x98007800 0x400>;
reg-shift = <2>;
reg-io-width = <4>;
clock-frequency = <27000000>;
status = "disabled";
};
uart1: serial@9801b200 {
compatible = "snps,dw-apb-uart";
reg = <0x9801b200 0x100>;
reg-shift = <2>;
reg-io-width = <4>;
clock-frequency = <432000000>;
status = "disabled";
};
uart2: serial@9801b400 {
compatible = "snps,dw-apb-uart";
reg = <0x9801b400 0x100>;
reg-shift = <2>;
reg-io-width = <4>;
clock-frequency = <432000000>;
status = "disabled";
};
gic: interrupt-controller@ff011000 {
compatible = "arm,gic-400";
reg = <0xff011000 0x1000>,
<0xff012000 0x2000>,
<0xff014000 0x2000>,
<0xff016000 0x2000>;
interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
interrupt-controller;
#interrupt-cells = <3>;
};
};
};