Merge remote branch 'intel/drm-intel-fixes' of ../drm-next into drm-core-next
* 'intel/drm-intel-fixes' of ../drm-next: Revert "drm/i915: Don't save/restore hardware status page address register" drm/i915: Avoid unmapping pages from a NULL address space drm/i915: Fix use after free within tracepoint drm/i915: Restore missing command flush before interrupt on BLT ring drm/i915: Disable pagefaults along execbuffer relocation fast path drm/i915: Fix computation of pitch for dumb bo creator drm/i915: report correct render clock frequencies on SNB drm/i915/dp: Correct the order of deletion for ghost eDP devices drm/i915: Fix tiling corruption from pipelined fencing drm/i915: Re-enable self-refresh drm/i915: Prevent racy removal of request from client list drm/i915: skip redundant operations whilst enabling pipes and planes drm/i915: Remove surplus POSTING_READs before wait_for_vblank
This commit is contained in:
Dave Airlie
Коммит
2d370f502a
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@ -892,7 +892,7 @@ static int i915_cur_delayinfo(struct seq_file *m, void *unused)
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seq_printf(m, "Render p-state limit: %d\n",
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rp_state_limits & 0xff);
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seq_printf(m, "CAGF: %dMHz\n", ((rpstat & GEN6_CAGF_MASK) >>
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GEN6_CAGF_SHIFT) * 100);
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GEN6_CAGF_SHIFT) * 50);
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seq_printf(m, "RP CUR UP EI: %dus\n", rpupei &
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GEN6_CURICONT_MASK);
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seq_printf(m, "RP CUR UP: %dus\n", rpcurup &
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@ -908,15 +908,15 @@ static int i915_cur_delayinfo(struct seq_file *m, void *unused)
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max_freq = (rp_state_cap & 0xff0000) >> 16;
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seq_printf(m, "Lowest (RPN) frequency: %dMHz\n",
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max_freq * 100);
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max_freq * 50);
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max_freq = (rp_state_cap & 0xff00) >> 8;
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seq_printf(m, "Nominal (RP1) frequency: %dMHz\n",
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max_freq * 100);
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max_freq * 50);
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max_freq = rp_state_cap & 0xff;
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seq_printf(m, "Max non-overclocked (RP0) frequency: %dMHz\n",
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max_freq * 100);
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max_freq * 50);
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__gen6_gt_force_wake_put(dev_priv);
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} else {
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@ -383,6 +383,7 @@ typedef struct drm_i915_private {
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u32 saveDSPACNTR;
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u32 saveDSPBCNTR;
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u32 saveDSPARB;
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u32 saveHWS;
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u32 savePIPEACONF;
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u32 savePIPEBCONF;
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u32 savePIPEASRC;
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@ -224,7 +224,7 @@ i915_gem_dumb_create(struct drm_file *file,
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struct drm_mode_create_dumb *args)
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{
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/* have to work out size/pitch and return them */
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args->pitch = ALIGN(args->width & ((args->bpp + 1) / 8), 64);
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args->pitch = ALIGN(args->width * ((args->bpp + 7) / 8), 64);
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args->size = args->pitch * args->height;
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return i915_gem_create(file, dev,
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args->size, &args->handle);
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@ -1356,9 +1356,10 @@ i915_gem_release_mmap(struct drm_i915_gem_object *obj)
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if (!obj->fault_mappable)
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return;
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unmap_mapping_range(obj->base.dev->dev_mapping,
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(loff_t)obj->base.map_list.hash.key<<PAGE_SHIFT,
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obj->base.size, 1);
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if (obj->base.dev->dev_mapping)
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unmap_mapping_range(obj->base.dev->dev_mapping,
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(loff_t)obj->base.map_list.hash.key<<PAGE_SHIFT,
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obj->base.size, 1);
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obj->fault_mappable = false;
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}
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@ -1796,8 +1797,10 @@ i915_gem_request_remove_from_client(struct drm_i915_gem_request *request)
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return;
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spin_lock(&file_priv->mm.lock);
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list_del(&request->client_list);
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request->file_priv = NULL;
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if (request->file_priv) {
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list_del(&request->client_list);
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request->file_priv = NULL;
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}
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spin_unlock(&file_priv->mm.lock);
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}
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@ -2217,13 +2220,18 @@ i915_gem_flush_ring(struct intel_ring_buffer *ring,
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{
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int ret;
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if (((invalidate_domains | flush_domains) & I915_GEM_GPU_DOMAINS) == 0)
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return 0;
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trace_i915_gem_ring_flush(ring, invalidate_domains, flush_domains);
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ret = ring->flush(ring, invalidate_domains, flush_domains);
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if (ret)
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return ret;
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i915_gem_process_flushing_list(ring, flush_domains);
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if (flush_domains & I915_GEM_GPU_DOMAINS)
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i915_gem_process_flushing_list(ring, flush_domains);
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return 0;
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}
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@ -2579,8 +2587,23 @@ i915_gem_object_get_fence(struct drm_i915_gem_object *obj,
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reg = &dev_priv->fence_regs[obj->fence_reg];
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list_move_tail(®->lru_list, &dev_priv->mm.fence_list);
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if (!obj->fenced_gpu_access && !obj->last_fenced_seqno)
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pipelined = NULL;
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if (obj->tiling_changed) {
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ret = i915_gem_object_flush_fence(obj, pipelined);
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if (ret)
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return ret;
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if (!obj->fenced_gpu_access && !obj->last_fenced_seqno)
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pipelined = NULL;
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if (pipelined) {
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reg->setup_seqno =
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i915_gem_next_request_seqno(pipelined);
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obj->last_fenced_seqno = reg->setup_seqno;
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obj->last_fenced_ring = pipelined;
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}
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goto update;
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}
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if (!pipelined) {
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if (reg->setup_seqno) {
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@ -2599,31 +2622,6 @@ i915_gem_object_get_fence(struct drm_i915_gem_object *obj,
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ret = i915_gem_object_flush_fence(obj, pipelined);
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if (ret)
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return ret;
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} else if (obj->tiling_changed) {
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if (obj->fenced_gpu_access) {
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if (obj->base.write_domain & I915_GEM_GPU_DOMAINS) {
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ret = i915_gem_flush_ring(obj->ring,
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0, obj->base.write_domain);
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if (ret)
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return ret;
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}
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obj->fenced_gpu_access = false;
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}
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}
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if (!obj->fenced_gpu_access && !obj->last_fenced_seqno)
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pipelined = NULL;
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BUG_ON(!pipelined && reg->setup_seqno);
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if (obj->tiling_changed) {
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if (pipelined) {
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reg->setup_seqno =
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i915_gem_next_request_seqno(pipelined);
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obj->last_fenced_seqno = reg->setup_seqno;
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obj->last_fenced_ring = pipelined;
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}
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goto update;
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}
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return 0;
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@ -3606,6 +3604,8 @@ static void i915_gem_free_object_tail(struct drm_i915_gem_object *obj)
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return;
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}
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trace_i915_gem_object_destroy(obj);
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if (obj->base.map_list.map)
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i915_gem_free_mmap_offset(obj);
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@ -3615,8 +3615,6 @@ static void i915_gem_free_object_tail(struct drm_i915_gem_object *obj)
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kfree(obj->page_cpu_valid);
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kfree(obj->bit_17);
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kfree(obj);
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trace_i915_gem_object_destroy(obj);
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}
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void i915_gem_free_object(struct drm_gem_object *gem_obj)
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@ -367,6 +367,10 @@ i915_gem_execbuffer_relocate_entry(struct drm_i915_gem_object *obj,
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uint32_t __iomem *reloc_entry;
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void __iomem *reloc_page;
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/* We can't wait for rendering with pagefaults disabled */
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if (obj->active && in_atomic())
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return -EFAULT;
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ret = i915_gem_object_set_to_gtt_domain(obj, 1);
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if (ret)
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return ret;
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@ -440,15 +444,24 @@ i915_gem_execbuffer_relocate(struct drm_device *dev,
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struct list_head *objects)
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{
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struct drm_i915_gem_object *obj;
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int ret;
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int ret = 0;
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/* This is the fast path and we cannot handle a pagefault whilst
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* holding the struct mutex lest the user pass in the relocations
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* contained within a mmaped bo. For in such a case we, the page
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* fault handler would call i915_gem_fault() and we would try to
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* acquire the struct mutex again. Obviously this is bad and so
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* lockdep complains vehemently.
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*/
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pagefault_disable();
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list_for_each_entry(obj, objects, exec_list) {
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ret = i915_gem_execbuffer_relocate_object(obj, eb);
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if (ret)
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return ret;
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break;
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}
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pagefault_enable();
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return 0;
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return ret;
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}
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static int
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|
|
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@ -796,6 +796,9 @@ int i915_save_state(struct drm_device *dev)
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pci_read_config_byte(dev->pdev, LBB, &dev_priv->saveLBB);
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/* Hardware status page */
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dev_priv->saveHWS = I915_READ(HWS_PGA);
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i915_save_display(dev);
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/* Interrupt state */
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@ -842,6 +845,9 @@ int i915_restore_state(struct drm_device *dev)
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pci_write_config_byte(dev->pdev, LBB, dev_priv->saveLBB);
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/* Hardware status page */
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I915_WRITE(HWS_PGA, dev_priv->saveHWS);
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i915_restore_display(dev);
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/* Interrupt state */
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|
|
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|
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@ -1516,9 +1516,10 @@ static void intel_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe,
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reg = PIPECONF(pipe);
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val = I915_READ(reg);
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val |= PIPECONF_ENABLE;
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I915_WRITE(reg, val);
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POSTING_READ(reg);
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if (val & PIPECONF_ENABLE)
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return;
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I915_WRITE(reg, val | PIPECONF_ENABLE);
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intel_wait_for_vblank(dev_priv->dev, pipe);
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}
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@ -1552,9 +1553,10 @@ static void intel_disable_pipe(struct drm_i915_private *dev_priv,
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reg = PIPECONF(pipe);
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val = I915_READ(reg);
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val &= ~PIPECONF_ENABLE;
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I915_WRITE(reg, val);
|
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POSTING_READ(reg);
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if ((val & PIPECONF_ENABLE) == 0)
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return;
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|
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I915_WRITE(reg, val & ~PIPECONF_ENABLE);
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intel_wait_for_pipe_off(dev_priv->dev, pipe);
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}
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@ -1577,9 +1579,10 @@ static void intel_enable_plane(struct drm_i915_private *dev_priv,
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reg = DSPCNTR(plane);
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val = I915_READ(reg);
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val |= DISPLAY_PLANE_ENABLE;
|
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I915_WRITE(reg, val);
|
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POSTING_READ(reg);
|
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if (val & DISPLAY_PLANE_ENABLE)
|
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return;
|
||||
|
||||
I915_WRITE(reg, val | DISPLAY_PLANE_ENABLE);
|
||||
intel_wait_for_vblank(dev_priv->dev, pipe);
|
||||
}
|
||||
|
||||
|
|
@ -1610,9 +1613,10 @@ static void intel_disable_plane(struct drm_i915_private *dev_priv,
|
|||
|
||||
reg = DSPCNTR(plane);
|
||||
val = I915_READ(reg);
|
||||
val &= ~DISPLAY_PLANE_ENABLE;
|
||||
I915_WRITE(reg, val);
|
||||
POSTING_READ(reg);
|
||||
if ((val & DISPLAY_PLANE_ENABLE) == 0)
|
||||
return;
|
||||
|
||||
I915_WRITE(reg, val & ~DISPLAY_PLANE_ENABLE);
|
||||
intel_flush_display_plane(dev_priv, plane);
|
||||
intel_wait_for_vblank(dev_priv->dev, pipe);
|
||||
}
|
||||
|
|
@ -1769,7 +1773,6 @@ static void g4x_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
|
|||
return;
|
||||
|
||||
I915_WRITE(DPFC_CONTROL, dpfc_ctl & ~DPFC_CTL_EN);
|
||||
POSTING_READ(DPFC_CONTROL);
|
||||
intel_wait_for_vblank(dev, intel_crtc->pipe);
|
||||
}
|
||||
|
||||
|
|
@ -1861,7 +1864,6 @@ static void ironlake_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
|
|||
return;
|
||||
|
||||
I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl & ~DPFC_CTL_EN);
|
||||
POSTING_READ(ILK_DPFC_CONTROL);
|
||||
intel_wait_for_vblank(dev, intel_crtc->pipe);
|
||||
}
|
||||
|
||||
|
|
@ -3883,10 +3885,7 @@ static bool g4x_compute_srwm(struct drm_device *dev,
|
|||
display, cursor);
|
||||
}
|
||||
|
||||
static inline bool single_plane_enabled(unsigned int mask)
|
||||
{
|
||||
return mask && (mask & -mask) == 0;
|
||||
}
|
||||
#define single_plane_enabled(mask) is_power_of_2(mask)
|
||||
|
||||
static void g4x_update_wm(struct drm_device *dev)
|
||||
{
|
||||
|
|
@ -5777,7 +5776,6 @@ static void intel_increase_pllclock(struct drm_crtc *crtc)
|
|||
|
||||
dpll &= ~DISPLAY_RATE_SELECT_FPA1;
|
||||
I915_WRITE(dpll_reg, dpll);
|
||||
POSTING_READ(dpll_reg);
|
||||
intel_wait_for_vblank(dev, pipe);
|
||||
|
||||
dpll = I915_READ(dpll_reg);
|
||||
|
|
@ -5821,7 +5819,6 @@ static void intel_decrease_pllclock(struct drm_crtc *crtc)
|
|||
|
||||
dpll |= DISPLAY_RATE_SELECT_FPA1;
|
||||
I915_WRITE(dpll_reg, dpll);
|
||||
dpll = I915_READ(dpll_reg);
|
||||
intel_wait_for_vblank(dev, pipe);
|
||||
dpll = I915_READ(dpll_reg);
|
||||
if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
|
||||
|
|
@ -6933,7 +6930,7 @@ void gen6_enable_rps(struct drm_i915_private *dev_priv)
|
|||
DRM_ERROR("timeout waiting for pcode mailbox to finish\n");
|
||||
if (pcu_mbox & (1<<31)) { /* OC supported */
|
||||
max_freq = pcu_mbox & 0xff;
|
||||
DRM_DEBUG_DRIVER("overclocking supported, adjusting frequency max to %dMHz\n", pcu_mbox * 100);
|
||||
DRM_DEBUG_DRIVER("overclocking supported, adjusting frequency max to %dMHz\n", pcu_mbox * 50);
|
||||
}
|
||||
|
||||
/* In units of 100MHz */
|
||||
|
|
|
|||
|
|
@ -1957,9 +1957,9 @@ intel_dp_init(struct drm_device *dev, int output_reg)
|
|||
DP_NO_AUX_HANDSHAKE_LINK_TRAINING;
|
||||
} else {
|
||||
/* if this fails, presume the device is a ghost */
|
||||
DRM_ERROR("failed to retrieve link info\n");
|
||||
intel_dp_destroy(&intel_connector->base);
|
||||
DRM_INFO("failed to retrieve link info, disabling eDP\n");
|
||||
intel_dp_encoder_destroy(&intel_dp->base.base);
|
||||
intel_dp_destroy(&intel_connector->base);
|
||||
return;
|
||||
}
|
||||
}
|
||||
|
|
|
|||
|
|
@ -65,62 +65,60 @@ render_ring_flush(struct intel_ring_buffer *ring,
|
|||
u32 cmd;
|
||||
int ret;
|
||||
|
||||
if ((invalidate_domains | flush_domains) & I915_GEM_GPU_DOMAINS) {
|
||||
/*
|
||||
* read/write caches:
|
||||
*
|
||||
* I915_GEM_DOMAIN_RENDER is always invalidated, but is
|
||||
* only flushed if MI_NO_WRITE_FLUSH is unset. On 965, it is
|
||||
* also flushed at 2d versus 3d pipeline switches.
|
||||
*
|
||||
* read-only caches:
|
||||
*
|
||||
* I915_GEM_DOMAIN_SAMPLER is flushed on pre-965 if
|
||||
* MI_READ_FLUSH is set, and is always flushed on 965.
|
||||
*
|
||||
* I915_GEM_DOMAIN_COMMAND may not exist?
|
||||
*
|
||||
* I915_GEM_DOMAIN_INSTRUCTION, which exists on 965, is
|
||||
* invalidated when MI_EXE_FLUSH is set.
|
||||
*
|
||||
* I915_GEM_DOMAIN_VERTEX, which exists on 965, is
|
||||
* invalidated with every MI_FLUSH.
|
||||
*
|
||||
* TLBs:
|
||||
*
|
||||
* On 965, TLBs associated with I915_GEM_DOMAIN_COMMAND
|
||||
* and I915_GEM_DOMAIN_CPU in are invalidated at PTE write and
|
||||
* I915_GEM_DOMAIN_RENDER and I915_GEM_DOMAIN_SAMPLER
|
||||
* are flushed at any MI_FLUSH.
|
||||
*/
|
||||
|
||||
cmd = MI_FLUSH | MI_NO_WRITE_FLUSH;
|
||||
if ((invalidate_domains|flush_domains) &
|
||||
I915_GEM_DOMAIN_RENDER)
|
||||
cmd &= ~MI_NO_WRITE_FLUSH;
|
||||
if (INTEL_INFO(dev)->gen < 4) {
|
||||
/*
|
||||
* read/write caches:
|
||||
*
|
||||
* I915_GEM_DOMAIN_RENDER is always invalidated, but is
|
||||
* only flushed if MI_NO_WRITE_FLUSH is unset. On 965, it is
|
||||
* also flushed at 2d versus 3d pipeline switches.
|
||||
*
|
||||
* read-only caches:
|
||||
*
|
||||
* I915_GEM_DOMAIN_SAMPLER is flushed on pre-965 if
|
||||
* MI_READ_FLUSH is set, and is always flushed on 965.
|
||||
*
|
||||
* I915_GEM_DOMAIN_COMMAND may not exist?
|
||||
*
|
||||
* I915_GEM_DOMAIN_INSTRUCTION, which exists on 965, is
|
||||
* invalidated when MI_EXE_FLUSH is set.
|
||||
*
|
||||
* I915_GEM_DOMAIN_VERTEX, which exists on 965, is
|
||||
* invalidated with every MI_FLUSH.
|
||||
*
|
||||
* TLBs:
|
||||
*
|
||||
* On 965, TLBs associated with I915_GEM_DOMAIN_COMMAND
|
||||
* and I915_GEM_DOMAIN_CPU in are invalidated at PTE write and
|
||||
* I915_GEM_DOMAIN_RENDER and I915_GEM_DOMAIN_SAMPLER
|
||||
* are flushed at any MI_FLUSH.
|
||||
* On the 965, the sampler cache always gets flushed
|
||||
* and this bit is reserved.
|
||||
*/
|
||||
|
||||
cmd = MI_FLUSH | MI_NO_WRITE_FLUSH;
|
||||
if ((invalidate_domains|flush_domains) &
|
||||
I915_GEM_DOMAIN_RENDER)
|
||||
cmd &= ~MI_NO_WRITE_FLUSH;
|
||||
if (INTEL_INFO(dev)->gen < 4) {
|
||||
/*
|
||||
* On the 965, the sampler cache always gets flushed
|
||||
* and this bit is reserved.
|
||||
*/
|
||||
if (invalidate_domains & I915_GEM_DOMAIN_SAMPLER)
|
||||
cmd |= MI_READ_FLUSH;
|
||||
}
|
||||
if (invalidate_domains & I915_GEM_DOMAIN_INSTRUCTION)
|
||||
cmd |= MI_EXE_FLUSH;
|
||||
|
||||
if (invalidate_domains & I915_GEM_DOMAIN_COMMAND &&
|
||||
(IS_G4X(dev) || IS_GEN5(dev)))
|
||||
cmd |= MI_INVALIDATE_ISP;
|
||||
|
||||
ret = intel_ring_begin(ring, 2);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
intel_ring_emit(ring, cmd);
|
||||
intel_ring_emit(ring, MI_NOOP);
|
||||
intel_ring_advance(ring);
|
||||
if (invalidate_domains & I915_GEM_DOMAIN_SAMPLER)
|
||||
cmd |= MI_READ_FLUSH;
|
||||
}
|
||||
if (invalidate_domains & I915_GEM_DOMAIN_INSTRUCTION)
|
||||
cmd |= MI_EXE_FLUSH;
|
||||
|
||||
if (invalidate_domains & I915_GEM_DOMAIN_COMMAND &&
|
||||
(IS_G4X(dev) || IS_GEN5(dev)))
|
||||
cmd |= MI_INVALIDATE_ISP;
|
||||
|
||||
ret = intel_ring_begin(ring, 2);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
intel_ring_emit(ring, cmd);
|
||||
intel_ring_emit(ring, MI_NOOP);
|
||||
intel_ring_advance(ring);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
|
@ -568,9 +566,6 @@ bsd_ring_flush(struct intel_ring_buffer *ring,
|
|||
{
|
||||
int ret;
|
||||
|
||||
if ((flush_domains & I915_GEM_DOMAIN_RENDER) == 0)
|
||||
return 0;
|
||||
|
||||
ret = intel_ring_begin(ring, 2);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
|
@ -1056,9 +1051,6 @@ static int gen6_ring_flush(struct intel_ring_buffer *ring,
|
|||
uint32_t cmd;
|
||||
int ret;
|
||||
|
||||
if (((invalidate | flush) & I915_GEM_GPU_DOMAINS) == 0)
|
||||
return 0;
|
||||
|
||||
ret = intel_ring_begin(ring, 4);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
|
@ -1230,9 +1222,6 @@ static int blt_ring_flush(struct intel_ring_buffer *ring,
|
|||
uint32_t cmd;
|
||||
int ret;
|
||||
|
||||
if (((invalidate | flush) & I915_GEM_DOMAIN_RENDER) == 0)
|
||||
return 0;
|
||||
|
||||
ret = blt_ring_begin(ring, 4);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
|
|
|||
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