MIPS: Correct FP ISA requirements
Correct ISA requirements for floating-point instructions: * the CU3 exception signifies a real COP3 instruction in MIPS I & II, * the BC1FL and BC1TL instructions are not supported in MIPS I, * the SQRT.fmt instructions are indeed supported in MIPS II, * the LDC1 and SDC1 instructions are indeed supported in MIPS32r1, * the CEIL.W.fmt, FLOOR.W.fmt, ROUND.W.fmt and TRUNC.W.fmt instructions are indeed supported in MIPS32, * the CVT.L.fmt and CVT.fmt.L instructions are indeed supported in MIPS32r2 and MIPS32r6, * the CEIL.L.fmt, FLOOR.L.fmt, ROUND.L.fmt and TRUNC.L.fmt instructions are indeed supported in MIPS32r2 and MIPS32r6, * the RSQRT.fmt and RECIP.fmt instructions are indeed supported in MIPS64r1, Also simplify conditionals for MIPS III and MIPS IV FPU instructions and the handling of the MOVCI minor opcode. Signed-off-by: Maciej W. Rozycki <macro@linux-mips.org> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/9700/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
This commit is contained in:
Maciej W. Rozycki
Ralf Baechle
Родитель
80cbfad790
Коммит
2d83fea786
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@ -221,8 +221,11 @@
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#define cpu_has_mips_4_5_r (cpu_has_mips_4 | cpu_has_mips_5_r)
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#define cpu_has_mips_5_r (cpu_has_mips_5 | cpu_has_mips_r)
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#define cpu_has_mips_4_5_r2_r6 (cpu_has_mips_4_5 | cpu_has_mips_r2 | \
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cpu_has_mips_r6)
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#define cpu_has_mips_3_4_5_64_r2_r6 \
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(cpu_has_mips_3 | cpu_has_mips_4_5_64_r2_r6)
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#define cpu_has_mips_4_5_64_r2_r6 \
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(cpu_has_mips_4_5 | cpu_has_mips64r1 | \
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cpu_has_mips_r2 | cpu_has_mips_r6)
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#define cpu_has_mips32 (cpu_has_mips32r1 | cpu_has_mips32r2 | cpu_has_mips32r6)
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#define cpu_has_mips64 (cpu_has_mips64r1 | cpu_has_mips64r2 | cpu_has_mips64r6)
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@ -1349,19 +1349,18 @@ asmlinkage void do_cpu(struct pt_regs *regs)
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case 3:
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/*
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* Old (MIPS I and MIPS II) processors will set this code
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* for COP1X opcode instructions that replaced the original
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* COP3 space. We don't limit COP1 space instructions in
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* the emulator according to the CPU ISA, so we want to
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* treat COP1X instructions consistently regardless of which
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* code the CPU chose. Therefore we redirect this trap to
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* the FP emulator too.
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*
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* Then some newer FPU-less processors use this code
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* erroneously too, so they are covered by this choice
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* as well.
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* The COP3 opcode space and consequently the CP0.Status.CU3
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* bit and the CP0.Cause.CE=3 encoding have been removed as
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* of the MIPS III ISA. From the MIPS IV and MIPS32r2 ISAs
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* up the space has been reused for COP1X instructions, that
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* are enabled by the CP0.Status.CU1 bit and consequently
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* use the CP0.Cause.CE=1 encoding for Coprocessor Unusable
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* exceptions. Some FPU-less processors that implement one
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* of these ISAs however use this code erroneously for COP1X
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* instructions. Therefore we redirect this trap to the FP
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* emulator too.
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*/
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if (raw_cpu_has_fpu) {
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if (raw_cpu_has_fpu || !cpu_has_mips_4_5_64_r2_r6) {
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force_sig(SIGILL, current);
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break;
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}
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@ -1115,17 +1115,18 @@ emul:
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likely = 0;
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switch (MIPSInst_RT(ir) & 3) {
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case bcfl_op:
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likely = 1;
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if (cpu_has_mips_2_3_4_5_r)
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likely = 1;
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/* Fall through */
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case bcf_op:
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cond = !cond;
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break;
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case bctl_op:
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likely = 1;
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if (cpu_has_mips_2_3_4_5_r)
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likely = 1;
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/* Fall through */
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case bct_op:
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break;
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default:
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/* thats an illegal instruction */
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return SIGILL;
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}
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set_delay_slot(xcp);
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@ -1165,36 +1166,34 @@ emul:
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switch (MIPSInst_OPCODE(ir)) {
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case lwc1_op:
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goto emul;
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case swc1_op:
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goto emul;
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case ldc1_op:
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case sdc1_op:
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if (cpu_has_mips_2_3_4_5 ||
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cpu_has_mips64)
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if (cpu_has_mips_2_3_4_5_r)
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goto emul;
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return SIGILL;
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goto emul;
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case cop1_op:
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goto emul;
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case cop1x_op:
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if (cpu_has_mips_4_5 || cpu_has_mips64 || cpu_has_mips32r2)
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if (cpu_has_mips_4_5_64_r2_r6)
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/* its one of ours */
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goto emul;
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return SIGILL;
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case spec_op:
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if (!cpu_has_mips_4_5_r)
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return SIGILL;
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switch (MIPSInst_FUNC(ir)) {
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case movc_op:
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if (cpu_has_mips_4_5_r)
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goto emul;
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if (MIPSInst_FUNC(ir) == movc_op)
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goto emul;
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return SIGILL;
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}
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break;
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}
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@ -1228,7 +1227,7 @@ emul:
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break;
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case cop1x_op:
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if (!cpu_has_mips_4_5 && !cpu_has_mips64 && !cpu_has_mips32r2)
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if (!cpu_has_mips_4_5_64_r2_r6)
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return SIGILL;
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sig = fpux_emu(xcp, ctx, ir, fault_addr);
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@ -1561,7 +1560,7 @@ static int fpu_emu(struct pt_regs *xcp, struct mips_fpu_struct *ctx,
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/* unary ops */
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case fsqrt_op:
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if (!cpu_has_mips_4_5_r)
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if (!cpu_has_mips_2_3_4_5_r)
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return SIGILL;
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handler.u = ieee754sp_sqrt;
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@ -1573,14 +1572,14 @@ static int fpu_emu(struct pt_regs *xcp, struct mips_fpu_struct *ctx,
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* achieve full IEEE-754 accuracy - however this emulator does.
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*/
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case frsqrt_op:
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if (!cpu_has_mips_4_5_r2_r6)
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if (!cpu_has_mips_4_5_64_r2_r6)
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return SIGILL;
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handler.u = fpemu_sp_rsqrt;
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goto scopuop;
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case frecip_op:
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if (!cpu_has_mips_4_5_r2_r6)
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if (!cpu_has_mips_4_5_64_r2_r6)
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return SIGILL;
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handler.u = fpemu_sp_recip;
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@ -1682,7 +1681,7 @@ copcsr:
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case ftrunc_op:
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case fceil_op:
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case ffloor_op:
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if (!cpu_has_mips_2_3_4_5 && !cpu_has_mips64)
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if (!cpu_has_mips_2_3_4_5_r)
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return SIGILL;
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oldrm = ieee754_csr.rm;
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@ -1694,7 +1693,7 @@ copcsr:
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goto copcsr;
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case fcvtl_op:
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if (!cpu_has_mips_3_4_5 && !cpu_has_mips64)
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if (!cpu_has_mips_3_4_5_64_r2_r6)
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return SIGILL;
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SPFROMREG(fs, MIPSInst_FS(ir));
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@ -1706,7 +1705,7 @@ copcsr:
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case ftruncl_op:
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case fceill_op:
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case ffloorl_op:
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if (!cpu_has_mips_3_4_5 && !cpu_has_mips64)
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if (!cpu_has_mips_3_4_5_64_r2_r6)
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return SIGILL;
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oldrm = ieee754_csr.rm;
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@ -1775,13 +1774,13 @@ copcsr:
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* achieve full IEEE-754 accuracy - however this emulator does.
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*/
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case frsqrt_op:
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if (!cpu_has_mips_4_5_r2_r6)
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if (!cpu_has_mips_4_5_64_r2_r6)
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return SIGILL;
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handler.u = fpemu_dp_rsqrt;
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goto dcopuop;
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case frecip_op:
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if (!cpu_has_mips_4_5_r2_r6)
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if (!cpu_has_mips_4_5_64_r2_r6)
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return SIGILL;
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handler.u = fpemu_dp_recip;
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@ -1871,7 +1870,7 @@ dcopuop:
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goto copcsr;
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case fcvtl_op:
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if (!cpu_has_mips_3_4_5 && !cpu_has_mips64)
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if (!cpu_has_mips_3_4_5_64_r2_r6)
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return SIGILL;
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DPFROMREG(fs, MIPSInst_FS(ir));
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@ -1883,7 +1882,7 @@ dcopuop:
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case ftruncl_op:
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case fceill_op:
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case ffloorl_op:
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if (!cpu_has_mips_3_4_5 && !cpu_has_mips64)
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if (!cpu_has_mips_3_4_5_64_r2_r6)
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return SIGILL;
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oldrm = ieee754_csr.rm;
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@ -1942,7 +1941,7 @@ dcopuop:
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case l_fmt:
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if (!cpu_has_mips_3_4_5 && !cpu_has_mips64)
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if (!cpu_has_mips_3_4_5_64_r2_r6)
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return SIGILL;
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DIFROMREG(bits, MIPSInst_FS(ir));
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@ -2006,7 +2005,7 @@ dcopuop:
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SITOREG(rv.w, MIPSInst_FD(ir));
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break;
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case l_fmt:
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if (!cpu_has_mips_3_4_5 && !cpu_has_mips64)
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if (!cpu_has_mips_3_4_5_64_r2_r6)
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return SIGILL;
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DITOREG(rv.l, MIPSInst_FD(ir));
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