Merge remote-tracking branch 'jwb/next' into next
This commit is contained in:
Benjamin Herrenschmidt
Коммит
2d87e06e74
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@ -4034,7 +4034,7 @@ M: Josh Boyer <jwboyer@gmail.com>
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M: Matt Porter <mporter@kernel.crashing.org>
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W: http://www.penguinppc.org/
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L: linuxppc-dev@lists.ozlabs.org
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T: git git://git.infradead.org/users/jwboyer/powerpc-4xx.git
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T: git git://git.kernel.org/pub/scm/linux/kernel/git/jwboyer/powerpc-4xx.git
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S: Maintained
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F: arch/powerpc/platforms/40x/
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F: arch/powerpc/platforms/44x/
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@ -33,7 +33,7 @@
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aliases {
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ethernet0 = &EMAC0;
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serial0 = &UART0;
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//serial1 = &UART1; --gcl missing UART1 label
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serial1 = &UART1;
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};
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cpus {
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@ -52,7 +52,7 @@
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d-cache-size = <32768>;
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dcr-controller;
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dcr-access-method = "native";
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//next-level-cache = <&L2C0>; --gcl missing L2C0 label
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next-level-cache = <&L2C0>;
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};
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};
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@ -117,6 +117,16 @@
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dcr-reg = <0x00c 0x002>;
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};
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L2C0: l2c {
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compatible = "ibm,l2-cache-apm82181", "ibm,l2-cache";
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dcr-reg = <0x020 0x008
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0x030 0x008>;
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cache-line-size = <32>;
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cache-size = <262144>;
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interrupt-parent = <&UIC1>;
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interrupts = <11 1>;
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};
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plb {
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compatible = "ibm,plb4";
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#address-cells = <2>;
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@ -182,6 +192,53 @@
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reg = <0x001a0000 0x00060000>;
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};
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};
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ndfc@1,0 {
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compatible = "ibm,ndfc";
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reg = <0x00000003 0x00000000 0x00002000>;
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ccr = <0x00001000>;
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bank-settings = <0x80002222>;
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#address-cells = <1>;
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#size-cells = <1>;
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/* 2Gb Nand Flash */
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nand {
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#address-cells = <1>;
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#size-cells = <1>;
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partition@0 {
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label = "firmware";
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reg = <0x00000000 0x00C00000>;
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};
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partition@c00000 {
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label = "environment";
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reg = <0x00C00000 0x00B00000>;
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};
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partition@1700000 {
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label = "kernel";
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reg = <0x01700000 0x00E00000>;
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};
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partition@2500000 {
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label = "root";
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reg = <0x02500000 0x08200000>;
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};
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partition@a700000 {
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label = "device-tree";
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reg = <0x0A700000 0x00B00000>;
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};
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partition@b200000 {
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label = "config";
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reg = <0x0B200000 0x00D00000>;
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};
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partition@bf00000 {
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label = "diag";
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reg = <0x0BF00000 0x00C00000>;
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};
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partition@cb00000 {
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label = "vendor";
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reg = <0x0CB00000 0x3500000>;
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};
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};
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};
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};
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UART0: serial@ef600300 {
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@ -195,11 +252,36 @@
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interrupts = <0x1 0x4>;
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};
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UART1: serial@ef600400 {
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device_type = "serial";
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compatible = "ns16550";
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reg = <0xef600400 0x00000008>;
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virtual-reg = <0xef600400>;
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clock-frequency = <0>; /* Filled in by U-Boot */
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current-speed = <0>; /* Filled in by U-Boot */
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interrupt-parent = <&UIC0>;
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interrupts = <0x1 0x4>;
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};
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IIC0: i2c@ef600700 {
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compatible = "ibm,iic";
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reg = <0xef600700 0x00000014>;
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interrupt-parent = <&UIC0>;
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interrupts = <0x2 0x4>;
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#address-cells = <1>;
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#size-cells = <0>;
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rtc@68 {
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compatible = "stm,m41t80";
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reg = <0x68>;
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interrupt-parent = <&UIC0>;
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interrupts = <0x9 0x8>;
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};
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sttm@4C {
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compatible = "adm,adm1032";
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reg = <0x4C>;
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interrupt-parent = <&UIC1>;
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interrupts = <0x1E 0x8>; /* CPU_THERNAL_L */
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};
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};
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IIC1: i2c@ef600800 {
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@ -250,5 +332,46 @@
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};
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};
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PCIE0: pciex@d00000000 {
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device_type = "pci";
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#interrupt-cells = <1>;
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#size-cells = <2>;
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#address-cells = <3>;
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compatible = "ibm,plb-pciex-apm821xx", "ibm,plb-pciex";
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primary;
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port = <0x0>; /* port number */
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reg = <0x0000000d 0x00000000 0x20000000 /* Config space access */
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0x0000000c 0x08010000 0x00001000>; /* Registers */
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dcr-reg = <0x100 0x020>;
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sdr-base = <0x300>;
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/* Outbound ranges, one memory and one IO,
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* later cannot be changed
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*/
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ranges = <0x02000000 0x00000000 0x80000000 0x0000000e 0x00000000 0x00000000 0x80000000
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0x02000000 0x00000000 0x00000000 0x0000000f 0x00000000 0x00000000 0x00100000
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0x01000000 0x00000000 0x00000000 0x0000000f 0x80000000 0x00000000 0x00010000>;
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/* Inbound 2GB range starting at 0 */
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dma-ranges = <0x42000000 0x0 0x0 0x0 0x0 0x0 0x80000000>;
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/* This drives busses 40 to 0x7f */
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bus-range = <0x40 0x7f>;
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/* Legacy interrupts (note the weird polarity, the bridge seems
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* to invert PCIe legacy interrupts).
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* We are de-swizzling here because the numbers are actually for
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* port of the root complex virtual P2P bridge. But I want
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* to avoid putting a node for it in the tree, so the numbers
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* below are basically de-swizzled numbers.
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* The real slot is on idsel 0, so the swizzling is 1:1
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*/
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interrupt-map-mask = <0x0 0x0 0x0 0x7>;
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interrupt-map = <
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0x0 0x0 0x0 0x1 &UIC3 0xc 0x4 /* swizzled int A */
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0x0 0x0 0x0 0x2 &UIC3 0xd 0x4 /* swizzled int B */
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0x0 0x0 0x0 0x3 &UIC3 0xe 0x4 /* swizzled int C */
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0x0 0x0 0x0 0x4 &UIC3 0xf 0x4 /* swizzled int D */>;
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};
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};
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};
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@ -1816,7 +1816,7 @@ static struct cpu_spec __initdata cpu_specs[] = {
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.platform = "ppc440",
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},
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{ /* 464 in APM821xx */
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.pvr_mask = 0xffffff00,
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.pvr_mask = 0xfffffff0,
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.pvr_value = 0x12C41C80,
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.cpu_name = "APM821XX",
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.cpu_features = CPU_FTRS_44X,
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@ -23,6 +23,7 @@ config BLUESTONE
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default n
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select PPC44x_SIMPLE
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select APM821xx
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select PPC4xx_PCI_EXPRESS
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select IBM_EMAC_RGMII
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help
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This option enables support for the APM APM821xx Evaluation board.
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@ -52,7 +52,7 @@ machine_device_initcall(ppc44x_simple, ppc44x_device_probe);
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static char *board[] __initdata = {
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"amcc,arches",
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"amcc,bamboo",
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"amcc,bluestone",
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"apm,bluestone",
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"amcc,glacier",
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"ibm,ebony",
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"amcc,eiger",
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@ -1050,6 +1050,74 @@ static struct ppc4xx_pciex_hwops ppc460ex_pcie_hwops __initdata =
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.check_link = ppc4xx_pciex_check_link_sdr,
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};
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static int __init apm821xx_pciex_core_init(struct device_node *np)
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{
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/* Return the number of pcie port */
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return 1;
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}
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static int apm821xx_pciex_init_port_hw(struct ppc4xx_pciex_port *port)
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{
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u32 val;
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/*
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* Do a software reset on PCIe ports.
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* This code is to fix the issue that pci drivers doesn't re-assign
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* bus number for PCIE devices after Uboot
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* scanned and configured all the buses (eg. PCIE NIC IntelPro/1000
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* PT quad port, SAS LSI 1064E)
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*/
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mtdcri(SDR0, PESDR0_460EX_PHY_CTL_RST, 0x0);
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mdelay(10);
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if (port->endpoint)
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val = PTYPE_LEGACY_ENDPOINT << 20;
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else
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val = PTYPE_ROOT_PORT << 20;
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val |= LNKW_X1 << 12;
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mtdcri(SDR0, port->sdr_base + PESDRn_DLPSET, val);
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mtdcri(SDR0, port->sdr_base + PESDRn_UTLSET1, 0x00000000);
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mtdcri(SDR0, port->sdr_base + PESDRn_UTLSET2, 0x01010000);
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mtdcri(SDR0, PESDR0_460EX_L0CDRCTL, 0x00003230);
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mtdcri(SDR0, PESDR0_460EX_L0DRV, 0x00000130);
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mtdcri(SDR0, PESDR0_460EX_L0CLK, 0x00000006);
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mtdcri(SDR0, PESDR0_460EX_PHY_CTL_RST, 0x10000000);
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mdelay(50);
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mtdcri(SDR0, PESDR0_460EX_PHY_CTL_RST, 0x30000000);
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mtdcri(SDR0, port->sdr_base + PESDRn_RCSSET,
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mfdcri(SDR0, port->sdr_base + PESDRn_RCSSET) |
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(PESDRx_RCSSET_RSTGU | PESDRx_RCSSET_RSTPYN));
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/* Poll for PHY reset */
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val = PESDR0_460EX_RSTSTA - port->sdr_base;
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if (ppc4xx_pciex_wait_on_sdr(port, val, 0x1, 1, 100)) {
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printk(KERN_WARNING "%s: PCIE: Can't reset PHY\n", __func__);
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return -EBUSY;
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} else {
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mtdcri(SDR0, port->sdr_base + PESDRn_RCSSET,
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(mfdcri(SDR0, port->sdr_base + PESDRn_RCSSET) &
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~(PESDRx_RCSSET_RSTGU | PESDRx_RCSSET_RSTDL)) |
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PESDRx_RCSSET_RSTPYN);
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port->has_ibpre = 1;
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return 0;
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}
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}
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static struct ppc4xx_pciex_hwops apm821xx_pcie_hwops __initdata = {
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.want_sdr = true,
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.core_init = apm821xx_pciex_core_init,
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.port_init_hw = apm821xx_pciex_init_port_hw,
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.setup_utl = ppc460ex_pciex_init_utl,
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.check_link = ppc4xx_pciex_check_link_sdr,
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};
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static int __init ppc460sx_pciex_core_init(struct device_node *np)
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{
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/* HSS drive amplitude */
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@ -1362,6 +1430,8 @@ static int __init ppc4xx_pciex_check_core_init(struct device_node *np)
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ppc4xx_pciex_hwops = &ppc460ex_pcie_hwops;
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if (of_device_is_compatible(np, "ibm,plb-pciex-460sx"))
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ppc4xx_pciex_hwops = &ppc460sx_pcie_hwops;
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if (of_device_is_compatible(np, "ibm,plb-pciex-apm821xx"))
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ppc4xx_pciex_hwops = &apm821xx_pcie_hwops;
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#endif /* CONFIG_44x */
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#ifdef CONFIG_40x
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if (of_device_is_compatible(np, "ibm,plb-pciex-405ex"))
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