qedr: Add RoCE driver framework
Adds a skeletal implementation of the qed* RoCE driver - basically the ability to communicate with the qede driver and receive notifications from it regarding various init/exit events. Signed-off-by: Rajesh Borundia <rajesh.borundia@cavium.com> Signed-off-by: Ram Amrani <Ram.Amrani@cavium.com> Signed-off-by: Doug Ledford <dledford@redhat.com>
This commit is contained in:
Ram Amrani
Doug Ledford
Родитель
e9f8f48bca
Коммит
2e0cbc4dd0
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@ -89,4 +89,6 @@ source "drivers/infiniband/sw/rxe/Kconfig"
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source "drivers/infiniband/hw/hfi1/Kconfig"
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source "drivers/infiniband/hw/qedr/Kconfig"
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endif # INFINIBAND
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@ -10,3 +10,4 @@ obj-$(CONFIG_INFINIBAND_OCRDMA) += ocrdma/
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obj-$(CONFIG_INFINIBAND_USNIC) += usnic/
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obj-$(CONFIG_INFINIBAND_HFI1) += hfi1/
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obj-$(CONFIG_INFINIBAND_HNS) += hns/
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obj-$(CONFIG_INFINIBAND_QEDR) += qedr/
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@ -0,0 +1,7 @@
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config INFINIBAND_QEDR
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tristate "QLogic RoCE driver"
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depends on 64BIT && QEDE
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select QED_LL2
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---help---
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This driver provides low-level InfiniBand over Ethernet
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support for QLogic QED host channel adapters (HCAs).
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@ -0,0 +1,3 @@
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obj-$(CONFIG_INFINIBAND_QEDR) := qedr.o
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qedr-y := main.o
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@ -0,0 +1,254 @@
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/* QLogic qedr NIC Driver
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* Copyright (c) 2015-2016 QLogic Corporation
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*
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* This software is available to you under a choice of one of two
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* licenses. You may choose to be licensed under the terms of the GNU
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* General Public License (GPL) Version 2, available from the file
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* COPYING in the main directory of this source tree, or the
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* OpenIB.org BSD license below:
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*
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* Redistribution and use in source and binary forms, with or
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* without modification, are permitted provided that the following
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* conditions are met:
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*
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* - Redistributions of source code must retain the above
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* copyright notice, this list of conditions and the following
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* disclaimer.
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*
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* - Redistributions in binary form must reproduce the above
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* copyright notice, this list of conditions and the following
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* disclaimer in the documentation and /or other materials
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* provided with the distribution.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
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* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
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* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
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* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
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* BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
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* ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
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* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
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* SOFTWARE.
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*/
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#include <linux/module.h>
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#include <rdma/ib_verbs.h>
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#include <rdma/ib_addr.h>
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#include <linux/netdevice.h>
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#include <linux/iommu.h>
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#include <net/addrconf.h>
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#include <linux/qed/qede_roce.h>
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#include "qedr.h"
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MODULE_DESCRIPTION("QLogic 40G/100G ROCE Driver");
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MODULE_AUTHOR("QLogic Corporation");
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MODULE_LICENSE("Dual BSD/GPL");
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MODULE_VERSION(QEDR_MODULE_VERSION);
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void qedr_ib_dispatch_event(struct qedr_dev *dev, u8 port_num,
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enum ib_event_type type)
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{
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struct ib_event ibev;
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ibev.device = &dev->ibdev;
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ibev.element.port_num = port_num;
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ibev.event = type;
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ib_dispatch_event(&ibev);
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}
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static enum rdma_link_layer qedr_link_layer(struct ib_device *device,
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u8 port_num)
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{
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return IB_LINK_LAYER_ETHERNET;
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}
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static int qedr_register_device(struct qedr_dev *dev)
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{
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strlcpy(dev->ibdev.name, "qedr%d", IB_DEVICE_NAME_MAX);
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memcpy(dev->ibdev.node_desc, QEDR_NODE_DESC, sizeof(QEDR_NODE_DESC));
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dev->ibdev.owner = THIS_MODULE;
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dev->ibdev.get_link_layer = qedr_link_layer;
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return 0;
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}
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/* QEDR sysfs interface */
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static ssize_t show_rev(struct device *device, struct device_attribute *attr,
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char *buf)
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{
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struct qedr_dev *dev = dev_get_drvdata(device);
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return scnprintf(buf, PAGE_SIZE, "0x%x\n", dev->pdev->vendor);
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}
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static ssize_t show_hca_type(struct device *device,
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struct device_attribute *attr, char *buf)
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{
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return scnprintf(buf, PAGE_SIZE, "%s\n", "HCA_TYPE_TO_SET");
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}
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static DEVICE_ATTR(hw_rev, S_IRUGO, show_rev, NULL);
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static DEVICE_ATTR(hca_type, S_IRUGO, show_hca_type, NULL);
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static struct device_attribute *qedr_attributes[] = {
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&dev_attr_hw_rev,
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&dev_attr_hca_type
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};
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static void qedr_remove_sysfiles(struct qedr_dev *dev)
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{
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int i;
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for (i = 0; i < ARRAY_SIZE(qedr_attributes); i++)
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device_remove_file(&dev->ibdev.dev, qedr_attributes[i]);
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}
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static void qedr_pci_set_atomic(struct qedr_dev *dev, struct pci_dev *pdev)
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{
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struct pci_dev *bridge;
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u32 val;
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dev->atomic_cap = IB_ATOMIC_NONE;
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bridge = pdev->bus->self;
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if (!bridge)
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return;
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/* Check whether we are connected directly or via a switch */
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while (bridge && bridge->bus->parent) {
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DP_DEBUG(dev, QEDR_MSG_INIT,
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"Device is not connected directly to root. bridge->bus->number=%d primary=%d\n",
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bridge->bus->number, bridge->bus->primary);
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/* Need to check Atomic Op Routing Supported all the way to
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* root complex.
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*/
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pcie_capability_read_dword(bridge, PCI_EXP_DEVCAP2, &val);
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if (!(val & PCI_EXP_DEVCAP2_ATOMIC_ROUTE)) {
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pcie_capability_clear_word(pdev,
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PCI_EXP_DEVCTL2,
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PCI_EXP_DEVCTL2_ATOMIC_REQ);
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return;
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}
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bridge = bridge->bus->parent->self;
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}
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bridge = pdev->bus->self;
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/* according to bridge capability */
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pcie_capability_read_dword(bridge, PCI_EXP_DEVCAP2, &val);
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if (val & PCI_EXP_DEVCAP2_ATOMIC_COMP64) {
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pcie_capability_set_word(pdev, PCI_EXP_DEVCTL2,
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PCI_EXP_DEVCTL2_ATOMIC_REQ);
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dev->atomic_cap = IB_ATOMIC_GLOB;
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} else {
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pcie_capability_clear_word(pdev, PCI_EXP_DEVCTL2,
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PCI_EXP_DEVCTL2_ATOMIC_REQ);
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}
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}
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static struct qedr_dev *qedr_add(struct qed_dev *cdev, struct pci_dev *pdev,
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struct net_device *ndev)
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{
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struct qedr_dev *dev;
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int rc = 0, i;
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dev = (struct qedr_dev *)ib_alloc_device(sizeof(*dev));
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if (!dev) {
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pr_err("Unable to allocate ib device\n");
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return NULL;
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}
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DP_DEBUG(dev, QEDR_MSG_INIT, "qedr add device called\n");
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dev->pdev = pdev;
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dev->ndev = ndev;
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dev->cdev = cdev;
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qedr_pci_set_atomic(dev, pdev);
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rc = qedr_register_device(dev);
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if (rc) {
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DP_ERR(dev, "Unable to allocate register device\n");
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goto init_err;
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}
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for (i = 0; i < ARRAY_SIZE(qedr_attributes); i++)
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if (device_create_file(&dev->ibdev.dev, qedr_attributes[i]))
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goto init_err;
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DP_DEBUG(dev, QEDR_MSG_INIT, "qedr driver loaded successfully\n");
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return dev;
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init_err:
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ib_dealloc_device(&dev->ibdev);
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DP_ERR(dev, "qedr driver load failed rc=%d\n", rc);
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return NULL;
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}
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static void qedr_remove(struct qedr_dev *dev)
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{
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/* First unregister with stack to stop all the active traffic
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* of the registered clients.
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*/
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qedr_remove_sysfiles(dev);
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ib_dealloc_device(&dev->ibdev);
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}
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static int qedr_close(struct qedr_dev *dev)
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{
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qedr_ib_dispatch_event(dev, 1, IB_EVENT_PORT_ERR);
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return 0;
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}
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static void qedr_shutdown(struct qedr_dev *dev)
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{
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qedr_close(dev);
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qedr_remove(dev);
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}
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/* event handling via NIC driver ensures that all the NIC specific
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* initialization done before RoCE driver notifies
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* event to stack.
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*/
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static void qedr_notify(struct qedr_dev *dev, enum qede_roce_event event)
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{
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switch (event) {
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case QEDE_UP:
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qedr_ib_dispatch_event(dev, 1, IB_EVENT_PORT_ACTIVE);
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break;
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case QEDE_DOWN:
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qedr_close(dev);
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break;
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case QEDE_CLOSE:
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qedr_shutdown(dev);
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break;
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case QEDE_CHANGE_ADDR:
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qedr_ib_dispatch_event(dev, 1, IB_EVENT_GID_CHANGE);
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break;
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default:
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pr_err("Event not supported\n");
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}
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}
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static struct qedr_driver qedr_drv = {
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.name = "qedr_driver",
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.add = qedr_add,
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.remove = qedr_remove,
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.notify = qedr_notify,
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};
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static int __init qedr_init_module(void)
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{
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return qede_roce_register_driver(&qedr_drv);
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}
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static void __exit qedr_exit_module(void)
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{
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qede_roce_unregister_driver(&qedr_drv);
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}
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module_init(qedr_init_module);
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module_exit(qedr_exit_module);
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@ -0,0 +1,61 @@
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/* QLogic qedr NIC Driver
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* Copyright (c) 2015-2016 QLogic Corporation
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*
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* This software is available to you under a choice of one of two
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* licenses. You may choose to be licensed under the terms of the GNU
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* General Public License (GPL) Version 2, available from the file
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* COPYING in the main directory of this source tree, or the
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* OpenIB.org BSD license below:
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*
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* Redistribution and use in source and binary forms, with or
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* without modification, are permitted provided that the following
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* conditions are met:
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*
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* - Redistributions of source code must retain the above
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* copyright notice, this list of conditions and the following
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* disclaimer.
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*
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* - Redistributions in binary form must reproduce the above
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* copyright notice, this list of conditions and the following
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* disclaimer in the documentation and /or other materials
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* provided with the distribution.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
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* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
|
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* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
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* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
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* BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
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* ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
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* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
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* SOFTWARE.
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*/
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#ifndef __QEDR_H__
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#define __QEDR_H__
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#include <linux/pci.h>
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#include <rdma/ib_addr.h>
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#include <linux/qed/qed_if.h>
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#include <linux/qed/qede_roce.h>
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#define QEDR_MODULE_VERSION "8.10.10.0"
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#define QEDR_NODE_DESC "QLogic 579xx RoCE HCA"
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#define DP_NAME(dev) ((dev)->ibdev.name)
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#define DP_DEBUG(dev, module, fmt, ...) \
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pr_debug("(%s) " module ": " fmt, \
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DP_NAME(dev) ? DP_NAME(dev) : "", ## __VA_ARGS__)
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#define QEDR_MSG_INIT "INIT"
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struct qedr_dev {
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struct ib_device ibdev;
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struct qed_dev *cdev;
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struct pci_dev *pdev;
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struct net_device *ndev;
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enum ib_atomic_cap atomic_cap;
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u32 dp_module;
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u8 dp_level;
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};
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#endif
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@ -107,15 +107,4 @@ config QEDE
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---help---
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This enables the support for ...
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config INFINIBAND_QEDR
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tristate "QLogic qede RoCE sources [debug]"
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depends on QEDE && 64BIT
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select QED_LL2
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default n
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---help---
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This provides a temporary node that allows the compilation
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and logical testing of the InfiniBand over Ethernet support
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for QLogic QED. This would be replaced by the 'real' option
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once the QEDR driver is added [+relocated].
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endif # NET_VENDOR_QLOGIC
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@ -612,6 +612,8 @@
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*/
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#define PCI_EXP_DEVCAP2 36 /* Device Capabilities 2 */
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#define PCI_EXP_DEVCAP2_ARI 0x00000020 /* Alternative Routing-ID */
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#define PCI_EXP_DEVCAP2_ATOMIC_ROUTE 0x00000040 /* Atomic Op routing */
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#define PCI_EXP_DEVCAP2_ATOMIC_COMP64 0x00000100 /* Atomic 64-bit compare */
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#define PCI_EXP_DEVCAP2_LTR 0x00000800 /* Latency tolerance reporting */
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#define PCI_EXP_DEVCAP2_OBFF_MASK 0x000c0000 /* OBFF support mechanism */
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#define PCI_EXP_DEVCAP2_OBFF_MSG 0x00040000 /* New message signaling */
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@ -619,6 +621,7 @@
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#define PCI_EXP_DEVCTL2 40 /* Device Control 2 */
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#define PCI_EXP_DEVCTL2_COMP_TIMEOUT 0x000f /* Completion Timeout Value */
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#define PCI_EXP_DEVCTL2_ARI 0x0020 /* Alternative Routing-ID */
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#define PCI_EXP_DEVCTL2_ATOMIC_REQ 0x0040 /* Set Atomic requests */
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#define PCI_EXP_DEVCTL2_IDO_REQ_EN 0x0100 /* Allow IDO for requests */
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#define PCI_EXP_DEVCTL2_IDO_CMP_EN 0x0200 /* Allow IDO for completions */
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#define PCI_EXP_DEVCTL2_LTR_EN 0x0400 /* Enable LTR mechanism */
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