IB/rdmavt, IB/hfi1: Create device dependent s_flags
Move some s_flags defines out of rdmavt and into hfi1 because they are hfi1 specific and therefore should remain in the driver instead of bubbling up to rdmavt. Document device specific ranges in rdmavt and remap those in hfi1. Reviewed-by: Dennis Dalessandro <dennis.dalessandro@intel.com> Signed-off-by: Mike Marciniszyn <mike.marciniszyn@intel.com> Signed-off-by: Kaike Wan <kaike.wan@intel.com> Signed-off-by: Dennis Dalessandro <dennis.dalessandro@intel.com> Signed-off-by: Jason Gunthorpe <jgg@mellanox.com>
This commit is contained in:
Mike Marciniszyn
Jason Gunthorpe
Родитель
32e3d97079
Коммит
2e2ba09e48
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@ -1,5 +1,5 @@
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/*
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* Copyright(c) 2015-2017 Intel Corporation.
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* Copyright(c) 2015-2018 Intel Corporation.
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*
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* This file is provided under a dual BSD/GPLv2 license. When using or
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* redistributing this file, you may do so under either license.
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@ -1618,11 +1618,11 @@ static void sc_piobufavail(struct send_context *sc)
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/* Wake up the most starved one first */
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if (n)
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hfi1_qp_wakeup(qps[max_idx],
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RVT_S_WAIT_PIO | RVT_S_WAIT_PIO_DRAIN);
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RVT_S_WAIT_PIO | HFI1_S_WAIT_PIO_DRAIN);
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for (i = 0; i < n; i++)
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if (i != max_idx)
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hfi1_qp_wakeup(qps[i],
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RVT_S_WAIT_PIO | RVT_S_WAIT_PIO_DRAIN);
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RVT_S_WAIT_PIO | HFI1_S_WAIT_PIO_DRAIN);
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}
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/* translate a send credit update to a bit code of reasons */
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@ -1,5 +1,5 @@
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/*
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* Copyright(c) 2015 - 2017 Intel Corporation.
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* Copyright(c) 2015 - 2018 Intel Corporation.
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*
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* This file is provided under a dual BSD/GPLv2 license. When using or
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* redistributing this file, you may do so under either license.
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@ -273,7 +273,7 @@ void hfi1_modify_qp(struct rvt_qp *qp, struct ib_qp_attr *attr,
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if (attr_mask & IB_QP_PATH_MIG_STATE &&
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attr->path_mig_state == IB_MIG_MIGRATED &&
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qp->s_mig_state == IB_MIG_ARMED) {
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qp->s_flags |= RVT_S_AHG_CLEAR;
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qp->s_flags |= HFI1_S_AHG_CLEAR;
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priv->s_sc = ah_to_sc(ibqp->device, &qp->remote_ah_attr);
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priv->s_sde = qp_to_sdma_engine(qp, priv->s_sc);
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priv->s_sendcontext = qp_to_send_context(qp, priv->s_sc);
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@ -717,7 +717,7 @@ void hfi1_migrate_qp(struct rvt_qp *qp)
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qp->remote_ah_attr = qp->alt_ah_attr;
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qp->port_num = rdma_ah_get_port_num(&qp->alt_ah_attr);
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qp->s_pkey_index = qp->s_alt_pkey_index;
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qp->s_flags |= RVT_S_AHG_CLEAR;
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qp->s_flags |= HFI1_S_AHG_CLEAR;
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priv->s_sc = ah_to_sc(qp->ibqp.device, &qp->remote_ah_attr);
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priv->s_sde = qp_to_sdma_engine(qp, priv->s_sc);
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qp_set_16b(qp);
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@ -1,7 +1,7 @@
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#ifndef _QP_H
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#define _QP_H
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/*
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* Copyright(c) 2015 - 2017 Intel Corporation.
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* Copyright(c) 2015 - 2018 Intel Corporation.
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*
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* This file is provided under a dual BSD/GPLv2 license. When using or
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* redistributing this file, you may do so under either license.
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@ -69,6 +69,26 @@ static inline int hfi1_send_ok(struct rvt_qp *qp)
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!(qp->s_flags & RVT_S_ANY_WAIT_SEND));
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}
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/*
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* Driver specific s_flags starting at bit 31 down to HFI1_S_MIN_BIT_MASK
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*
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* HFI1_S_AHG_VALID - ahg header valid on chip
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* HFI1_S_AHG_CLEAR - have send engine clear ahg state
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* HFI1_S_WAIT_PIO_DRAIN - qp waiting for PIOs to drain
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* HFI1_S_MIN_BIT_MASK - the lowest bit that can be used by hfi1
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*/
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#define HFI1_S_AHG_VALID 0x80000000
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#define HFI1_S_AHG_CLEAR 0x40000000
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#define HFI1_S_WAIT_PIO_DRAIN 0x20000000
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#define HFI1_S_MIN_BIT_MASK 0x01000000
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/*
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* overload wait defines
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*/
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#define HFI1_S_ANY_WAIT_IO (RVT_S_ANY_WAIT_IO | HFI1_S_WAIT_PIO_DRAIN)
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#define HFI1_S_ANY_WAIT (HFI1_S_ANY_WAIT_IO | RVT_S_ANY_WAIT_SEND)
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/*
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* free_ahg - clear ahg from QP
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*/
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@ -77,7 +97,7 @@ static inline void clear_ahg(struct rvt_qp *qp)
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struct hfi1_qp_priv *priv = qp->priv;
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priv->s_ahg->ahgcount = 0;
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qp->s_flags &= ~(RVT_S_AHG_VALID | RVT_S_AHG_CLEAR);
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qp->s_flags &= ~(HFI1_S_AHG_VALID | HFI1_S_AHG_CLEAR);
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if (priv->s_sde && qp->s_ahgidx >= 0)
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sdma_ahg_free(priv->s_sde, qp->s_ahgidx);
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qp->s_ahgidx = -1;
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@ -1,5 +1,5 @@
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/*
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* Copyright(c) 2015, 2016 Intel Corporation.
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* Copyright(c) 2015 - 2018 Intel Corporation.
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*
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* This file is provided under a dual BSD/GPLv2 license. When using or
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* redistributing this file, you may do so under either license.
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@ -241,7 +241,7 @@ bail:
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smp_wmb();
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qp->s_flags &= ~(RVT_S_RESP_PENDING
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| RVT_S_ACK_PENDING
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| RVT_S_AHG_VALID);
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| HFI1_S_AHG_VALID);
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return 0;
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}
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@ -1024,7 +1024,7 @@ done:
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if ((cmp_psn(qp->s_psn, qp->s_sending_hpsn) <= 0) &&
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(cmp_psn(qp->s_sending_psn, qp->s_sending_hpsn) <= 0))
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qp->s_flags |= RVT_S_WAIT_PSN;
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qp->s_flags &= ~RVT_S_AHG_VALID;
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qp->s_flags &= ~HFI1_S_AHG_VALID;
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}
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/*
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@ -1,5 +1,5 @@
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/*
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* Copyright(c) 2015 - 2017 Intel Corporation.
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* Copyright(c) 2015 - 2018 Intel Corporation.
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*
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* This file is provided under a dual BSD/GPLv2 license. When using or
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* redistributing this file, you may do so under either license.
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@ -194,7 +194,7 @@ static void ruc_loopback(struct rvt_qp *sqp)
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spin_lock_irqsave(&sqp->s_lock, flags);
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/* Return if we are already busy processing a work request. */
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if ((sqp->s_flags & (RVT_S_BUSY | RVT_S_ANY_WAIT)) ||
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if ((sqp->s_flags & (RVT_S_BUSY | HFI1_S_ANY_WAIT)) ||
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!(ib_rvt_state_ops[sqp->state] & RVT_PROCESS_OR_FLUSH_SEND))
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goto unlock;
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@ -533,9 +533,9 @@ static inline void build_ahg(struct rvt_qp *qp, u32 npsn)
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{
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struct hfi1_qp_priv *priv = qp->priv;
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if (unlikely(qp->s_flags & RVT_S_AHG_CLEAR))
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if (unlikely(qp->s_flags & HFI1_S_AHG_CLEAR))
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clear_ahg(qp);
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if (!(qp->s_flags & RVT_S_AHG_VALID)) {
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if (!(qp->s_flags & HFI1_S_AHG_VALID)) {
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/* first middle that needs copy */
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if (qp->s_ahgidx < 0)
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qp->s_ahgidx = sdma_ahg_alloc(priv->s_sde);
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@ -544,7 +544,7 @@ static inline void build_ahg(struct rvt_qp *qp, u32 npsn)
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priv->s_ahg->tx_flags |= SDMA_TXREQ_F_AHG_COPY;
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/* save to protect a change in another thread */
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priv->s_ahg->ahgidx = qp->s_ahgidx;
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qp->s_flags |= RVT_S_AHG_VALID;
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qp->s_flags |= HFI1_S_AHG_VALID;
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}
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} else {
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/* subsequent middle after valid */
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@ -650,7 +650,7 @@ static inline void hfi1_make_ruc_header_16B(struct rvt_qp *qp,
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if (middle)
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build_ahg(qp, bth2);
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else
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qp->s_flags &= ~RVT_S_AHG_VALID;
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qp->s_flags &= ~HFI1_S_AHG_VALID;
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bth0 |= pkey;
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bth0 |= extra_bytes << 20;
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@ -727,7 +727,7 @@ static inline void hfi1_make_ruc_header_9B(struct rvt_qp *qp,
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if (middle)
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build_ahg(qp, bth2);
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else
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qp->s_flags &= ~RVT_S_AHG_VALID;
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qp->s_flags &= ~HFI1_S_AHG_VALID;
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bth0 |= pkey;
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bth0 |= extra_bytes << 20;
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@ -1007,7 +1007,7 @@ static int pio_wait(struct rvt_qp *qp,
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int was_empty;
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dev->n_piowait += !!(flag & RVT_S_WAIT_PIO);
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dev->n_piodrain += !!(flag & RVT_S_WAIT_PIO_DRAIN);
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dev->n_piodrain += !!(flag & HFI1_S_WAIT_PIO_DRAIN);
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qp->s_flags |= flag;
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was_empty = list_empty(&sc->piowait);
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iowait_queue(ps->pkts_sent, &priv->s_iowait,
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@ -1376,7 +1376,7 @@ int hfi1_verbs_send(struct rvt_qp *qp, struct hfi1_pkt_state *ps)
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return pio_wait(qp,
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ps->s_txreq->psc,
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ps,
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RVT_S_WAIT_PIO_DRAIN);
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HFI1_S_WAIT_PIO_DRAIN);
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return sr(qp, ps, 0);
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}
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@ -2,7 +2,7 @@
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#define DEF_RDMAVT_INCQP_H
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/*
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* Copyright(c) 2016, 2017 Intel Corporation.
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* Copyright(c) 2016 - 2018 Intel Corporation.
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*
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* This file is provided under a dual BSD/GPLv2 license. When using or
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* redistributing this file, you may do so under either license.
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@ -91,6 +91,7 @@
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* RVT_S_WAIT_ACK - waiting for an ACK packet before sending more requests
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* RVT_S_SEND_ONE - send one packet, request ACK, then wait for ACK
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* RVT_S_ECN - a BECN was queued to the send engine
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* RVT_S_MAX_BIT_MASK - The max bit that can be used by rdmavt
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*/
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#define RVT_S_SIGNAL_REQ_WR 0x0001
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#define RVT_S_BUSY 0x0002
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@ -103,23 +104,26 @@
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#define RVT_S_WAIT_SSN_CREDIT 0x0100
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#define RVT_S_WAIT_DMA 0x0200
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#define RVT_S_WAIT_PIO 0x0400
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#define RVT_S_WAIT_PIO_DRAIN 0x0800
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#define RVT_S_WAIT_TX 0x1000
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#define RVT_S_WAIT_DMA_DESC 0x2000
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#define RVT_S_WAIT_KMEM 0x4000
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#define RVT_S_WAIT_PSN 0x8000
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#define RVT_S_WAIT_ACK 0x10000
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#define RVT_S_SEND_ONE 0x20000
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#define RVT_S_UNLIMITED_CREDIT 0x40000
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#define RVT_S_AHG_VALID 0x80000
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#define RVT_S_AHG_CLEAR 0x100000
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#define RVT_S_ECN 0x200000
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#define RVT_S_WAIT_TX 0x0800
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#define RVT_S_WAIT_DMA_DESC 0x1000
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#define RVT_S_WAIT_KMEM 0x2000
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#define RVT_S_WAIT_PSN 0x4000
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#define RVT_S_WAIT_ACK 0x8000
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#define RVT_S_SEND_ONE 0x10000
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#define RVT_S_UNLIMITED_CREDIT 0x20000
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#define RVT_S_ECN 0x40000
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#define RVT_S_MAX_BIT_MASK 0x800000
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/*
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* Drivers should use s_flags starting with bit 31 down to the bit next to
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* RVT_S_MAX_BIT_MASK
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*/
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/*
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* Wait flags that would prevent any packet type from being sent.
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*/
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#define RVT_S_ANY_WAIT_IO \
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(RVT_S_WAIT_PIO | RVT_S_WAIT_PIO_DRAIN | RVT_S_WAIT_TX | \
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(RVT_S_WAIT_PIO | RVT_S_WAIT_TX | \
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RVT_S_WAIT_DMA_DESC | RVT_S_WAIT_KMEM)
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/*
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