[POWERPC] Make endianess of cfg_addr for indirect pci ops runtime
Make it so we do a runtime check to know if we need to write cfg_addr as big or little endian. This is needed if we want to allow 86xx support to co-exist in the same kernel as other 6xx PPCs. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
This commit is contained in:
Kumar Gala
Родитель
d5269966e5
Коммит
2e56ff206b
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@ -411,11 +411,6 @@ config PPC_INDIRECT_PCI
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default y if 40x || 44x
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default n
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config PPC_INDIRECT_PCI_BE
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bool
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depends PPC_INDIRECT_PCI
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default n
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config EISA
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bool
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@ -553,7 +553,8 @@ static void __init mpc82xx_add_bridge(struct device_node *np)
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setup_indirect_pci(hose,
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r.start + offsetof(pci_cpm2_t, pci_cfg_addr),
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r.start + offsetof(pci_cpm2_t, pci_cfg_data));
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r.start + offsetof(pci_cpm2_t, pci_cfg_data),
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0);
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pci_process_bridge_OF_ranges(hose, np, 1);
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}
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@ -74,11 +74,11 @@ int __init mpc83xx_add_bridge(struct device_node *dev)
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*/
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/* PCI 1 */
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if ((rsrc.start & 0xfffff) == 0x8500) {
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setup_indirect_pci(hose, immr + 0x8300, immr + 0x8304);
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setup_indirect_pci(hose, immr + 0x8300, immr + 0x8304, 0);
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}
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/* PCI 2 */
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if ((rsrc.start & 0xfffff) == 0x8600) {
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setup_indirect_pci(hose, immr + 0x8380, immr + 0x8384);
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setup_indirect_pci(hose, immr + 0x8380, immr + 0x8384, 0);
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primary = 0;
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}
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@ -51,7 +51,6 @@ config MPC85xx
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bool
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select PPC_UDBG_16550
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select PPC_INDIRECT_PCI if PCI
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select PPC_INDIRECT_PCI_BE if PCI
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select MPIC
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select FSL_PCI if PCI
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select SERIAL_8250_SHARE_IRQ if SERIAL_8250
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@ -14,7 +14,6 @@ endchoice
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config MPC8641
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bool
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select PPC_INDIRECT_PCI_BE if PCI
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select FSL_PCI if PCI
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select PPC_UDBG_16550
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select MPIC
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@ -181,7 +181,7 @@ setup_python(struct pci_controller *hose, struct device_node *dev)
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}
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iounmap(reg);
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setup_indirect_pci(hose, r.start + 0xf8000, r.start + 0xf8010);
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setup_indirect_pci(hose, r.start + 0xf8000, r.start + 0xf8010, 0);
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}
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/* Marvell Discovery II based Pegasos 2 */
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@ -277,13 +277,14 @@ chrp_find_bridges(void)
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hose->cfg_data = p;
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gg2_pci_config_base = p;
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} else if (is_pegasos == 1) {
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setup_indirect_pci(hose, 0xfec00cf8, 0xfee00cfc);
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setup_indirect_pci(hose, 0xfec00cf8, 0xfee00cfc, 0);
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} else if (is_pegasos == 2) {
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setup_peg2(hose, dev);
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} else if (!strncmp(model, "IBM,CPC710", 10)) {
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setup_indirect_pci(hose,
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r.start + 0x000f8000,
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r.start + 0x000f8010);
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r.start + 0x000f8010,
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0);
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if (index == 0) {
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dma = of_get_property(dev, "system-dma-base",
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&len);
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@ -73,7 +73,7 @@ static int __init linkstation_add_bridge(struct device_node *dev)
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return -ENOMEM;
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hose->first_busno = bus_range ? bus_range[0] : 0;
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hose->last_busno = bus_range ? bus_range[1] : 0xff;
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setup_indirect_pci(hose, 0xfec00000, 0xfee00000);
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setup_indirect_pci(hose, 0xfec00000, 0xfee00000, 0);
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/* Interpret the "ranges" property */
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/* This also maps the I/O region and sets isa_io/mem_base */
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@ -185,7 +185,8 @@ int __init fsl_add_bridge(struct device_node *dev, int is_primary)
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hose->first_busno = bus_range ? bus_range[0] : 0x0;
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hose->last_busno = bus_range ? bus_range[1] : 0xff;
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setup_indirect_pci(hose, rsrc.start, rsrc.start + 0x4);
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setup_indirect_pci(hose, rsrc.start, rsrc.start + 0x4,
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PPC_INDIRECT_TYPE_BIG_ENDIAN);
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setup_pci_cmd(hose);
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/* check PCI express link status */
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@ -55,7 +55,7 @@ static inline void grackle_set_loop_snoop(struct pci_controller *bp, int enable)
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void __init setup_grackle(struct pci_controller *hose)
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{
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setup_indirect_pci(hose, 0xfec00000, 0xfee00000);
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setup_indirect_pci(hose, 0xfec00000, 0xfee00000, 0);
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if (machine_is_compatible("PowerMac1,1"))
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pci_assign_all_buses = 1;
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if (machine_is_compatible("AAPL,PowerBook1998"))
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@ -20,12 +20,6 @@
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#include <asm/pci-bridge.h>
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#include <asm/machdep.h>
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#ifdef CONFIG_PPC_INDIRECT_PCI_BE
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#define PCI_CFG_OUT out_be32
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#else
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#define PCI_CFG_OUT out_le32
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#endif
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static int
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indirect_read_config(struct pci_bus *bus, unsigned int devfn, int offset,
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int len, u32 *val)
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@ -58,9 +52,12 @@ indirect_read_config(struct pci_bus *bus, unsigned int devfn, int offset,
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else
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reg = offset & 0xfc;
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PCI_CFG_OUT(hose->cfg_addr,
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(0x80000000 | (bus_no << 16)
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| (devfn << 8) | reg | cfg_type));
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if (hose->indirect_type & PPC_INDIRECT_TYPE_BIG_ENDIAN)
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out_be32(hose->cfg_addr, (0x80000000 | (bus_no << 16) |
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(devfn << 8) | reg | cfg_type));
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else
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out_le32(hose->cfg_addr, (0x80000000 | (bus_no << 16) |
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(devfn << 8) | reg | cfg_type));
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/*
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* Note: the caller has already checked that offset is
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@ -113,9 +110,12 @@ indirect_write_config(struct pci_bus *bus, unsigned int devfn, int offset,
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else
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reg = offset & 0xfc;
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PCI_CFG_OUT(hose->cfg_addr,
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(0x80000000 | (bus_no << 16)
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| (devfn << 8) | reg | cfg_type));
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if (hose->indirect_type & PPC_INDIRECT_TYPE_BIG_ENDIAN)
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out_be32(hose->cfg_addr, (0x80000000 | (bus_no << 16) |
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(devfn << 8) | reg | cfg_type));
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else
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out_le32(hose->cfg_addr, (0x80000000 | (bus_no << 16) |
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(devfn << 8) | reg | cfg_type));
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/* surpress setting of PCI_PRIMARY_BUS */
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if (hose->indirect_type & PPC_INDIRECT_TYPE_SURPRESS_PRIMARY_BUS)
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@ -149,7 +149,7 @@ static struct pci_ops indirect_pci_ops =
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};
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void __init
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setup_indirect_pci(struct pci_controller* hose, u32 cfg_addr, u32 cfg_data)
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setup_indirect_pci(struct pci_controller* hose, u32 cfg_addr, u32 cfg_data, u32 flags)
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{
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unsigned long base = cfg_addr & PAGE_MASK;
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void __iomem *mbase;
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@ -144,7 +144,7 @@ static int __init mv64x60_add_bridge(struct device_node *dev)
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hose->first_busno = bus_range ? bus_range[0] : 0;
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hose->last_busno = bus_range ? bus_range[1] : 0xff;
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setup_indirect_pci(hose, rsrc.start, rsrc.start + 4);
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setup_indirect_pci(hose, rsrc.start, rsrc.start + 4, 0);
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hose->self_busno = hose->first_busno;
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printk(KERN_INFO "Found MV64x60 PCI host bridge at 0x%016llx. "
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@ -49,11 +49,13 @@ struct pci_controller {
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* hanging if we don't have link and try to do config cycles to
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* anything but the PHB. Only allow talking to the PHB if this is
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* set.
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* BIG_ENDIAN - cfg_addr is a big endian register
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*/
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#define PPC_INDIRECT_TYPE_SET_CFG_TYPE (0x00000001)
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#define PPC_INDIRECT_TYPE_EXT_REG (0x00000002)
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#define PPC_INDIRECT_TYPE_SURPRESS_PRIMARY_BUS (0x00000004)
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#define PPC_INDIRECT_TYPE_NO_PCIE_LINK (0x00000008)
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#define PPC_INDIRECT_TYPE_BIG_ENDIAN (0x00000010)
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u32 indirect_type;
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/* Currently, we limit ourselves to 1 IO range and 3 mem
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@ -88,7 +90,7 @@ extern int early_find_capability(struct pci_controller *hose, int bus,
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int dev_fn, int cap);
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extern void setup_indirect_pci(struct pci_controller* hose,
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u32 cfg_addr, u32 cfg_data);
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u32 cfg_addr, u32 cfg_data, u32 flags);
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extern void setup_grackle(struct pci_controller *hose);
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#else
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