net: phy: at803x: Allow specifying the RGMII RX clock delay via phy mode
at803x currently automatically enables the RGMII TX clock delay when the phy interface mode is PHY_INTERFACE_MODE_RGMII_TXID. The same should be done when PHY_INTERFACE_MODE_RGMII_ID is specified. Use a similar logic to enable the RGMII RX clock delay as well. at803x_context_{save,restore} were not touched because these are only used on AR8030 which is a RMII phy (RGMII clock delays are irrelevant). Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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e15bb4c64d
Коммит
2e5f9f281e
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@ -36,8 +36,10 @@
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#define AT803X_INSR 0x0013
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#define AT803X_INSR 0x0013
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#define AT803X_DEBUG_ADDR 0x1D
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#define AT803X_DEBUG_ADDR 0x1D
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#define AT803X_DEBUG_DATA 0x1E
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#define AT803X_DEBUG_DATA 0x1E
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#define AT803X_DEBUG_SYSTEM_MODE_CTRL 0x05
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#define AT803X_DEBUG_REG_0 0x00
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#define AT803X_DEBUG_RGMII_TX_CLK_DLY BIT(8)
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#define AT803X_DEBUG_RX_CLK_DLY_EN BIT(15)
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#define AT803X_DEBUG_REG_5 0x05
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#define AT803X_DEBUG_TX_CLK_DLY_EN BIT(8)
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#define ATH8030_PHY_ID 0x004dd076
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#define ATH8030_PHY_ID 0x004dd076
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#define ATH8031_PHY_ID 0x004dd074
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#define ATH8031_PHY_ID 0x004dd074
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@ -61,6 +63,46 @@ struct at803x_context {
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u16 led_control;
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u16 led_control;
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};
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};
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static int at803x_debug_reg_read(struct phy_device *phydev, u16 reg)
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{
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int ret;
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ret = phy_write(phydev, AT803X_DEBUG_ADDR, reg);
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if (ret < 0)
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return ret;
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return phy_read(phydev, AT803X_DEBUG_DATA);
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}
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static int at803x_debug_reg_mask(struct phy_device *phydev, u16 reg,
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u16 clear, u16 set)
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{
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u16 val;
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int ret;
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ret = at803x_debug_reg_read(phydev, reg);
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if (ret < 0)
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return ret;
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val = ret & 0xffff;
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val &= ~clear;
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val |= set;
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return phy_write(phydev, AT803X_DEBUG_DATA, val);
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}
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static inline int at803x_enable_rx_delay(struct phy_device *phydev)
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{
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return at803x_debug_reg_mask(phydev, AT803X_DEBUG_REG_0, 0,
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AT803X_DEBUG_RX_CLK_DLY_EN);
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}
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static inline int at803x_enable_tx_delay(struct phy_device *phydev)
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{
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return at803x_debug_reg_mask(phydev, AT803X_DEBUG_REG_5, 0,
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AT803X_DEBUG_TX_CLK_DLY_EN);
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}
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/* save relevant PHY registers to private copy */
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/* save relevant PHY registers to private copy */
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static void at803x_context_save(struct phy_device *phydev,
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static void at803x_context_save(struct phy_device *phydev,
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struct at803x_context *context)
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struct at803x_context *context)
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@ -217,14 +259,17 @@ static int at803x_config_init(struct phy_device *phydev)
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if (ret < 0)
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if (ret < 0)
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return ret;
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return ret;
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if (phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID) {
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if (phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID ||
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ret = phy_write(phydev, AT803X_DEBUG_ADDR,
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phydev->interface == PHY_INTERFACE_MODE_RGMII_ID) {
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AT803X_DEBUG_SYSTEM_MODE_CTRL);
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ret = at803x_enable_rx_delay(phydev);
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if (ret)
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if (ret < 0)
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return ret;
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return ret;
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ret = phy_write(phydev, AT803X_DEBUG_DATA,
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}
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AT803X_DEBUG_RGMII_TX_CLK_DLY);
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if (ret)
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if (phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID ||
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phydev->interface == PHY_INTERFACE_MODE_RGMII_ID) {
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ret = at803x_enable_tx_delay(phydev);
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if (ret < 0)
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return ret;
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return ret;
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}
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}
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