Merge branch 'drm-fixes-4.4' of git://people.freedesktop.org/~agd5f/linux into drm-fixes
Radeon and amdgpu fixes for 4.4: - DPM fixes for r7xx devices - VCE fixes for Stoney - GPUVM fixes - Scheduler fixes * 'drm-fixes-4.4' of git://people.freedesktop.org/~agd5f/linux: drm/radeon: make some dpm errors debug only drm/radeon: make rv770_set_sw_state failures non-fatal drm/amdgpu: move dependency handling out of atomic section v2 drm/amdgpu: optimize scheduler fence handling drm/amdgpu: remove vm->mutex drm/amdgpu: add mutex for ba_va->valids/invalids drm/amdgpu: adapt vce session create interface changes drm/amdgpu: vce use multiple cache surface starting from stoney drm/amdgpu: reset vce trap interrupt flag
This commit is contained in:
Коммит
2f1371614a
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@ -496,6 +496,7 @@ struct amdgpu_bo_va_mapping {
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/* bo virtual addresses in a specific vm */
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struct amdgpu_bo_va {
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struct mutex mutex;
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/* protected by bo being reserved */
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struct list_head bo_list;
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struct fence *last_pt_update;
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@ -928,8 +929,6 @@ struct amdgpu_vm_id {
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};
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struct amdgpu_vm {
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struct mutex mutex;
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struct rb_root va;
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/* protecting invalidated */
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@ -784,8 +784,6 @@ int amdgpu_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp)
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{
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struct amdgpu_device *adev = dev->dev_private;
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union drm_amdgpu_cs *cs = data;
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struct amdgpu_fpriv *fpriv = filp->driver_priv;
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struct amdgpu_vm *vm = &fpriv->vm;
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struct amdgpu_cs_parser parser = {};
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bool reserved_buffers = false;
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int i, r;
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@ -803,7 +801,6 @@ int amdgpu_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp)
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r = amdgpu_cs_handle_lockup(adev, r);
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return r;
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}
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mutex_lock(&vm->mutex);
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r = amdgpu_cs_parser_relocs(&parser);
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if (r == -ENOMEM)
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DRM_ERROR("Not enough memory for command submission!\n");
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@ -888,7 +885,6 @@ int amdgpu_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp)
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out:
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amdgpu_cs_parser_fini(&parser, r, reserved_buffers);
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mutex_unlock(&vm->mutex);
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r = amdgpu_cs_handle_lockup(adev, r);
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return r;
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}
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@ -115,12 +115,9 @@ int amdgpu_gem_object_open(struct drm_gem_object *obj, struct drm_file *file_pri
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struct amdgpu_vm *vm = &fpriv->vm;
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struct amdgpu_bo_va *bo_va;
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int r;
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mutex_lock(&vm->mutex);
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r = amdgpu_bo_reserve(rbo, false);
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if (r) {
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mutex_unlock(&vm->mutex);
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if (r)
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return r;
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}
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bo_va = amdgpu_vm_bo_find(vm, rbo);
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if (!bo_va) {
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@ -129,7 +126,6 @@ int amdgpu_gem_object_open(struct drm_gem_object *obj, struct drm_file *file_pri
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++bo_va->ref_count;
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}
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amdgpu_bo_unreserve(rbo);
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mutex_unlock(&vm->mutex);
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return 0;
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}
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@ -142,10 +138,8 @@ void amdgpu_gem_object_close(struct drm_gem_object *obj,
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struct amdgpu_vm *vm = &fpriv->vm;
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struct amdgpu_bo_va *bo_va;
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int r;
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mutex_lock(&vm->mutex);
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r = amdgpu_bo_reserve(rbo, true);
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if (r) {
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mutex_unlock(&vm->mutex);
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dev_err(adev->dev, "leaking bo va because "
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"we fail to reserve bo (%d)\n", r);
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return;
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@ -157,7 +151,6 @@ void amdgpu_gem_object_close(struct drm_gem_object *obj,
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}
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}
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amdgpu_bo_unreserve(rbo);
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mutex_unlock(&vm->mutex);
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}
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static int amdgpu_gem_handle_lockup(struct amdgpu_device *adev, int r)
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@ -553,7 +546,6 @@ int amdgpu_gem_va_ioctl(struct drm_device *dev, void *data,
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gobj = drm_gem_object_lookup(dev, filp, args->handle);
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if (gobj == NULL)
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return -ENOENT;
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mutex_lock(&fpriv->vm.mutex);
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rbo = gem_to_amdgpu_bo(gobj);
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INIT_LIST_HEAD(&list);
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INIT_LIST_HEAD(&duplicates);
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@ -568,7 +560,6 @@ int amdgpu_gem_va_ioctl(struct drm_device *dev, void *data,
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}
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r = ttm_eu_reserve_buffers(&ticket, &list, true, &duplicates);
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if (r) {
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mutex_unlock(&fpriv->vm.mutex);
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drm_gem_object_unreference_unlocked(gobj);
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return r;
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}
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@ -577,7 +568,6 @@ int amdgpu_gem_va_ioctl(struct drm_device *dev, void *data,
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if (!bo_va) {
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ttm_eu_backoff_reservation(&ticket, &list);
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drm_gem_object_unreference_unlocked(gobj);
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mutex_unlock(&fpriv->vm.mutex);
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return -ENOENT;
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}
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@ -602,7 +592,7 @@ int amdgpu_gem_va_ioctl(struct drm_device *dev, void *data,
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ttm_eu_backoff_reservation(&ticket, &list);
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if (!r && !(args->flags & AMDGPU_VM_DELAY_UPDATE))
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amdgpu_gem_va_update_vm(adev, bo_va, args->operation);
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mutex_unlock(&fpriv->vm.mutex);
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drm_gem_object_unreference_unlocked(gobj);
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return r;
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}
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@ -392,7 +392,10 @@ int amdgpu_vce_get_create_msg(struct amdgpu_ring *ring, uint32_t handle,
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ib->ptr[ib->length_dw++] = 0x00000001; /* session cmd */
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ib->ptr[ib->length_dw++] = handle;
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ib->ptr[ib->length_dw++] = 0x00000030; /* len */
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if ((ring->adev->vce.fw_version >> 24) >= 52)
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ib->ptr[ib->length_dw++] = 0x00000040; /* len */
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else
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ib->ptr[ib->length_dw++] = 0x00000030; /* len */
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ib->ptr[ib->length_dw++] = 0x01000001; /* create cmd */
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ib->ptr[ib->length_dw++] = 0x00000000;
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ib->ptr[ib->length_dw++] = 0x00000042;
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@ -404,6 +407,12 @@ int amdgpu_vce_get_create_msg(struct amdgpu_ring *ring, uint32_t handle,
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ib->ptr[ib->length_dw++] = 0x00000100;
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ib->ptr[ib->length_dw++] = 0x0000000c;
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ib->ptr[ib->length_dw++] = 0x00000000;
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if ((ring->adev->vce.fw_version >> 24) >= 52) {
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ib->ptr[ib->length_dw++] = 0x00000000;
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ib->ptr[ib->length_dw++] = 0x00000000;
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ib->ptr[ib->length_dw++] = 0x00000000;
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ib->ptr[ib->length_dw++] = 0x00000000;
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}
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ib->ptr[ib->length_dw++] = 0x00000014; /* len */
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ib->ptr[ib->length_dw++] = 0x05000005; /* feedback buffer */
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@ -922,8 +922,9 @@ int amdgpu_vm_clear_invalids(struct amdgpu_device *adev,
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bo_va = list_first_entry(&vm->invalidated,
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struct amdgpu_bo_va, vm_status);
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spin_unlock(&vm->status_lock);
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mutex_lock(&bo_va->mutex);
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r = amdgpu_vm_bo_update(adev, bo_va, NULL);
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mutex_unlock(&bo_va->mutex);
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if (r)
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return r;
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@ -967,7 +968,7 @@ struct amdgpu_bo_va *amdgpu_vm_bo_add(struct amdgpu_device *adev,
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INIT_LIST_HEAD(&bo_va->valids);
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INIT_LIST_HEAD(&bo_va->invalids);
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INIT_LIST_HEAD(&bo_va->vm_status);
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mutex_init(&bo_va->mutex);
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list_add_tail(&bo_va->bo_list, &bo->va);
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return bo_va;
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@ -1045,7 +1046,9 @@ int amdgpu_vm_bo_map(struct amdgpu_device *adev,
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mapping->offset = offset;
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mapping->flags = flags;
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mutex_lock(&bo_va->mutex);
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list_add(&mapping->list, &bo_va->invalids);
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mutex_unlock(&bo_va->mutex);
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spin_lock(&vm->it_lock);
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interval_tree_insert(&mapping->it, &vm->va);
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spin_unlock(&vm->it_lock);
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@ -1121,7 +1124,7 @@ int amdgpu_vm_bo_unmap(struct amdgpu_device *adev,
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bool valid = true;
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saddr /= AMDGPU_GPU_PAGE_SIZE;
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mutex_lock(&bo_va->mutex);
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list_for_each_entry(mapping, &bo_va->valids, list) {
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if (mapping->it.start == saddr)
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break;
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@ -1135,10 +1138,12 @@ int amdgpu_vm_bo_unmap(struct amdgpu_device *adev,
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break;
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}
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if (&mapping->list == &bo_va->invalids)
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if (&mapping->list == &bo_va->invalids) {
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mutex_unlock(&bo_va->mutex);
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return -ENOENT;
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}
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}
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mutex_unlock(&bo_va->mutex);
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list_del(&mapping->list);
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spin_lock(&vm->it_lock);
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interval_tree_remove(&mapping->it, &vm->va);
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@ -1190,8 +1195,8 @@ void amdgpu_vm_bo_rmv(struct amdgpu_device *adev,
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spin_unlock(&vm->it_lock);
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kfree(mapping);
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}
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fence_put(bo_va->last_pt_update);
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mutex_destroy(&bo_va->mutex);
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kfree(bo_va);
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}
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@ -1236,7 +1241,6 @@ int amdgpu_vm_init(struct amdgpu_device *adev, struct amdgpu_vm *vm)
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vm->ids[i].id = 0;
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vm->ids[i].flushed_updates = NULL;
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}
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mutex_init(&vm->mutex);
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vm->va = RB_ROOT;
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spin_lock_init(&vm->status_lock);
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INIT_LIST_HEAD(&vm->invalidated);
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@ -1320,7 +1324,6 @@ void amdgpu_vm_fini(struct amdgpu_device *adev, struct amdgpu_vm *vm)
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fence_put(vm->ids[i].flushed_updates);
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}
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mutex_destroy(&vm->mutex);
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}
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/**
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@ -40,6 +40,9 @@
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#define GRBM_GFX_INDEX__VCE_INSTANCE__SHIFT 0x04
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#define GRBM_GFX_INDEX__VCE_INSTANCE_MASK 0x10
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#define mmVCE_LMI_VCPU_CACHE_40BIT_BAR0 0x8616
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#define mmVCE_LMI_VCPU_CACHE_40BIT_BAR1 0x8617
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#define mmVCE_LMI_VCPU_CACHE_40BIT_BAR2 0x8618
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#define VCE_V3_0_FW_SIZE (384 * 1024)
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#define VCE_V3_0_STACK_SIZE (64 * 1024)
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@ -130,9 +133,11 @@ static int vce_v3_0_start(struct amdgpu_device *adev)
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/* set BUSY flag */
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WREG32_P(mmVCE_STATUS, 1, ~1);
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WREG32_P(mmVCE_VCPU_CNTL, VCE_VCPU_CNTL__CLK_EN_MASK,
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~VCE_VCPU_CNTL__CLK_EN_MASK);
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if (adev->asic_type >= CHIP_STONEY)
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WREG32_P(mmVCE_VCPU_CNTL, 1, ~0x200001);
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else
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WREG32_P(mmVCE_VCPU_CNTL, VCE_VCPU_CNTL__CLK_EN_MASK,
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~VCE_VCPU_CNTL__CLK_EN_MASK);
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WREG32_P(mmVCE_SOFT_RESET,
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VCE_SOFT_RESET__ECPU_SOFT_RESET_MASK,
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@ -391,8 +396,12 @@ static void vce_v3_0_mc_resume(struct amdgpu_device *adev, int idx)
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WREG32(mmVCE_LMI_SWAP_CNTL, 0);
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WREG32(mmVCE_LMI_SWAP_CNTL1, 0);
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WREG32(mmVCE_LMI_VM_CTRL, 0);
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WREG32(mmVCE_LMI_VCPU_CACHE_40BIT_BAR, (adev->vce.gpu_addr >> 8));
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if (adev->asic_type >= CHIP_STONEY) {
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WREG32(mmVCE_LMI_VCPU_CACHE_40BIT_BAR0, (adev->vce.gpu_addr >> 8));
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WREG32(mmVCE_LMI_VCPU_CACHE_40BIT_BAR1, (adev->vce.gpu_addr >> 8));
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WREG32(mmVCE_LMI_VCPU_CACHE_40BIT_BAR2, (adev->vce.gpu_addr >> 8));
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} else
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WREG32(mmVCE_LMI_VCPU_CACHE_40BIT_BAR, (adev->vce.gpu_addr >> 8));
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offset = AMDGPU_VCE_FIRMWARE_OFFSET;
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size = VCE_V3_0_FW_SIZE;
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WREG32(mmVCE_VCPU_CACHE_OFFSET0, offset & 0x7fffffff);
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|
@ -576,6 +585,11 @@ static int vce_v3_0_process_interrupt(struct amdgpu_device *adev,
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struct amdgpu_iv_entry *entry)
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{
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DRM_DEBUG("IH: VCE\n");
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WREG32_P(mmVCE_SYS_INT_STATUS,
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VCE_SYS_INT_STATUS__VCE_SYS_INT_TRAP_INTERRUPT_INT_MASK,
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~VCE_SYS_INT_STATUS__VCE_SYS_INT_TRAP_INTERRUPT_INT_MASK);
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|
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switch (entry->src_data) {
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case 0:
|
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amdgpu_fence_process(&adev->vce.ring[0]);
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|
|
|
@ -30,8 +30,7 @@
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#define CREATE_TRACE_POINTS
|
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#include "gpu_sched_trace.h"
|
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|
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static struct amd_sched_job *
|
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amd_sched_entity_pop_job(struct amd_sched_entity *entity);
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static bool amd_sched_entity_is_ready(struct amd_sched_entity *entity);
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static void amd_sched_wakeup(struct amd_gpu_scheduler *sched);
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|
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struct kmem_cache *sched_fence_slab;
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|
@ -64,36 +63,36 @@ static void amd_sched_rq_remove_entity(struct amd_sched_rq *rq,
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}
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|
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/**
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* Select next job from a specified run queue with round robin policy.
|
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* Return NULL if nothing available.
|
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* Select an entity which could provide a job to run
|
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*
|
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* @rq The run queue to check.
|
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*
|
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* Try to find a ready entity, returns NULL if none found.
|
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*/
|
||||
static struct amd_sched_job *
|
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amd_sched_rq_select_job(struct amd_sched_rq *rq)
|
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static struct amd_sched_entity *
|
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amd_sched_rq_select_entity(struct amd_sched_rq *rq)
|
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{
|
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struct amd_sched_entity *entity;
|
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struct amd_sched_job *sched_job;
|
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|
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spin_lock(&rq->lock);
|
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|
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entity = rq->current_entity;
|
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if (entity) {
|
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list_for_each_entry_continue(entity, &rq->entities, list) {
|
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sched_job = amd_sched_entity_pop_job(entity);
|
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if (sched_job) {
|
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if (amd_sched_entity_is_ready(entity)) {
|
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rq->current_entity = entity;
|
||||
spin_unlock(&rq->lock);
|
||||
return sched_job;
|
||||
return entity;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
list_for_each_entry(entity, &rq->entities, list) {
|
||||
|
||||
sched_job = amd_sched_entity_pop_job(entity);
|
||||
if (sched_job) {
|
||||
if (amd_sched_entity_is_ready(entity)) {
|
||||
rq->current_entity = entity;
|
||||
spin_unlock(&rq->lock);
|
||||
return sched_job;
|
||||
return entity;
|
||||
}
|
||||
|
||||
if (entity == rq->current_entity)
|
||||
|
@ -176,6 +175,24 @@ static bool amd_sched_entity_is_idle(struct amd_sched_entity *entity)
|
|||
return false;
|
||||
}
|
||||
|
||||
/**
|
||||
* Check if entity is ready
|
||||
*
|
||||
* @entity The pointer to a valid scheduler entity
|
||||
*
|
||||
* Return true if entity could provide a job.
|
||||
*/
|
||||
static bool amd_sched_entity_is_ready(struct amd_sched_entity *entity)
|
||||
{
|
||||
if (kfifo_is_empty(&entity->job_queue))
|
||||
return false;
|
||||
|
||||
if (ACCESS_ONCE(entity->dependency))
|
||||
return false;
|
||||
|
||||
return true;
|
||||
}
|
||||
|
||||
/**
|
||||
* Destroy a context entity
|
||||
*
|
||||
|
@ -211,32 +228,53 @@ static void amd_sched_entity_wakeup(struct fence *f, struct fence_cb *cb)
|
|||
amd_sched_wakeup(entity->sched);
|
||||
}
|
||||
|
||||
static bool amd_sched_entity_add_dependency_cb(struct amd_sched_entity *entity)
|
||||
{
|
||||
struct amd_gpu_scheduler *sched = entity->sched;
|
||||
struct fence * fence = entity->dependency;
|
||||
struct amd_sched_fence *s_fence;
|
||||
|
||||
if (fence->context == entity->fence_context) {
|
||||
/* We can ignore fences from ourself */
|
||||
fence_put(entity->dependency);
|
||||
return false;
|
||||
}
|
||||
|
||||
s_fence = to_amd_sched_fence(fence);
|
||||
if (s_fence && s_fence->sched == sched) {
|
||||
/* Fence is from the same scheduler */
|
||||
if (test_bit(AMD_SCHED_FENCE_SCHEDULED_BIT, &fence->flags)) {
|
||||
/* Ignore it when it is already scheduled */
|
||||
fence_put(entity->dependency);
|
||||
return false;
|
||||
}
|
||||
|
||||
/* Wait for fence to be scheduled */
|
||||
entity->cb.func = amd_sched_entity_wakeup;
|
||||
list_add_tail(&entity->cb.node, &s_fence->scheduled_cb);
|
||||
return true;
|
||||
}
|
||||
|
||||
if (!fence_add_callback(entity->dependency, &entity->cb,
|
||||
amd_sched_entity_wakeup))
|
||||
return true;
|
||||
|
||||
fence_put(entity->dependency);
|
||||
return false;
|
||||
}
|
||||
|
||||
static struct amd_sched_job *
|
||||
amd_sched_entity_pop_job(struct amd_sched_entity *entity)
|
||||
{
|
||||
struct amd_gpu_scheduler *sched = entity->sched;
|
||||
struct amd_sched_job *sched_job;
|
||||
|
||||
if (ACCESS_ONCE(entity->dependency))
|
||||
return NULL;
|
||||
|
||||
if (!kfifo_out_peek(&entity->job_queue, &sched_job, sizeof(sched_job)))
|
||||
return NULL;
|
||||
|
||||
while ((entity->dependency = sched->ops->dependency(sched_job))) {
|
||||
|
||||
if (entity->dependency->context == entity->fence_context) {
|
||||
/* We can ignore fences from ourself */
|
||||
fence_put(entity->dependency);
|
||||
continue;
|
||||
}
|
||||
|
||||
if (fence_add_callback(entity->dependency, &entity->cb,
|
||||
amd_sched_entity_wakeup))
|
||||
fence_put(entity->dependency);
|
||||
else
|
||||
while ((entity->dependency = sched->ops->dependency(sched_job)))
|
||||
if (amd_sched_entity_add_dependency_cb(entity))
|
||||
return NULL;
|
||||
}
|
||||
|
||||
return sched_job;
|
||||
}
|
||||
|
@ -304,22 +342,22 @@ static void amd_sched_wakeup(struct amd_gpu_scheduler *sched)
|
|||
}
|
||||
|
||||
/**
|
||||
* Select next to run
|
||||
* Select next entity to process
|
||||
*/
|
||||
static struct amd_sched_job *
|
||||
amd_sched_select_job(struct amd_gpu_scheduler *sched)
|
||||
static struct amd_sched_entity *
|
||||
amd_sched_select_entity(struct amd_gpu_scheduler *sched)
|
||||
{
|
||||
struct amd_sched_job *sched_job;
|
||||
struct amd_sched_entity *entity;
|
||||
|
||||
if (!amd_sched_ready(sched))
|
||||
return NULL;
|
||||
|
||||
/* Kernel run queue has higher priority than normal run queue*/
|
||||
sched_job = amd_sched_rq_select_job(&sched->kernel_rq);
|
||||
if (sched_job == NULL)
|
||||
sched_job = amd_sched_rq_select_job(&sched->sched_rq);
|
||||
entity = amd_sched_rq_select_entity(&sched->kernel_rq);
|
||||
if (entity == NULL)
|
||||
entity = amd_sched_rq_select_entity(&sched->sched_rq);
|
||||
|
||||
return sched_job;
|
||||
return entity;
|
||||
}
|
||||
|
||||
static void amd_sched_process_job(struct fence *f, struct fence_cb *cb)
|
||||
|
@ -381,13 +419,16 @@ static int amd_sched_main(void *param)
|
|||
unsigned long flags;
|
||||
|
||||
wait_event_interruptible(sched->wake_up_worker,
|
||||
kthread_should_stop() ||
|
||||
(sched_job = amd_sched_select_job(sched)));
|
||||
(entity = amd_sched_select_entity(sched)) ||
|
||||
kthread_should_stop());
|
||||
|
||||
if (!entity)
|
||||
continue;
|
||||
|
||||
sched_job = amd_sched_entity_pop_job(entity);
|
||||
if (!sched_job)
|
||||
continue;
|
||||
|
||||
entity = sched_job->s_entity;
|
||||
s_fence = sched_job->s_fence;
|
||||
|
||||
if (sched->timeout != MAX_SCHEDULE_TIMEOUT) {
|
||||
|
@ -400,6 +441,7 @@ static int amd_sched_main(void *param)
|
|||
|
||||
atomic_inc(&sched->hw_rq_count);
|
||||
fence = sched->ops->run_job(sched_job);
|
||||
amd_sched_fence_scheduled(s_fence);
|
||||
if (fence) {
|
||||
r = fence_add_callback(fence, &s_fence->cb,
|
||||
amd_sched_process_job);
|
||||
|
|
|
@ -27,6 +27,8 @@
|
|||
#include <linux/kfifo.h>
|
||||
#include <linux/fence.h>
|
||||
|
||||
#define AMD_SCHED_FENCE_SCHEDULED_BIT FENCE_FLAG_USER_BITS
|
||||
|
||||
struct amd_gpu_scheduler;
|
||||
struct amd_sched_rq;
|
||||
|
||||
|
@ -68,6 +70,7 @@ struct amd_sched_rq {
|
|||
struct amd_sched_fence {
|
||||
struct fence base;
|
||||
struct fence_cb cb;
|
||||
struct list_head scheduled_cb;
|
||||
struct amd_gpu_scheduler *sched;
|
||||
spinlock_t lock;
|
||||
void *owner;
|
||||
|
@ -134,7 +137,7 @@ void amd_sched_entity_push_job(struct amd_sched_job *sched_job);
|
|||
|
||||
struct amd_sched_fence *amd_sched_fence_create(
|
||||
struct amd_sched_entity *s_entity, void *owner);
|
||||
void amd_sched_fence_scheduled(struct amd_sched_fence *fence);
|
||||
void amd_sched_fence_signal(struct amd_sched_fence *fence);
|
||||
|
||||
|
||||
#endif
|
||||
|
|
|
@ -35,6 +35,8 @@ struct amd_sched_fence *amd_sched_fence_create(struct amd_sched_entity *s_entity
|
|||
fence = kmem_cache_zalloc(sched_fence_slab, GFP_KERNEL);
|
||||
if (fence == NULL)
|
||||
return NULL;
|
||||
|
||||
INIT_LIST_HEAD(&fence->scheduled_cb);
|
||||
fence->owner = owner;
|
||||
fence->sched = s_entity->sched;
|
||||
spin_lock_init(&fence->lock);
|
||||
|
@ -55,6 +57,17 @@ void amd_sched_fence_signal(struct amd_sched_fence *fence)
|
|||
FENCE_TRACE(&fence->base, "was already signaled\n");
|
||||
}
|
||||
|
||||
void amd_sched_fence_scheduled(struct amd_sched_fence *s_fence)
|
||||
{
|
||||
struct fence_cb *cur, *tmp;
|
||||
|
||||
set_bit(AMD_SCHED_FENCE_SCHEDULED_BIT, &s_fence->base.flags);
|
||||
list_for_each_entry_safe(cur, tmp, &s_fence->scheduled_cb, node) {
|
||||
list_del_init(&cur->node);
|
||||
cur->func(&s_fence->base, cur);
|
||||
}
|
||||
}
|
||||
|
||||
static const char *amd_sched_fence_get_driver_name(struct fence *fence)
|
||||
{
|
||||
return "amd_sched";
|
||||
|
|
|
@ -464,7 +464,7 @@ void rv730_stop_dpm(struct radeon_device *rdev)
|
|||
result = rv770_send_msg_to_smc(rdev, PPSMC_MSG_TwoLevelsDisabled);
|
||||
|
||||
if (result != PPSMC_Result_OK)
|
||||
DRM_ERROR("Could not force DPM to low\n");
|
||||
DRM_DEBUG("Could not force DPM to low\n");
|
||||
|
||||
WREG32_P(GENERAL_PWRMGT, 0, ~GLOBAL_PWRMGT_EN);
|
||||
|
||||
|
|
|
@ -193,7 +193,7 @@ void rv770_stop_dpm(struct radeon_device *rdev)
|
|||
result = rv770_send_msg_to_smc(rdev, PPSMC_MSG_TwoLevelsDisabled);
|
||||
|
||||
if (result != PPSMC_Result_OK)
|
||||
DRM_ERROR("Could not force DPM to low.\n");
|
||||
DRM_DEBUG("Could not force DPM to low.\n");
|
||||
|
||||
WREG32_P(GENERAL_PWRMGT, 0, ~GLOBAL_PWRMGT_EN);
|
||||
|
||||
|
@ -1418,7 +1418,7 @@ int rv770_resume_smc(struct radeon_device *rdev)
|
|||
int rv770_set_sw_state(struct radeon_device *rdev)
|
||||
{
|
||||
if (rv770_send_msg_to_smc(rdev, PPSMC_MSG_SwitchToSwState) != PPSMC_Result_OK)
|
||||
return -EINVAL;
|
||||
DRM_DEBUG("rv770_set_sw_state failed\n");
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
|
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