Merge branch 'Refactor-lan9303_xxx_packet_processing'
Egil Hjelmeland says: ==================== Refactor lan9303_xxx_packet_processing This series is purely non functional. It changes the lan9303_enable_packet_processing, lan9303_disable_packet_processing() to pass port number (0,1,2) as parameter instead of port offset. This aligns them with other functions in the module, and makes it possible to simplify the code. The lan9303_enable_packet_processing, lan9303_disable_packet_processing functions operate on port. Therefore rename the functions to reflect that as well. Reviewer pointed out lan9303_get_ethtool_stats would be better off with the use of a lan9303_read_switch_port(). So that was added to the series. Changes v3 -> v4: - Whitespace adjustments. Changes v2 -> v3: - Patch 1: Removed the change in lan9303_get_ethtool_stats - Added patch 4: rename lan9303_xxx_packet_processing - Added patch 5: refactor lan9303_get_ethtool_stats Changes v1 -> v2: - introduced lan9303_write_switch_port() in first patch - inserted LAN9303_NUM_PORTS patch - Use LAN9303_NUM_PORTS in last patch. Plus whitespace change. ==================== Signed-off-by: David S. Miller <davem@davemloft.net>
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2f23678c28
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@ -20,6 +20,8 @@
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#include "lan9303.h"
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#define LAN9303_NUM_PORTS 3
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/* 13.2 System Control and Status Registers
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* Multiply register number by 4 to get address offset.
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*/
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@ -159,9 +161,7 @@
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# define LAN9303_BM_EGRSS_PORT_TYPE_SPECIAL_TAG_PORT1 (BIT(9) | BIT(8))
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# define LAN9303_BM_EGRSS_PORT_TYPE_SPECIAL_TAG_PORT0 (BIT(1) | BIT(0))
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#define LAN9303_PORT_0_OFFSET 0x400
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#define LAN9303_PORT_1_OFFSET 0x800
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#define LAN9303_PORT_2_OFFSET 0xc00
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#define LAN9303_SWITCH_PORT_REG(port, reg0) (0x400 * (port) + (reg0))
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/* the built-in PHYs are of type LAN911X */
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#define MII_LAN911X_SPECIAL_MODES 0x12
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@ -428,6 +428,20 @@ on_error:
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return ret;
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}
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static int lan9303_write_switch_port(struct lan9303 *chip, int port,
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u16 regnum, u32 val)
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{
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return lan9303_write_switch_reg(
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chip, LAN9303_SWITCH_PORT_REG(port, regnum), val);
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}
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static int lan9303_read_switch_port(struct lan9303 *chip, int port,
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u16 regnum, u32 *val)
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{
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return lan9303_read_switch_reg(
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chip, LAN9303_SWITCH_PORT_REG(port, regnum), val);
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}
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static int lan9303_detect_phy_setup(struct lan9303 *chip)
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{
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int reg;
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@ -458,40 +472,37 @@ static int lan9303_detect_phy_setup(struct lan9303 *chip)
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return 0;
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}
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#define LAN9303_MAC_RX_CFG_OFFS (LAN9303_MAC_RX_CFG_0 - LAN9303_PORT_0_OFFSET)
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#define LAN9303_MAC_TX_CFG_OFFS (LAN9303_MAC_TX_CFG_0 - LAN9303_PORT_0_OFFSET)
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static int lan9303_disable_packet_processing(struct lan9303 *chip,
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unsigned int port)
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static int lan9303_disable_processing_port(struct lan9303 *chip,
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unsigned int port)
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{
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int ret;
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/* disable RX, but keep register reset default values else */
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ret = lan9303_write_switch_reg(chip, LAN9303_MAC_RX_CFG_OFFS + port,
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LAN9303_MAC_RX_CFG_X_REJECT_MAC_TYPES);
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ret = lan9303_write_switch_port(chip, port, LAN9303_MAC_RX_CFG_0,
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LAN9303_MAC_RX_CFG_X_REJECT_MAC_TYPES);
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if (ret)
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return ret;
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/* disable TX, but keep register reset default values else */
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return lan9303_write_switch_reg(chip, LAN9303_MAC_TX_CFG_OFFS + port,
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return lan9303_write_switch_port(chip, port, LAN9303_MAC_TX_CFG_0,
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LAN9303_MAC_TX_CFG_X_TX_IFG_CONFIG_DEFAULT |
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LAN9303_MAC_TX_CFG_X_TX_PAD_ENABLE);
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}
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static int lan9303_enable_packet_processing(struct lan9303 *chip,
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unsigned int port)
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static int lan9303_enable_processing_port(struct lan9303 *chip,
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unsigned int port)
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{
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int ret;
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/* enable RX and keep register reset default values else */
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ret = lan9303_write_switch_reg(chip, LAN9303_MAC_RX_CFG_OFFS + port,
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LAN9303_MAC_RX_CFG_X_REJECT_MAC_TYPES |
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LAN9303_MAC_RX_CFG_X_RX_ENABLE);
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ret = lan9303_write_switch_port(chip, port, LAN9303_MAC_RX_CFG_0,
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LAN9303_MAC_RX_CFG_X_REJECT_MAC_TYPES |
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LAN9303_MAC_RX_CFG_X_RX_ENABLE);
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if (ret)
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return ret;
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/* enable TX and keep register reset default values else */
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return lan9303_write_switch_reg(chip, LAN9303_MAC_TX_CFG_OFFS + port,
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return lan9303_write_switch_port(chip, port, LAN9303_MAC_TX_CFG_0,
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LAN9303_MAC_TX_CFG_X_TX_IFG_CONFIG_DEFAULT |
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LAN9303_MAC_TX_CFG_X_TX_PAD_ENABLE |
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LAN9303_MAC_TX_CFG_X_TX_ENABLE);
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@ -556,15 +567,16 @@ static int lan9303_handle_reset(struct lan9303 *chip)
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/* stop processing packets for all ports */
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static int lan9303_disable_processing(struct lan9303 *chip)
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{
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int ret;
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int p;
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ret = lan9303_disable_packet_processing(chip, LAN9303_PORT_0_OFFSET);
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if (ret)
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return ret;
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ret = lan9303_disable_packet_processing(chip, LAN9303_PORT_1_OFFSET);
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if (ret)
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return ret;
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return lan9303_disable_packet_processing(chip, LAN9303_PORT_2_OFFSET);
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for (p = 0; p < LAN9303_NUM_PORTS; p++) {
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int ret = lan9303_disable_processing_port(chip, p);
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if (ret)
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return ret;
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}
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return 0;
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}
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static int lan9303_check_device(struct lan9303 *chip)
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@ -634,7 +646,7 @@ static int lan9303_setup(struct dsa_switch *ds)
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if (ret)
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dev_err(chip->dev, "failed to separate ports %d\n", ret);
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ret = lan9303_enable_packet_processing(chip, LAN9303_PORT_0_OFFSET);
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ret = lan9303_enable_processing_port(chip, 0);
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if (ret)
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dev_err(chip->dev, "failed to re-enable switching %d\n", ret);
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@ -700,19 +712,18 @@ static void lan9303_get_ethtool_stats(struct dsa_switch *ds, int port,
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uint64_t *data)
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{
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struct lan9303 *chip = ds->priv;
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u32 reg;
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unsigned int u, poff;
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int ret;
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poff = port * 0x400;
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unsigned int u;
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for (u = 0; u < ARRAY_SIZE(lan9303_mib); u++) {
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ret = lan9303_read_switch_reg(chip,
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lan9303_mib[u].offset + poff,
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®);
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u32 reg;
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int ret;
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ret = lan9303_read_switch_port(
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chip, port, lan9303_mib[u].offset, ®);
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if (ret)
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dev_warn(chip->dev, "Reading status reg %u failed\n",
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lan9303_mib[u].offset + poff);
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dev_warn(chip->dev, "Reading status port %d reg %u failed\n",
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port, lan9303_mib[u].offset);
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data[u] = reg;
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}
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}
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@ -757,11 +768,8 @@ static int lan9303_port_enable(struct dsa_switch *ds, int port,
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/* enable internal packet processing */
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switch (port) {
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case 1:
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return lan9303_enable_packet_processing(chip,
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LAN9303_PORT_1_OFFSET);
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case 2:
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return lan9303_enable_packet_processing(chip,
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LAN9303_PORT_2_OFFSET);
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return lan9303_enable_processing_port(chip, port);
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default:
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dev_dbg(chip->dev,
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"Error: request to power up invalid port %d\n", port);
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/* disable internal packet processing */
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switch (port) {
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case 1:
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lan9303_disable_packet_processing(chip, LAN9303_PORT_1_OFFSET);
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lan9303_phy_write(ds, chip->phy_addr_sel_strap + 1,
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MII_BMCR, BMCR_PDOWN);
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break;
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case 2:
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lan9303_disable_packet_processing(chip, LAN9303_PORT_2_OFFSET);
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lan9303_phy_write(ds, chip->phy_addr_sel_strap + 2,
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lan9303_disable_processing_port(chip, port);
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lan9303_phy_write(ds, chip->phy_addr_sel_strap + port,
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MII_BMCR, BMCR_PDOWN);
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break;
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default:
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