Blackfin arch: add support for Blackfin latest processor family BF51x
Signed-off-by: Bryan Wu <cooloney@kernel.org>
This commit is contained in:
Bryan Wu
Родитель
2563265bdb
Коммит
2f6f4bcdd6
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@ -77,6 +77,26 @@ choice
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prompt "CPU"
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default BF533
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config BF512
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bool "BF512"
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help
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BF512 Processor Support.
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config BF514
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bool "BF514"
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help
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BF514 Processor Support.
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config BF516
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bool "BF516"
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help
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BF516 Processor Support.
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config BF518
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bool "BF518"
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help
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BF518 Processor Support.
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config BF522
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bool "BF522"
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help
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@ -181,27 +201,27 @@ endchoice
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config BF_REV_MIN
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int
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default 0 if (BF52x || BF54x)
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default 0 if (BF51x || BF52x || BF54x)
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default 2 if (BF537 || BF536 || BF534)
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default 3 if (BF561 ||BF533 || BF532 || BF531)
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default 4 if (BF538 || BF539)
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config BF_REV_MAX
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int
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default 2 if (BF52x || BF54x)
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default 2 if (BF51x || BF52x || BF54x)
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default 3 if (BF537 || BF536 || BF534)
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default 5 if (BF561|| BF538 || BF539)
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default 5 if (BF561 || BF538 || BF539)
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default 6 if (BF533 || BF532 || BF531)
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choice
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prompt "Silicon Rev"
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default BF_REV_0_1 if (BF52x || BF54x)
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default BF_REV_0_1 if (BF51x || BF52x || BF54x)
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default BF_REV_0_2 if (BF534 || BF536 || BF537)
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default BF_REV_0_3 if (BF531 || BF532 || BF533 || BF561)
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config BF_REV_0_0
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bool "0.0"
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depends on (BF52x || BF54x)
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depends on (BF51x || BF52x || BF54x)
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config BF_REV_0_1
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bool "0.1"
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@ -235,6 +255,11 @@ config BF_REV_NONE
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endchoice
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config BF51x
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bool
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depends on (BF512 || BF514 || BF516 || BF518)
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default y
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config BF52x
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bool
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depends on (BF522 || BF523 || BF524 || BF525 || BF526 || BF527)
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@ -282,6 +307,7 @@ config MEM_MT48LC32M16A2TG_75
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depends on (BFIN527_EZKIT || BFIN532_IP0X || BLACKSTAMP || BFIN526_EZBRD)
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default y
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source "arch/blackfin/mach-bf518/Kconfig"
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source "arch/blackfin/mach-bf527/Kconfig"
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source "arch/blackfin/mach-bf533/Kconfig"
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source "arch/blackfin/mach-bf561/Kconfig"
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@ -330,7 +356,7 @@ config CLKIN_HZ
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int "Frequency of the crystal on the board in Hz"
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default "11059200" if BFIN533_STAMP
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default "27000000" if BFIN533_EZKIT
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default "25000000" if (BFIN537_STAMP || BFIN527_EZKIT || H8606_HVSISTEMAS || BLACKSTAMP || BFIN526_EZBRD || BFIN538_EZKIT)
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default "25000000" if (BFIN537_STAMP || BFIN527_EZKIT || H8606_HVSISTEMAS || BLACKSTAMP || BFIN526_EZBRD || BFIN538_EZKIT || BFIN518F-EZBRD)
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default "30000000" if BFIN561_EZKIT
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default "24576000" if PNAV10
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default "10000000" if BFIN532_IP0X
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@ -370,7 +396,7 @@ config VCO_MULT
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default "22" if BFIN533_BLUETECHNIX_CM
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default "20" if (BFIN537_BLUETECHNIX_CM || BFIN527_BLUETECHNIX_CM || BFIN561_BLUETECHNIX_CM)
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default "20" if BFIN561_EZKIT
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default "16" if (H8606_HVSISTEMAS || BLACKSTAMP || BFIN526_EZBRD)
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default "16" if (H8606_HVSISTEMAS || BLACKSTAMP || BFIN526_EZBRD || BFIN518F_EZBRD)
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help
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This controls the frequency of the on-chip PLL. This can be between 1 and 64.
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PLL Frequency = (Crystal Frequency) * (this setting)
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@ -432,6 +458,10 @@ config MAX_MEM_SIZE
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#
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config MAX_VCO_HZ
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int
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default 400000000 if BF512
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default 400000000 if BF514
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default 400000000 if BF516
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default 400000000 if BF518
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default 600000000 if BF522
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default 400000000 if BF523
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default 400000000 if BF524
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@ -1025,7 +1055,7 @@ comment "Possible Suspend Mem / Hibernate Wake-Up Sources"
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config PM_BFIN_WAKE_PH6
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bool "Allow Wake-Up from on-chip PHY or PH6 GP"
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depends on PM && (BF52x || BF534 || BF536 || BF537)
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depends on PM && (BF51x || BF52x || BF534 || BF536 || BF537)
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default n
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help
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Enable PHY and PH6 GP Wake-Up (Voltage Regulator Power-Up)
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@ -21,6 +21,10 @@ KALLSYMS += --symbol-prefix=_
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KBUILD_DEFCONFIG := BF537-STAMP_defconfig
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# setup the machine name and the machine dependent settings
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machine-$(CONFIG_BF512) := bf518
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machine-$(CONFIG_BF514) := bf518
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machine-$(CONFIG_BF516) := bf518
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machine-$(CONFIG_BF518) := bf518
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machine-$(CONFIG_BF522) := bf527
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machine-$(CONFIG_BF523) := bf527
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machine-$(CONFIG_BF524) := bf527
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@ -44,6 +48,10 @@ machine-$(CONFIG_BF561) := bf561
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MACHINE := $(machine-y)
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export MACHINE
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cpu-$(CONFIG_BF512) := bf512
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cpu-$(CONFIG_BF514) := bf514
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cpu-$(CONFIG_BF516) := bf516
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cpu-$(CONFIG_BF518) := bf518
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cpu-$(CONFIG_BF522) := bf522
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cpu-$(CONFIG_BF523) := bf523
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cpu-$(CONFIG_BF524) := bf524
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Разница между файлами не показана из-за своего большого размера
Загрузить разницу
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@ -143,6 +143,57 @@
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#define PERIPHERAL_USAGE 1
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#define GPIO_USAGE 0
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#if defined(BF518_FAMILY)
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#define MAX_BLACKFIN_GPIOS 40
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#define GPIO_PF0 0
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#define GPIO_PF1 1
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#define GPIO_PF2 2
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#define GPIO_PF3 3
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#define GPIO_PF4 4
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#define GPIO_PF5 5
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#define GPIO_PF6 6
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#define GPIO_PF7 7
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#define GPIO_PF8 8
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#define GPIO_PF9 9
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#define GPIO_PF10 10
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#define GPIO_PF11 11
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#define GPIO_PF12 12
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#define GPIO_PF13 13
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#define GPIO_PF14 14
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#define GPIO_PF15 15
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#define GPIO_PG0 16
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#define GPIO_PG1 17
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#define GPIO_PG2 18
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#define GPIO_PG3 19
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#define GPIO_PG4 20
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#define GPIO_PG5 21
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#define GPIO_PG6 22
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#define GPIO_PG7 23
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#define GPIO_PG8 24
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#define GPIO_PG9 25
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#define GPIO_PG10 26
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#define GPIO_PG11 27
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#define GPIO_PG12 28
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#define GPIO_PG13 29
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#define GPIO_PG14 30
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#define GPIO_PG15 31
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#define GPIO_PH0 32
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#define GPIO_PH1 33
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#define GPIO_PH2 34
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#define GPIO_PH3 35
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#define GPIO_PH4 36
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#define GPIO_PH5 37
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#define GPIO_PH6 38
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#define GPIO_PH7 39
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#define PORT_F GPIO_PF0
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#define PORT_G GPIO_PG0
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#define PORT_H GPIO_PH0
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#endif
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#ifdef BF533_FAMILY
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#define MAX_BLACKFIN_GPIOS 16
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@ -125,7 +125,7 @@ static struct gpio_port_t *gpio_bankb[gpio_bank(MAX_BLACKFIN_GPIOS)] = {
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};
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#endif
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#if defined(BF527_FAMILY) || defined(BF537_FAMILY)
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#if defined(BF527_FAMILY) || defined(BF537_FAMILY) || defined(BF518_FAMILY)
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static struct gpio_port_t *gpio_bankb[gpio_bank(MAX_BLACKFIN_GPIOS)] = {
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(struct gpio_port_t *) PORTFIO,
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(struct gpio_port_t *) PORTGIO,
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@ -139,7 +139,7 @@ static unsigned short *port_fer[gpio_bank(MAX_BLACKFIN_GPIOS)] = {
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};
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#endif
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#ifdef BF527_FAMILY
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#if defined(BF527_FAMILY) || defined(BF518_FAMILY)
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static unsigned short *port_mux[gpio_bank(MAX_BLACKFIN_GPIOS)] = {
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(unsigned short *) PORTF_MUX,
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(unsigned short *) PORTG_MUX,
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@ -206,7 +206,7 @@ static unsigned int sic_iwr_irqs[gpio_bank(MAX_BLACKFIN_GPIOS)] = {IRQ_PROG_INTB
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static unsigned int sic_iwr_irqs[gpio_bank(MAX_BLACKFIN_GPIOS)] = {IRQ_PORTF_INTB};
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#endif
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#ifdef BF527_FAMILY
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#if defined(BF527_FAMILY) || defined(BF518_FAMILY)
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static unsigned int sic_iwr_irqs[gpio_bank(MAX_BLACKFIN_GPIOS)] = {IRQ_PORTF_INTB, IRQ_PORTG_INTB, IRQ_PORTH_INTB};
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#endif
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@ -268,7 +268,7 @@ static int cmp_label(unsigned short ident, const char *label)
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return -EINVAL;
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}
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#if defined(BF527_FAMILY) || defined(BF537_FAMILY)
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#if defined(BF527_FAMILY) || defined(BF537_FAMILY) || defined(BF518_FAMILY)
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static void port_setup(unsigned gpio, unsigned short usage)
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{
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if (!check_gpio(gpio)) {
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@ -383,7 +383,7 @@ inline u16 get_portmux(unsigned short portno)
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return (pmux >> (2 * gpio_sub_n(portno)) & 0x3);
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}
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#elif defined(BF527_FAMILY)
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#elif defined(BF527_FAMILY) || defined(BF518_FAMILY)
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inline void portmux_setup(unsigned short portno, unsigned short function)
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{
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u16 pmux, ident = P_IDENT(portno);
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@ -683,7 +683,7 @@ u32 bfin_pm_standby_setup(void)
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gpio_bankb[bank]->maskb = 0;
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if (mask) {
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#if defined(BF527_FAMILY) || defined(BF537_FAMILY)
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#if defined(BF527_FAMILY) || defined(BF537_FAMILY) || defined(BF518_FAMILY)
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gpio_bank_saved[bank].fer = *port_fer[bank];
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#endif
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gpio_bank_saved[bank].inen = gpio_bankb[bank]->inen;
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@ -728,7 +728,7 @@ void bfin_pm_standby_restore(void)
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bank = gpio_bank(i);
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if (mask) {
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#if defined(BF527_FAMILY) || defined(BF537_FAMILY)
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#if defined(BF527_FAMILY) || defined(BF537_FAMILY) || defined(BF518_FAMILY)
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*port_fer[bank] = gpio_bank_saved[bank].fer;
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#endif
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gpio_bankb[bank]->inen = gpio_bank_saved[bank].inen;
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@ -754,9 +754,9 @@ void bfin_gpio_pm_hibernate_suspend(void)
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for (i = 0; i < MAX_BLACKFIN_GPIOS; i += GPIO_BANKSIZE) {
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bank = gpio_bank(i);
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#if defined(BF527_FAMILY) || defined(BF537_FAMILY)
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#if defined(BF527_FAMILY) || defined(BF537_FAMILY) || defined(BF518_FAMILY)
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gpio_bank_saved[bank].fer = *port_fer[bank];
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#ifdef BF527_FAMILY
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#if defined(BF527_FAMILY) || defined(BF518_FAMILY)
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gpio_bank_saved[bank].mux = *port_mux[bank];
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#else
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if (bank == 0)
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@ -782,8 +782,8 @@ void bfin_gpio_pm_hibernate_restore(void)
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for (i = 0; i < MAX_BLACKFIN_GPIOS; i += GPIO_BANKSIZE) {
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bank = gpio_bank(i);
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#if defined(BF527_FAMILY) || defined(BF537_FAMILY)
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#ifdef BF527_FAMILY
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#if defined(BF527_FAMILY) || defined(BF537_FAMILY) || defined(BF518_FAMILY)
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#if defined(BF527_FAMILY) || defined(BF518_FAMILY)
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*port_mux[bank] = gpio_bank_saved[bank].mux;
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#else
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if (bank == 0)
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@ -0,0 +1,233 @@
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if (BF51x)
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source "arch/blackfin/mach-bf518/boards/Kconfig"
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menu "BF518 Specific Configuration"
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comment "Alternative Multiplexing Scheme"
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choice
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prompt "SPORT0"
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default BF518_SPORT0_PORTG
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help
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Select PORT used for SPORT0. See Hardware Reference Manual
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config BF518_SPORT0_PORTF
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bool "PORT F"
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help
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PORT F
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config BF518_SPORT0_PORTG
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bool "PORT G"
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help
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PORT G
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endchoice
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choice
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prompt "SPORT0 TSCLK Location"
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depends on BF518_SPORT0_PORTG
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default BF518_SPORT0_TSCLK_PG10
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help
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Select PIN used for SPORT0_TSCLK. See Hardware Reference Manual
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config BF518_SPORT0_TSCLK_PG10
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bool "PORT PG10"
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help
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PORT PG10
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config BF518_SPORT0_TSCLK_PG14
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bool "PORT PG14"
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help
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PORT PG14
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endchoice
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choice
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prompt "UART1"
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default BF518_UART1_PORTF
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help
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Select PORT used for UART1. See Hardware Reference Manual
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config BF518_UART1_PORTF
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bool "PORT F"
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help
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PORT F
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config BF518_UART1_PORTG
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bool "PORT G"
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help
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PORT G
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endchoice
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comment "Interrupt Priority Assignment"
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menu "Priority"
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config IRQ_PLL_WAKEUP
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int "IRQ_PLL_WAKEUP"
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default 7
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config IRQ_DMA0_ERROR
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int "IRQ_DMA0_ERROR"
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default 7
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config IRQ_DMAR0_BLK
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int "IRQ_DMAR0_BLK"
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default 7
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config IRQ_DMAR1_BLK
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int "IRQ_DMAR1_BLK"
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default 7
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config IRQ_DMAR0_OVR
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int "IRQ_DMAR0_OVR"
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default 7
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config IRQ_DMAR1_OVR
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int "IRQ_DMAR1_OVR"
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default 7
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config IRQ_PPI_ERROR
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int "IRQ_PPI_ERROR"
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default 7
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config IRQ_MAC_ERROR
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int "IRQ_MAC_ERROR"
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default 7
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config IRQ_SPORT0_ERROR
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int "IRQ_SPORT0_ERROR"
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default 7
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config IRQ_SPORT1_ERROR
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int "IRQ_SPORT1_ERROR"
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default 7
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config IRQ_PTP_ERROR
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int "IRQ_PTP_ERROR"
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default 7
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config IRQ_UART0_ERROR
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int "IRQ_UART0_ERROR"
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default 7
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config IRQ_UART1_ERROR
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int "IRQ_UART1_ERROR"
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default 7
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config IRQ_RTC
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int "IRQ_RTC"
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default 8
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config IRQ_PPI
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int "IRQ_PPI"
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default 8
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config IRQ_SPORT0_RX
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int "IRQ_SPORT0_RX"
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default 9
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config IRQ_SPORT0_TX
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int "IRQ_SPORT0_TX"
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default 9
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config IRQ_SPORT1_RX
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int "IRQ_SPORT1_RX"
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default 9
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config IRQ_SPORT1_TX
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int "IRQ_SPORT1_TX"
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default 9
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config IRQ_TWI
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int "IRQ_TWI"
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default 10
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config IRQ_SPI0
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int "IRQ_SPI"
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default 10
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config IRQ_UART0_RX
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int "IRQ_UART0_RX"
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default 10
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config IRQ_UART0_TX
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int "IRQ_UART0_TX"
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default 10
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config IRQ_UART1_RX
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int "IRQ_UART1_RX"
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default 10
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config IRQ_UART1_TX
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int "IRQ_UART1_TX"
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default 10
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config IRQ_OPTSEC
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int "IRQ_OPTSEC"
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default 11
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config IRQ_CNT
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int "IRQ_CNT"
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default 11
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config IRQ_MAC_RX
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int "IRQ_MAC_RX"
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default 11
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config IRQ_PORTH_INTA
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int "IRQ_PORTH_INTA"
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default 11
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config IRQ_MAC_TX
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int "IRQ_MAC_TX/NFC"
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default 11
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config IRQ_PORTH_INTB
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int "IRQ_PORTH_INTB"
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default 11
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config IRQ_TMR0
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int "IRQ_TMR0"
|
||||
default 12
|
||||
config IRQ_TMR1
|
||||
int "IRQ_TMR1"
|
||||
default 12
|
||||
config IRQ_TMR2
|
||||
int "IRQ_TMR2"
|
||||
default 12
|
||||
config IRQ_TMR3
|
||||
int "IRQ_TMR3"
|
||||
default 12
|
||||
config IRQ_TMR4
|
||||
int "IRQ_TMR4"
|
||||
default 12
|
||||
config IRQ_TMR5
|
||||
int "IRQ_TMR5"
|
||||
default 12
|
||||
config IRQ_TMR6
|
||||
int "IRQ_TMR6"
|
||||
default 12
|
||||
config IRQ_TMR7
|
||||
int "IRQ_TMR7"
|
||||
default 12
|
||||
config IRQ_PORTG_INTA
|
||||
int "IRQ_PORTG_INTA"
|
||||
default 12
|
||||
config IRQ_PORTG_INTB
|
||||
int "IRQ_PORTG_INTB"
|
||||
default 12
|
||||
config IRQ_MEM_DMA0
|
||||
int "IRQ_MEM_DMA0"
|
||||
default 13
|
||||
config IRQ_MEM_DMA1
|
||||
int "IRQ_MEM_DMA1"
|
||||
default 13
|
||||
config IRQ_WATCH
|
||||
int "IRQ_WATCH"
|
||||
default 13
|
||||
config IRQ_PORTF_INTA
|
||||
int "IRQ_PORTF_INTA"
|
||||
default 13
|
||||
config IRQ_PORTF_INTB
|
||||
int "IRQ_PORTF_INTB"
|
||||
default 13
|
||||
config IRQ_SPI0_ERROR
|
||||
int "IRQ_SPI0_ERROR"
|
||||
default 7
|
||||
config IRQ_SPI1_ERROR
|
||||
int "IRQ_SPI1_ERROR"
|
||||
default 7
|
||||
config IRQ_RSI_INT0
|
||||
int "IRQ_RSI_INT0"
|
||||
default 7
|
||||
config IRQ_RSI_INT1
|
||||
int "IRQ_RSI_INT1"
|
||||
default 7
|
||||
config IRQ_PWM_TRIP
|
||||
int "IRQ_PWM_TRIP"
|
||||
default 10
|
||||
config IRQ_PWM_SYNC
|
||||
int "IRQ_PWM_SYNC"
|
||||
default 10
|
||||
config IRQ_PTP_STAT
|
||||
int "IRQ_PTP_STAT"
|
||||
default 10
|
||||
|
||||
help
|
||||
Enter the priority numbers between 7-13 ONLY. Others are Reserved.
|
||||
This applies to all the above. It is not recommended to assign the
|
||||
highest priority number 7 to UART or any other device.
|
||||
|
||||
endmenu
|
||||
|
||||
endmenu
|
||||
|
||||
endif
|
||||
|
|
@ -0,0 +1,7 @@
|
|||
#
|
||||
# arch/blackfin/mach-bf518/Makefile
|
||||
#
|
||||
|
||||
extra-y := head.o
|
||||
|
||||
obj-y := ints-priority.o dma.o
|
||||
|
|
@ -0,0 +1,12 @@
|
|||
choice
|
||||
prompt "System type"
|
||||
default BFIN518F_EZBRD
|
||||
help
|
||||
Select your board!
|
||||
|
||||
config BFIN518F_EZBRD
|
||||
bool "BF518F-EZBRD"
|
||||
help
|
||||
BF518-EZBRD board support.
|
||||
|
||||
endchoice
|
||||
|
|
@ -0,0 +1,5 @@
|
|||
#
|
||||
# arch/blackfin/mach-bf518/boards/Makefile
|
||||
#
|
||||
|
||||
obj-$(CONFIG_BFIN518F_EZBRD) += ezbrd.o
|
||||
|
|
@ -0,0 +1,613 @@
|
|||
/*
|
||||
* File: arch/blackfin/mach-bf518/boards/ezbrd.c
|
||||
* Based on: arch/blackfin/mach-bf527/boards/ezbrd.c
|
||||
* Author: Bryan Wu <cooloney@kernel.org>
|
||||
*
|
||||
* Created:
|
||||
* Description:
|
||||
*
|
||||
* Modified:
|
||||
* Copyright 2005 National ICT Australia (NICTA)
|
||||
* Copyright 2004-2008 Analog Devices Inc.
|
||||
*
|
||||
* Bugs: Enter bugs at http://blackfin.uclinux.org/
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, see the file COPYING, or write
|
||||
* to the Free Software Foundation, Inc.,
|
||||
* 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
*/
|
||||
|
||||
#include <linux/device.h>
|
||||
#include <linux/platform_device.h>
|
||||
#include <linux/mtd/mtd.h>
|
||||
#include <linux/mtd/partitions.h>
|
||||
#include <linux/mtd/physmap.h>
|
||||
#include <linux/spi/spi.h>
|
||||
#include <linux/spi/flash.h>
|
||||
|
||||
#include <linux/i2c.h>
|
||||
#include <linux/irq.h>
|
||||
#include <linux/interrupt.h>
|
||||
#include <asm/dma.h>
|
||||
#include <asm/bfin5xx_spi.h>
|
||||
#include <asm/reboot.h>
|
||||
#include <asm/portmux.h>
|
||||
#include <asm/dpmc.h>
|
||||
#include <linux/spi/ad7877.h>
|
||||
|
||||
/*
|
||||
* Name the Board for the /proc/cpuinfo
|
||||
*/
|
||||
const char bfin_board_name[] = "BF518F-EZBRD";
|
||||
|
||||
/*
|
||||
* Driver needs to know address, irq and flag pin.
|
||||
*/
|
||||
|
||||
#if defined(CONFIG_MTD_PHYSMAP) || defined(CONFIG_MTD_PHYSMAP_MODULE)
|
||||
static struct mtd_partition ezbrd_partitions[] = {
|
||||
{
|
||||
.name = "bootloader(nor)",
|
||||
.size = 0x40000,
|
||||
.offset = 0,
|
||||
}, {
|
||||
.name = "linux kernel(nor)",
|
||||
.size = 0x1C0000,
|
||||
.offset = MTDPART_OFS_APPEND,
|
||||
}, {
|
||||
.name = "file system(nor)",
|
||||
.size = MTDPART_SIZ_FULL,
|
||||
.offset = MTDPART_OFS_APPEND,
|
||||
}
|
||||
};
|
||||
|
||||
static struct physmap_flash_data ezbrd_flash_data = {
|
||||
.width = 2,
|
||||
.parts = ezbrd_partitions,
|
||||
.nr_parts = ARRAY_SIZE(ezbrd_partitions),
|
||||
};
|
||||
|
||||
static struct resource ezbrd_flash_resource = {
|
||||
.start = 0x20000000,
|
||||
.end = 0x203fffff,
|
||||
.flags = IORESOURCE_MEM,
|
||||
};
|
||||
|
||||
static struct platform_device ezbrd_flash_device = {
|
||||
.name = "physmap-flash",
|
||||
.id = 0,
|
||||
.dev = {
|
||||
.platform_data = &ezbrd_flash_data,
|
||||
},
|
||||
.num_resources = 1,
|
||||
.resource = &ezbrd_flash_resource,
|
||||
};
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_RTC_DRV_BFIN) || defined(CONFIG_RTC_DRV_BFIN_MODULE)
|
||||
static struct platform_device rtc_device = {
|
||||
.name = "rtc-bfin",
|
||||
.id = -1,
|
||||
};
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE)
|
||||
static struct platform_device bfin_mac_device = {
|
||||
.name = "bfin_mac",
|
||||
};
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_MTD_M25P80) \
|
||||
|| defined(CONFIG_MTD_M25P80_MODULE)
|
||||
static struct mtd_partition bfin_spi_flash_partitions[] = {
|
||||
{
|
||||
.name = "bootloader(spi)",
|
||||
.size = 0x00040000,
|
||||
.offset = 0,
|
||||
.mask_flags = MTD_CAP_ROM
|
||||
}, {
|
||||
.name = "linux kernel(spi)",
|
||||
.size = MTDPART_SIZ_FULL,
|
||||
.offset = MTDPART_OFS_APPEND,
|
||||
}
|
||||
};
|
||||
|
||||
static struct flash_platform_data bfin_spi_flash_data = {
|
||||
.name = "m25p80",
|
||||
.parts = bfin_spi_flash_partitions,
|
||||
.nr_parts = ARRAY_SIZE(bfin_spi_flash_partitions),
|
||||
.type = "m25p16",
|
||||
};
|
||||
|
||||
/* SPI flash chip (m25p64) */
|
||||
static struct bfin5xx_spi_chip spi_flash_chip_info = {
|
||||
.enable_dma = 0, /* use dma transfer with this chip*/
|
||||
.bits_per_word = 8,
|
||||
};
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_SPI_ADC_BF533) \
|
||||
|| defined(CONFIG_SPI_ADC_BF533_MODULE)
|
||||
/* SPI ADC chip */
|
||||
static struct bfin5xx_spi_chip spi_adc_chip_info = {
|
||||
.enable_dma = 1, /* use dma transfer with this chip*/
|
||||
.bits_per_word = 16,
|
||||
};
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_SPI_MMC) || defined(CONFIG_SPI_MMC_MODULE)
|
||||
static struct bfin5xx_spi_chip spi_mmc_chip_info = {
|
||||
.enable_dma = 1,
|
||||
.bits_per_word = 8,
|
||||
};
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_PBX)
|
||||
static struct bfin5xx_spi_chip spi_si3xxx_chip_info = {
|
||||
.ctl_reg = 0x4, /* send zero */
|
||||
.enable_dma = 0,
|
||||
.bits_per_word = 8,
|
||||
.cs_change_per_word = 1,
|
||||
};
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_TOUCHSCREEN_AD7877) || defined(CONFIG_TOUCHSCREEN_AD7877_MODULE)
|
||||
static struct bfin5xx_spi_chip spi_ad7877_chip_info = {
|
||||
.enable_dma = 0,
|
||||
.bits_per_word = 16,
|
||||
};
|
||||
|
||||
static const struct ad7877_platform_data bfin_ad7877_ts_info = {
|
||||
.model = 7877,
|
||||
.vref_delay_usecs = 50, /* internal, no capacitor */
|
||||
.x_plate_ohms = 419,
|
||||
.y_plate_ohms = 486,
|
||||
.pressure_max = 1000,
|
||||
.pressure_min = 0,
|
||||
.stopacq_polarity = 1,
|
||||
.first_conversion_delay = 3,
|
||||
.acquisition_time = 1,
|
||||
.averaging = 1,
|
||||
.pen_down_acc_interval = 1,
|
||||
};
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_SND_SOC_WM8731) || defined(CONFIG_SND_SOC_WM8731_MODULE) \
|
||||
&& defined(CONFIG_SND_SOC_WM8731_SPI)
|
||||
static struct bfin5xx_spi_chip spi_wm8731_chip_info = {
|
||||
.enable_dma = 0,
|
||||
.bits_per_word = 16,
|
||||
};
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_SPI_SPIDEV) || defined(CONFIG_SPI_SPIDEV_MODULE)
|
||||
static struct bfin5xx_spi_chip spidev_chip_info = {
|
||||
.enable_dma = 0,
|
||||
.bits_per_word = 8,
|
||||
};
|
||||
#endif
|
||||
|
||||
static struct spi_board_info bfin_spi_board_info[] __initdata = {
|
||||
#if defined(CONFIG_MTD_M25P80) \
|
||||
|| defined(CONFIG_MTD_M25P80_MODULE)
|
||||
{
|
||||
/* the modalias must be the same as spi device driver name */
|
||||
.modalias = "m25p80", /* Name of spi_driver for this device */
|
||||
.max_speed_hz = 25000000, /* max spi clock (SCK) speed in HZ */
|
||||
.bus_num = 0, /* Framework bus number */
|
||||
.chip_select = 1, /* Framework chip select. On STAMP537 it is SPISSEL1*/
|
||||
.platform_data = &bfin_spi_flash_data,
|
||||
.controller_data = &spi_flash_chip_info,
|
||||
.mode = SPI_MODE_3,
|
||||
},
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_SPI_ADC_BF533) \
|
||||
|| defined(CONFIG_SPI_ADC_BF533_MODULE)
|
||||
{
|
||||
.modalias = "bfin_spi_adc", /* Name of spi_driver for this device */
|
||||
.max_speed_hz = 6250000, /* max spi clock (SCK) speed in HZ */
|
||||
.bus_num = 0, /* Framework bus number */
|
||||
.chip_select = 1, /* Framework chip select. */
|
||||
.platform_data = NULL, /* No spi_driver specific config */
|
||||
.controller_data = &spi_adc_chip_info,
|
||||
},
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_SPI_MMC) || defined(CONFIG_SPI_MMC_MODULE)
|
||||
{
|
||||
.modalias = "spi_mmc_dummy",
|
||||
.max_speed_hz = 25000000, /* max spi clock (SCK) speed in HZ */
|
||||
.bus_num = 0,
|
||||
.chip_select = 0,
|
||||
.platform_data = NULL,
|
||||
.controller_data = &spi_mmc_chip_info,
|
||||
.mode = SPI_MODE_3,
|
||||
},
|
||||
{
|
||||
.modalias = "spi_mmc",
|
||||
.max_speed_hz = 25000000, /* max spi clock (SCK) speed in HZ */
|
||||
.bus_num = 0,
|
||||
.chip_select = CONFIG_SPI_MMC_CS_CHAN,
|
||||
.platform_data = NULL,
|
||||
.controller_data = &spi_mmc_chip_info,
|
||||
.mode = SPI_MODE_3,
|
||||
},
|
||||
#endif
|
||||
#if defined(CONFIG_PBX)
|
||||
{
|
||||
.modalias = "fxs-spi",
|
||||
.max_speed_hz = 12500000, /* max spi clock (SCK) speed in HZ */
|
||||
.bus_num = 0,
|
||||
.chip_select = 8 - CONFIG_J11_JUMPER,
|
||||
.controller_data = &spi_si3xxx_chip_info,
|
||||
.mode = SPI_MODE_3,
|
||||
},
|
||||
{
|
||||
.modalias = "fxo-spi",
|
||||
.max_speed_hz = 12500000, /* max spi clock (SCK) speed in HZ */
|
||||
.bus_num = 0,
|
||||
.chip_select = 8 - CONFIG_J19_JUMPER,
|
||||
.controller_data = &spi_si3xxx_chip_info,
|
||||
.mode = SPI_MODE_3,
|
||||
},
|
||||
#endif
|
||||
#if defined(CONFIG_TOUCHSCREEN_AD7877) || defined(CONFIG_TOUCHSCREEN_AD7877_MODULE)
|
||||
{
|
||||
.modalias = "ad7877",
|
||||
.platform_data = &bfin_ad7877_ts_info,
|
||||
.irq = IRQ_PF8,
|
||||
.max_speed_hz = 12500000, /* max spi clock (SCK) speed in HZ */
|
||||
.bus_num = 0,
|
||||
.chip_select = 2,
|
||||
.controller_data = &spi_ad7877_chip_info,
|
||||
},
|
||||
#endif
|
||||
#if defined(CONFIG_SND_SOC_WM8731) || defined(CONFIG_SND_SOC_WM8731_MODULE) \
|
||||
&& defined(CONFIG_SND_SOC_WM8731_SPI)
|
||||
{
|
||||
.modalias = "wm8731",
|
||||
.max_speed_hz = 3125000, /* max spi clock (SCK) speed in HZ */
|
||||
.bus_num = 0,
|
||||
.chip_select = 5,
|
||||
.controller_data = &spi_wm8731_chip_info,
|
||||
.mode = SPI_MODE_0,
|
||||
},
|
||||
#endif
|
||||
#if defined(CONFIG_SPI_SPIDEV) || defined(CONFIG_SPI_SPIDEV_MODULE)
|
||||
{
|
||||
.modalias = "spidev",
|
||||
.max_speed_hz = 3125000, /* max spi clock (SCK) speed in HZ */
|
||||
.bus_num = 0,
|
||||
.chip_select = 1,
|
||||
.controller_data = &spidev_chip_info,
|
||||
},
|
||||
#endif
|
||||
#if defined(CONFIG_FB_BFIN_LQ035Q1) || defined(CONFIG_FB_BFIN_LQ035Q1_MODULE)
|
||||
{
|
||||
.modalias = "bfin-lq035q1-spi",
|
||||
.max_speed_hz = 20000000, /* max spi clock (SCK) speed in HZ */
|
||||
.bus_num = 0,
|
||||
.chip_select = 1,
|
||||
.controller_data = &lq035q1_spi_chip_info,
|
||||
.mode = SPI_CPHA | SPI_CPOL,
|
||||
},
|
||||
#endif
|
||||
};
|
||||
|
||||
/* SPI controller data */
|
||||
#if defined(CONFIG_SPI_BFIN) || defined(CONFIG_SPI_BFIN_MODULE)
|
||||
/* SPI (0) */
|
||||
static struct bfin5xx_spi_master bfin_spi0_info = {
|
||||
.num_chipselect = 5,
|
||||
.enable_dma = 1, /* master has the ability to do dma transfer */
|
||||
.pin_req = {P_SPI0_SCK, P_SPI0_MISO, P_SPI0_MOSI, 0},
|
||||
};
|
||||
|
||||
static struct resource bfin_spi0_resource[] = {
|
||||
[0] = {
|
||||
.start = SPI0_REGBASE,
|
||||
.end = SPI0_REGBASE + 0xFF,
|
||||
.flags = IORESOURCE_MEM,
|
||||
},
|
||||
[1] = {
|
||||
.start = CH_SPI0,
|
||||
.end = CH_SPI0,
|
||||
.flags = IORESOURCE_IRQ,
|
||||
},
|
||||
};
|
||||
|
||||
static struct platform_device bfin_spi0_device = {
|
||||
.name = "bfin-spi",
|
||||
.id = 0, /* Bus number */
|
||||
.num_resources = ARRAY_SIZE(bfin_spi0_resource),
|
||||
.resource = bfin_spi0_resource,
|
||||
.dev = {
|
||||
.platform_data = &bfin_spi0_info, /* Passed to driver */
|
||||
},
|
||||
};
|
||||
|
||||
/* SPI (1) */
|
||||
static struct bfin5xx_spi_master bfin_spi1_info = {
|
||||
.num_chipselect = 5,
|
||||
.enable_dma = 1, /* master has the ability to do dma transfer */
|
||||
.pin_req = {P_SPI1_SCK, P_SPI1_MISO, P_SPI1_MOSI, 0},
|
||||
};
|
||||
|
||||
static struct resource bfin_spi1_resource[] = {
|
||||
[0] = {
|
||||
.start = SPI1_REGBASE,
|
||||
.end = SPI1_REGBASE + 0xFF,
|
||||
.flags = IORESOURCE_MEM,
|
||||
},
|
||||
[1] = {
|
||||
.start = CH_SPI1,
|
||||
.end = CH_SPI1,
|
||||
.flags = IORESOURCE_IRQ,
|
||||
},
|
||||
};
|
||||
|
||||
static struct platform_device bfin_spi1_device = {
|
||||
.name = "bfin-spi",
|
||||
.id = 1, /* Bus number */
|
||||
.num_resources = ARRAY_SIZE(bfin_spi1_resource),
|
||||
.resource = bfin_spi1_resource,
|
||||
.dev = {
|
||||
.platform_data = &bfin_spi1_info, /* Passed to driver */
|
||||
},
|
||||
};
|
||||
#endif /* spi master and devices */
|
||||
|
||||
#if defined(CONFIG_SERIAL_BFIN) || defined(CONFIG_SERIAL_BFIN_MODULE)
|
||||
static struct resource bfin_uart_resources[] = {
|
||||
#ifdef CONFIG_SERIAL_BFIN_UART0
|
||||
{
|
||||
.start = 0xFFC00400,
|
||||
.end = 0xFFC004FF,
|
||||
.flags = IORESOURCE_MEM,
|
||||
},
|
||||
#endif
|
||||
#ifdef CONFIG_SERIAL_BFIN_UART1
|
||||
{
|
||||
.start = 0xFFC02000,
|
||||
.end = 0xFFC020FF,
|
||||
.flags = IORESOURCE_MEM,
|
||||
},
|
||||
#endif
|
||||
};
|
||||
|
||||
static struct platform_device bfin_uart_device = {
|
||||
.name = "bfin-uart",
|
||||
.id = 1,
|
||||
.num_resources = ARRAY_SIZE(bfin_uart_resources),
|
||||
.resource = bfin_uart_resources,
|
||||
};
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_BFIN_SIR) || defined(CONFIG_BFIN_SIR_MODULE)
|
||||
static struct resource bfin_sir_resources[] = {
|
||||
#ifdef CONFIG_BFIN_SIR0
|
||||
{
|
||||
.start = 0xFFC00400,
|
||||
.end = 0xFFC004FF,
|
||||
.flags = IORESOURCE_MEM,
|
||||
},
|
||||
#endif
|
||||
#ifdef CONFIG_BFIN_SIR1
|
||||
{
|
||||
.start = 0xFFC02000,
|
||||
.end = 0xFFC020FF,
|
||||
.flags = IORESOURCE_MEM,
|
||||
},
|
||||
#endif
|
||||
};
|
||||
|
||||
static struct platform_device bfin_sir_device = {
|
||||
.name = "bfin_sir",
|
||||
.id = 0,
|
||||
.num_resources = ARRAY_SIZE(bfin_sir_resources),
|
||||
.resource = bfin_sir_resources,
|
||||
};
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_I2C_BLACKFIN_TWI) || defined(CONFIG_I2C_BLACKFIN_TWI_MODULE)
|
||||
static struct resource bfin_twi0_resource[] = {
|
||||
[0] = {
|
||||
.start = TWI0_REGBASE,
|
||||
.end = TWI0_REGBASE,
|
||||
.flags = IORESOURCE_MEM,
|
||||
},
|
||||
[1] = {
|
||||
.start = IRQ_TWI,
|
||||
.end = IRQ_TWI,
|
||||
.flags = IORESOURCE_IRQ,
|
||||
},
|
||||
};
|
||||
|
||||
static struct platform_device i2c_bfin_twi_device = {
|
||||
.name = "i2c-bfin-twi",
|
||||
.id = 0,
|
||||
.num_resources = ARRAY_SIZE(bfin_twi0_resource),
|
||||
.resource = bfin_twi0_resource,
|
||||
};
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_I2C_BOARDINFO
|
||||
static struct i2c_board_info __initdata bfin_i2c_board_info[] = {
|
||||
#if defined(CONFIG_TWI_LCD) || defined(CONFIG_TWI_LCD_MODULE)
|
||||
{
|
||||
I2C_BOARD_INFO("pcf8574_lcd", 0x22),
|
||||
},
|
||||
#endif
|
||||
#if defined(CONFIG_TWI_KEYPAD) || defined(CONFIG_TWI_KEYPAD_MODULE)
|
||||
{
|
||||
I2C_BOARD_INFO("pcf8574_keypad", 0x27),
|
||||
.irq = IRQ_PF8,
|
||||
},
|
||||
#endif
|
||||
};
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_SERIAL_BFIN_SPORT) || defined(CONFIG_SERIAL_BFIN_SPORT_MODULE)
|
||||
static struct platform_device bfin_sport0_uart_device = {
|
||||
.name = "bfin-sport-uart",
|
||||
.id = 0,
|
||||
};
|
||||
|
||||
static struct platform_device bfin_sport1_uart_device = {
|
||||
.name = "bfin-sport-uart",
|
||||
.id = 1,
|
||||
};
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_KEYBOARD_GPIO) || defined(CONFIG_KEYBOARD_GPIO_MODULE)
|
||||
#include <linux/input.h>
|
||||
#include <linux/gpio_keys.h>
|
||||
|
||||
static struct gpio_keys_button bfin_gpio_keys_table[] = {
|
||||
{BTN_0, GPIO_PG0, 1, "gpio-keys: BTN0"},
|
||||
{BTN_1, GPIO_PG13, 1, "gpio-keys: BTN1"},
|
||||
};
|
||||
|
||||
static struct gpio_keys_platform_data bfin_gpio_keys_data = {
|
||||
.buttons = bfin_gpio_keys_table,
|
||||
.nbuttons = ARRAY_SIZE(bfin_gpio_keys_table),
|
||||
};
|
||||
|
||||
static struct platform_device bfin_device_gpiokeys = {
|
||||
.name = "gpio-keys",
|
||||
.dev = {
|
||||
.platform_data = &bfin_gpio_keys_data,
|
||||
},
|
||||
};
|
||||
#endif
|
||||
|
||||
static struct resource bfin_gpios_resources = {
|
||||
.start = 0,
|
||||
.end = MAX_BLACKFIN_GPIOS - 1,
|
||||
.flags = IORESOURCE_IRQ,
|
||||
};
|
||||
|
||||
static struct platform_device bfin_gpios_device = {
|
||||
.name = "simple-gpio",
|
||||
.id = -1,
|
||||
.num_resources = 1,
|
||||
.resource = &bfin_gpios_resources,
|
||||
};
|
||||
|
||||
static const unsigned int cclk_vlev_datasheet[] =
|
||||
{
|
||||
VRPAIR(VLEV_100, 400000000),
|
||||
VRPAIR(VLEV_105, 426000000),
|
||||
VRPAIR(VLEV_110, 500000000),
|
||||
VRPAIR(VLEV_115, 533000000),
|
||||
VRPAIR(VLEV_120, 600000000),
|
||||
};
|
||||
|
||||
static struct bfin_dpmc_platform_data bfin_dmpc_vreg_data = {
|
||||
.tuple_tab = cclk_vlev_datasheet,
|
||||
.tabsize = ARRAY_SIZE(cclk_vlev_datasheet),
|
||||
.vr_settling_time = 25 /* us */,
|
||||
};
|
||||
|
||||
static struct platform_device bfin_dpmc = {
|
||||
.name = "bfin dpmc",
|
||||
.dev = {
|
||||
.platform_data = &bfin_dmpc_vreg_data,
|
||||
},
|
||||
};
|
||||
|
||||
static struct platform_device *stamp_devices[] __initdata = {
|
||||
|
||||
&bfin_dpmc,
|
||||
|
||||
#if defined(CONFIG_RTC_DRV_BFIN) || defined(CONFIG_RTC_DRV_BFIN_MODULE)
|
||||
&rtc_device,
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE)
|
||||
&bfin_mac_device,
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_SPI_BFIN) || defined(CONFIG_SPI_BFIN_MODULE)
|
||||
&bfin_spi0_device,
|
||||
&bfin_spi1_device,
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_SERIAL_BFIN) || defined(CONFIG_SERIAL_BFIN_MODULE)
|
||||
&bfin_uart_device,
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_BFIN_SIR) || defined(CONFIG_BFIN_SIR_MODULE)
|
||||
&bfin_sir_device,
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_I2C_BLACKFIN_TWI) || defined(CONFIG_I2C_BLACKFIN_TWI_MODULE)
|
||||
&i2c_bfin_twi_device,
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_SERIAL_BFIN_SPORT) || defined(CONFIG_SERIAL_BFIN_SPORT_MODULE)
|
||||
&bfin_sport0_uart_device,
|
||||
&bfin_sport1_uart_device,
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_KEYBOARD_GPIO) || defined(CONFIG_KEYBOARD_GPIO_MODULE)
|
||||
&bfin_device_gpiokeys,
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_MTD_PHYSMAP) || defined(CONFIG_MTD_PHYSMAP_MODULE)
|
||||
&ezbrd_flash_device,
|
||||
#endif
|
||||
|
||||
&bfin_gpios_device,
|
||||
};
|
||||
|
||||
static int __init ezbrd_init(void)
|
||||
{
|
||||
printk(KERN_INFO "%s(): registering device resources\n", __func__);
|
||||
|
||||
#ifdef CONFIG_I2C_BOARDINFO
|
||||
i2c_register_board_info(0, bfin_i2c_board_info,
|
||||
ARRAY_SIZE(bfin_i2c_board_info));
|
||||
#endif
|
||||
|
||||
platform_add_devices(stamp_devices, ARRAY_SIZE(stamp_devices));
|
||||
spi_register_board_info(bfin_spi_board_info, ARRAY_SIZE(bfin_spi_board_info));
|
||||
return 0;
|
||||
}
|
||||
|
||||
arch_initcall(ezbrd_init);
|
||||
|
||||
void native_machine_restart(char *cmd)
|
||||
{
|
||||
/* workaround reboot hang when booting from SPI */
|
||||
if ((bfin_read_SYSCR() & 0x7) == 0x3)
|
||||
bfin_gpio_reset_spi0_ssel1();
|
||||
}
|
||||
|
||||
void bfin_get_ether_addr(char *addr)
|
||||
{
|
||||
/* the MAC is stored in OTP memory page 0xDF */
|
||||
u32 ret;
|
||||
u64 otp_mac;
|
||||
u32 (*otp_read)(u32 page, u32 flags, u64 *page_content) = (void *)0xEF00001A;
|
||||
|
||||
ret = otp_read(0xDF, 0x00, &otp_mac);
|
||||
if (!(ret & 0x1)) {
|
||||
char *otp_mac_p = (char *)&otp_mac;
|
||||
for (ret = 0; ret < 6; ++ret)
|
||||
addr[ret] = otp_mac_p[5 - ret];
|
||||
}
|
||||
}
|
||||
EXPORT_SYMBOL(bfin_get_ether_addr);
|
||||
|
|
@ -0,0 +1,118 @@
|
|||
/*
|
||||
* File: arch/blackfin/mach-bf518/dma.c
|
||||
* Based on:
|
||||
* Author: Bryan Wu <cooloney@kernel.org>
|
||||
*
|
||||
* Created:
|
||||
* Description: This file contains the simple DMA Implementation for Blackfin
|
||||
*
|
||||
* Modified:
|
||||
* Copyright 2004-2008 Analog Devices Inc.
|
||||
*
|
||||
* Bugs: Enter bugs at http://blackfin.uclinux.org/
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, see the file COPYING, or write
|
||||
* to the Free Software Foundation, Inc.,
|
||||
* 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
*/
|
||||
#include <linux/module.h>
|
||||
|
||||
#include <asm/blackfin.h>
|
||||
#include <asm/dma.h>
|
||||
|
||||
struct dma_register *dma_io_base_addr[MAX_BLACKFIN_DMA_CHANNEL] = {
|
||||
(struct dma_register *) DMA0_NEXT_DESC_PTR,
|
||||
(struct dma_register *) DMA1_NEXT_DESC_PTR,
|
||||
(struct dma_register *) DMA2_NEXT_DESC_PTR,
|
||||
(struct dma_register *) DMA3_NEXT_DESC_PTR,
|
||||
(struct dma_register *) DMA4_NEXT_DESC_PTR,
|
||||
(struct dma_register *) DMA5_NEXT_DESC_PTR,
|
||||
(struct dma_register *) DMA6_NEXT_DESC_PTR,
|
||||
(struct dma_register *) DMA7_NEXT_DESC_PTR,
|
||||
(struct dma_register *) DMA8_NEXT_DESC_PTR,
|
||||
(struct dma_register *) DMA9_NEXT_DESC_PTR,
|
||||
(struct dma_register *) DMA10_NEXT_DESC_PTR,
|
||||
(struct dma_register *) DMA11_NEXT_DESC_PTR,
|
||||
(struct dma_register *) MDMA_S0_NEXT_DESC_PTR,
|
||||
(struct dma_register *) MDMA_D0_NEXT_DESC_PTR,
|
||||
(struct dma_register *) MDMA_S1_NEXT_DESC_PTR,
|
||||
(struct dma_register *) MDMA_D1_NEXT_DESC_PTR,
|
||||
};
|
||||
EXPORT_SYMBOL(dma_io_base_addr);
|
||||
|
||||
int channel2irq(unsigned int channel)
|
||||
{
|
||||
int ret_irq = -1;
|
||||
|
||||
switch (channel) {
|
||||
case CH_PPI:
|
||||
ret_irq = IRQ_PPI;
|
||||
break;
|
||||
|
||||
case CH_EMAC_RX:
|
||||
ret_irq = IRQ_MAC_RX;
|
||||
break;
|
||||
|
||||
case CH_EMAC_TX:
|
||||
ret_irq = IRQ_MAC_TX;
|
||||
break;
|
||||
|
||||
case CH_UART1_RX:
|
||||
ret_irq = IRQ_UART1_RX;
|
||||
break;
|
||||
|
||||
case CH_UART1_TX:
|
||||
ret_irq = IRQ_UART1_TX;
|
||||
break;
|
||||
|
||||
case CH_SPORT0_RX:
|
||||
ret_irq = IRQ_SPORT0_RX;
|
||||
break;
|
||||
|
||||
case CH_SPORT0_TX:
|
||||
ret_irq = IRQ_SPORT0_TX;
|
||||
break;
|
||||
|
||||
case CH_SPORT1_RX:
|
||||
ret_irq = IRQ_SPORT1_RX;
|
||||
break;
|
||||
|
||||
case CH_SPORT1_TX:
|
||||
ret_irq = IRQ_SPORT1_TX;
|
||||
break;
|
||||
|
||||
case CH_SPI0:
|
||||
ret_irq = IRQ_SPI0;
|
||||
break;
|
||||
|
||||
case CH_UART0_RX:
|
||||
ret_irq = IRQ_UART0_RX;
|
||||
break;
|
||||
|
||||
case CH_UART0_TX:
|
||||
ret_irq = IRQ_UART0_TX;
|
||||
break;
|
||||
|
||||
case CH_MEM_STREAM0_SRC:
|
||||
case CH_MEM_STREAM0_DEST:
|
||||
ret_irq = IRQ_MEM_DMA0;
|
||||
break;
|
||||
|
||||
case CH_MEM_STREAM1_SRC:
|
||||
case CH_MEM_STREAM1_DEST:
|
||||
ret_irq = IRQ_MEM_DMA1;
|
||||
break;
|
||||
}
|
||||
return ret_irq;
|
||||
}
|
||||
|
|
@ -0,0 +1,146 @@
|
|||
/*
|
||||
* File: arch/blackfin/mach-bf518/head.S
|
||||
* Based on: arch/blackfin/mach-bf527/head.S
|
||||
* Author: Bryan Wu <cooloney@kernel.org>
|
||||
*
|
||||
* Created: 2008
|
||||
* Description: Startup code for Blackfin BF51x
|
||||
*
|
||||
* Modified:
|
||||
* Copyright 2004-2008 Analog Devices Inc.
|
||||
*
|
||||
* Bugs: Enter bugs at http://blackfin.uclinux.org/
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, see the file COPYING, or write
|
||||
* to the Free Software Foundation, Inc.,
|
||||
* 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
*/
|
||||
|
||||
#include <linux/linkage.h>
|
||||
#include <linux/init.h>
|
||||
#include <asm/blackfin.h>
|
||||
#ifdef CONFIG_BFIN_KERNEL_CLOCK
|
||||
#include <asm/mach-common/clocks.h>
|
||||
#include <asm/mach/mem_init.h>
|
||||
#endif
|
||||
|
||||
.section .l1.text
|
||||
#ifdef CONFIG_BFIN_KERNEL_CLOCK
|
||||
ENTRY(_start_dma_code)
|
||||
|
||||
/* Enable PHY CLK buffer output */
|
||||
p0.h = hi(VR_CTL);
|
||||
p0.l = lo(VR_CTL);
|
||||
r0.l = w[p0];
|
||||
bitset(r0, 14);
|
||||
w[p0] = r0.l;
|
||||
ssync;
|
||||
|
||||
p0.h = hi(SIC_IWR0);
|
||||
p0.l = lo(SIC_IWR0);
|
||||
r0.l = 0x1;
|
||||
r0.h = 0x0;
|
||||
[p0] = r0;
|
||||
ssync;
|
||||
|
||||
/*
|
||||
* Set PLL_CTL
|
||||
* - [14:09] = MSEL[5:0] : CLKIN / VCO multiplication factors
|
||||
* - [8] = BYPASS : BYPASS the PLL, run CLKIN into CCLK/SCLK
|
||||
* - [7] = output delay (add 200ps of delay to mem signals)
|
||||
* - [6] = input delay (add 200ps of input delay to mem signals)
|
||||
* - [5] = PDWN : 1=All Clocks off
|
||||
* - [3] = STOPCK : 1=Core Clock off
|
||||
* - [1] = PLL_OFF : 1=Disable Power to PLL
|
||||
* - [0] = DF : 1=Pass CLKIN/2 to PLL / 0=Pass CLKIN to PLL
|
||||
* all other bits set to zero
|
||||
*/
|
||||
|
||||
p0.h = hi(PLL_LOCKCNT);
|
||||
p0.l = lo(PLL_LOCKCNT);
|
||||
r0 = 0x300(Z);
|
||||
w[p0] = r0.l;
|
||||
ssync;
|
||||
|
||||
P2.H = hi(EBIU_SDGCTL);
|
||||
P2.L = lo(EBIU_SDGCTL);
|
||||
R0 = [P2];
|
||||
BITSET (R0, 24);
|
||||
[P2] = R0;
|
||||
ssync;
|
||||
|
||||
r0 = CONFIG_VCO_MULT & 63; /* Load the VCO multiplier */
|
||||
r0 = r0 << 9; /* Shift it over, */
|
||||
r1 = CLKIN_HALF; /* Do we need to divide CLKIN by 2?*/
|
||||
r0 = r1 | r0;
|
||||
r1 = PLL_BYPASS; /* Bypass the PLL? */
|
||||
r1 = r1 << 8; /* Shift it over */
|
||||
r0 = r1 | r0; /* add them all together */
|
||||
#ifdef ANOMALY_05000265
|
||||
BITSET(r0, 15); /* Add 250 mV of hysteresis to SPORT input pins */
|
||||
#endif
|
||||
|
||||
p0.h = hi(PLL_CTL);
|
||||
p0.l = lo(PLL_CTL); /* Load the address */
|
||||
cli r2; /* Disable interrupts */
|
||||
ssync;
|
||||
w[p0] = r0.l; /* Set the value */
|
||||
idle; /* Wait for the PLL to stablize */
|
||||
sti r2; /* Enable interrupts */
|
||||
|
||||
.Lcheck_again:
|
||||
p0.h = hi(PLL_STAT);
|
||||
p0.l = lo(PLL_STAT);
|
||||
R0 = W[P0](Z);
|
||||
CC = BITTST(R0,5);
|
||||
if ! CC jump .Lcheck_again;
|
||||
|
||||
/* Configure SCLK & CCLK Dividers */
|
||||
r0 = (CONFIG_CCLK_ACT_DIV | CONFIG_SCLK_DIV);
|
||||
p0.h = hi(PLL_DIV);
|
||||
p0.l = lo(PLL_DIV);
|
||||
w[p0] = r0.l;
|
||||
ssync;
|
||||
|
||||
p0.l = lo(EBIU_SDRRC);
|
||||
p0.h = hi(EBIU_SDRRC);
|
||||
r0 = mem_SDRRC;
|
||||
w[p0] = r0.l;
|
||||
ssync;
|
||||
|
||||
P2.H = hi(EBIU_SDGCTL);
|
||||
P2.L = lo(EBIU_SDGCTL);
|
||||
R0 = [P2];
|
||||
BITCLR (R0, 24);
|
||||
p0.h = hi(EBIU_SDSTAT);
|
||||
p0.l = lo(EBIU_SDSTAT);
|
||||
r2.l = w[p0];
|
||||
cc = bittst(r2,3);
|
||||
if !cc jump .Lskip;
|
||||
NOP;
|
||||
BITSET (R0, 23);
|
||||
.Lskip:
|
||||
[P2] = R0;
|
||||
SSYNC;
|
||||
|
||||
R0.L = lo(mem_SDGCTL);
|
||||
R0.H = hi(mem_SDGCTL);
|
||||
R1 = [p2];
|
||||
R1 = R1 | R0;
|
||||
[P2] = R1;
|
||||
SSYNC;
|
||||
|
||||
RTS;
|
||||
ENDPROC(_start_dma_code)
|
||||
#endif /* CONFIG_BFIN_KERNEL_CLOCK */
|
||||
|
|
@ -0,0 +1,77 @@
|
|||
/*
|
||||
* File: include/asm-blackfin/mach-bf518/anomaly.h
|
||||
* Bugs: Enter bugs at http://blackfin.uclinux.org/
|
||||
*
|
||||
* Copyright (C) 2004-2008 Analog Devices Inc.
|
||||
* Licensed under the GPL-2 or later.
|
||||
*/
|
||||
|
||||
/* This file shoule be up to date with:
|
||||
* - ????
|
||||
*/
|
||||
|
||||
#ifndef _MACH_ANOMALY_H_
|
||||
#define _MACH_ANOMALY_H_
|
||||
|
||||
/* Multi-Issue Instruction with dsp32shiftimm in slot1 and P-reg Store in slot2 Not Supported */
|
||||
#define ANOMALY_05000074 (1)
|
||||
/* Rx.H Cannot Be Used to Access 16-bit System MMR Registers */
|
||||
#define ANOMALY_05000122 (1)
|
||||
/* False Hardware Error from an Access in the Shadow of a Conditional Branch */
|
||||
#define ANOMALY_05000245 (1)
|
||||
/* Sensitivity To Noise with Slow Input Edge Rates on External SPORT TX and RX Clocks */
|
||||
#define ANOMALY_05000265 (1)
|
||||
/* False Hardware Errors Caused by Fetches at the Boundary of Reserved Memory */
|
||||
#define ANOMALY_05000310 (1)
|
||||
/* PPI Underflow Error Goes Undetected in ITU-R 656 Mode */
|
||||
#define ANOMALY_05000366 (1)
|
||||
/* Lockbox SESR Firmware Does Not Save/Restore Full Context */
|
||||
#define ANOMALY_05000405 (1)
|
||||
/* Lockbox Firmware Memory Cleanup Routine Does not Clear Registers */
|
||||
#define ANOMALY_05000408 (1)
|
||||
/* Speculative Fetches Can Cause Undesired External FIFO Operations */
|
||||
#define ANOMALY_05000416 (1)
|
||||
/* TWI Fall Time (Tof) May Violate the Minimum I2C Specification */
|
||||
#define ANOMALY_05000421 (1)
|
||||
/* TWI Input Capacitance (Ci) May Violate the Maximum I2C Specification */
|
||||
#define ANOMALY_05000422 (1)
|
||||
/* Speculative Fetches of Indirect-Pointer Instructions Can Cause False Hardware Errors */
|
||||
#define ANOMALY_05000426 (1)
|
||||
/* Software System Reset Corrupts PLL_LOCKCNT Register */
|
||||
#define ANOMALY_05000430 (1)
|
||||
/* Incorrect Use of Stack in Lockbox Firmware During Authentication */
|
||||
#define ANOMALY_05000431 (1)
|
||||
/* Certain SIC Registers are not Reset After Soft or Core Double Fault Reset */
|
||||
#define ANOMALY_05000435 (1)
|
||||
/* PORTx_DRIVE and PORTx_HYSTERESIS Registers Read Back Incorrect Values */
|
||||
#define ANOMALY_05000438 (1)
|
||||
/* Preboot Cannot be Used to Program the PLL_DIV Register */
|
||||
#define ANOMALY_05000439 (1)
|
||||
/* bfrom_SysControl() Cannot be Used to Write the PLL_DIV Register */
|
||||
#define ANOMALY_05000440 (1)
|
||||
/* IFLUSH Instruction at End of Hardware Loop Causes Infinite Stall */
|
||||
#define ANOMALY_05000443 (1)
|
||||
/* Incorrect L1 Instruction Bank B Memory Map Location */
|
||||
#define ANOMALY_05000444 (1)
|
||||
|
||||
/* Anomalies that don't exist on this proc */
|
||||
#define ANOMALY_05000125 (0)
|
||||
#define ANOMALY_05000158 (0)
|
||||
#define ANOMALY_05000183 (0)
|
||||
#define ANOMALY_05000198 (0)
|
||||
#define ANOMALY_05000230 (0)
|
||||
#define ANOMALY_05000244 (0)
|
||||
#define ANOMALY_05000261 (0)
|
||||
#define ANOMALY_05000263 (0)
|
||||
#define ANOMALY_05000266 (0)
|
||||
#define ANOMALY_05000273 (0)
|
||||
#define ANOMALY_05000285 (0)
|
||||
#define ANOMALY_05000307 (0)
|
||||
#define ANOMALY_05000311 (0)
|
||||
#define ANOMALY_05000312 (0)
|
||||
#define ANOMALY_05000323 (0)
|
||||
#define ANOMALY_05000353 (0)
|
||||
#define ANOMALY_05000363 (0)
|
||||
#define ANOMALY_05000386 (0)
|
||||
|
||||
#endif
|
||||
|
|
@ -0,0 +1,132 @@
|
|||
/*
|
||||
* File: include/asm-blackfin/mach-bf518/bf518.h
|
||||
* Based on: include/asm-blackfin/mach-bf527/bf527.h
|
||||
* Author: Michael Hennerich (michael.hennerich@analog.com)
|
||||
*
|
||||
* Created:
|
||||
* Description: SYSTEM MMR REGISTER AND MEMORY MAP FOR ADSP-BF518
|
||||
*
|
||||
* Modified:
|
||||
* Copyright 2004-2007 Analog Devices Inc.
|
||||
*
|
||||
* Bugs: Enter bugs at http://blackfin.uclinux.org/
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, see the file COPYING, or write
|
||||
* to the Free Software Foundation, Inc.,
|
||||
* 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
*/
|
||||
|
||||
#ifndef __MACH_BF518_H__
|
||||
#define __MACH_BF518_H__
|
||||
|
||||
#define OFFSET_(x) ((x) & 0x0000FFFF)
|
||||
|
||||
/*some misc defines*/
|
||||
#define IMASK_IVG15 0x8000
|
||||
#define IMASK_IVG14 0x4000
|
||||
#define IMASK_IVG13 0x2000
|
||||
#define IMASK_IVG12 0x1000
|
||||
|
||||
#define IMASK_IVG11 0x0800
|
||||
#define IMASK_IVG10 0x0400
|
||||
#define IMASK_IVG9 0x0200
|
||||
#define IMASK_IVG8 0x0100
|
||||
|
||||
#define IMASK_IVG7 0x0080
|
||||
#define IMASK_IVGTMR 0x0040
|
||||
#define IMASK_IVGHW 0x0020
|
||||
|
||||
/***************************/
|
||||
|
||||
#define BFIN_DSUBBANKS 4
|
||||
#define BFIN_DWAYS 2
|
||||
#define BFIN_DLINES 64
|
||||
#define BFIN_ISUBBANKS 4
|
||||
#define BFIN_IWAYS 4
|
||||
#define BFIN_ILINES 32
|
||||
|
||||
#define WAY0_L 0x1
|
||||
#define WAY1_L 0x2
|
||||
#define WAY01_L 0x3
|
||||
#define WAY2_L 0x4
|
||||
#define WAY02_L 0x5
|
||||
#define WAY12_L 0x6
|
||||
#define WAY012_L 0x7
|
||||
|
||||
#define WAY3_L 0x8
|
||||
#define WAY03_L 0x9
|
||||
#define WAY13_L 0xA
|
||||
#define WAY013_L 0xB
|
||||
|
||||
#define WAY32_L 0xC
|
||||
#define WAY320_L 0xD
|
||||
#define WAY321_L 0xE
|
||||
#define WAYALL_L 0xF
|
||||
|
||||
#define DMC_ENABLE (2<<2) /*yes, 2, not 1 */
|
||||
|
||||
/********************************* EBIU Settings ************************************/
|
||||
#define AMBCTL0VAL ((CONFIG_BANK_1 << 16) | CONFIG_BANK_0)
|
||||
#define AMBCTL1VAL ((CONFIG_BANK_3 << 16) | CONFIG_BANK_2)
|
||||
|
||||
#ifdef CONFIG_C_AMBEN_ALL
|
||||
#define V_AMBEN AMBEN_ALL
|
||||
#endif
|
||||
#ifdef CONFIG_C_AMBEN
|
||||
#define V_AMBEN 0x0
|
||||
#endif
|
||||
#ifdef CONFIG_C_AMBEN_B0
|
||||
#define V_AMBEN AMBEN_B0
|
||||
#endif
|
||||
#ifdef CONFIG_C_AMBEN_B0_B1
|
||||
#define V_AMBEN AMBEN_B0_B1
|
||||
#endif
|
||||
#ifdef CONFIG_C_AMBEN_B0_B1_B2
|
||||
#define V_AMBEN AMBEN_B0_B1_B2
|
||||
#endif
|
||||
#ifdef CONFIG_C_AMCKEN
|
||||
#define V_AMCKEN AMCKEN
|
||||
#else
|
||||
#define V_AMCKEN 0x0
|
||||
#endif
|
||||
#ifdef CONFIG_C_CDPRIO
|
||||
#define V_CDPRIO 0x100
|
||||
#else
|
||||
#define V_CDPRIO 0x0
|
||||
#endif
|
||||
|
||||
#define AMGCTLVAL (V_AMBEN | V_AMCKEN | V_CDPRIO)
|
||||
|
||||
#ifdef CONFIG_BF518
|
||||
#define CPU "BF518"
|
||||
#define CPUID 0x27e8
|
||||
#endif
|
||||
#ifdef CONFIG_BF516
|
||||
#define CPU "BF516"
|
||||
#define CPUID 0x27e8
|
||||
#endif
|
||||
#ifdef CONFIG_BF514
|
||||
#define CPU "BF514"
|
||||
#define CPUID 0x27e8
|
||||
#endif
|
||||
#ifdef CONFIG_BF512
|
||||
#define CPU "BF512"
|
||||
#define CPUID 0x27e8
|
||||
#endif
|
||||
|
||||
#ifndef CPU
|
||||
#error "Unknown CPU type - This kernel doesn't seem to be configured properly"
|
||||
#endif
|
||||
|
||||
#endif /* __MACH_BF518_H__ */
|
||||
|
|
@ -0,0 +1,169 @@
|
|||
/*
|
||||
* file: include/asm-blackfin/mach-bf518/bfin_serial_5xx.h
|
||||
* based on:
|
||||
* author:
|
||||
*
|
||||
* created:
|
||||
* description:
|
||||
* blackfin serial driver head file
|
||||
* rev:
|
||||
*
|
||||
* modified:
|
||||
*
|
||||
*
|
||||
* bugs: enter bugs at http://blackfin.uclinux.org/
|
||||
*
|
||||
* this program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the gnu general public license as published by
|
||||
* the free software foundation; either version 2, or (at your option)
|
||||
* any later version.
|
||||
*
|
||||
* this program is distributed in the hope that it will be useful,
|
||||
* but without any warranty; without even the implied warranty of
|
||||
* merchantability or fitness for a particular purpose. see the
|
||||
* gnu general public license for more details.
|
||||
*
|
||||
* you should have received a copy of the gnu general public license
|
||||
* along with this program; see the file copying.
|
||||
* if not, write to the free software foundation,
|
||||
* 59 temple place - suite 330, boston, ma 02111-1307, usa.
|
||||
*/
|
||||
|
||||
#include <linux/serial.h>
|
||||
#include <asm/dma.h>
|
||||
#include <asm/portmux.h>
|
||||
|
||||
#define UART_GET_CHAR(uart) bfin_read16(((uart)->port.membase + OFFSET_RBR))
|
||||
#define UART_GET_DLL(uart) bfin_read16(((uart)->port.membase + OFFSET_DLL))
|
||||
#define UART_GET_IER(uart) bfin_read16(((uart)->port.membase + OFFSET_IER))
|
||||
#define UART_GET_DLH(uart) bfin_read16(((uart)->port.membase + OFFSET_DLH))
|
||||
#define UART_GET_IIR(uart) bfin_read16(((uart)->port.membase + OFFSET_IIR))
|
||||
#define UART_GET_LCR(uart) bfin_read16(((uart)->port.membase + OFFSET_LCR))
|
||||
#define UART_GET_GCTL(uart) bfin_read16(((uart)->port.membase + OFFSET_GCTL))
|
||||
|
||||
#define UART_PUT_CHAR(uart, v) bfin_write16(((uart)->port.membase + OFFSET_THR), v)
|
||||
#define UART_PUT_DLL(uart, v) bfin_write16(((uart)->port.membase + OFFSET_DLL), v)
|
||||
#define UART_PUT_IER(uart, v) bfin_write16(((uart)->port.membase + OFFSET_IER), v)
|
||||
#define UART_SET_IER(uart, v) UART_PUT_IER(uart, UART_GET_IER(uart) | (v))
|
||||
#define UART_CLEAR_IER(uart, v) UART_PUT_IER(uart, UART_GET_IER(uart) & ~(v))
|
||||
#define UART_PUT_DLH(uart, v) bfin_write16(((uart)->port.membase + OFFSET_DLH), v)
|
||||
#define UART_PUT_LCR(uart, v) bfin_write16(((uart)->port.membase + OFFSET_LCR), v)
|
||||
#define UART_PUT_GCTL(uart, v) bfin_write16(((uart)->port.membase + OFFSET_GCTL), v)
|
||||
|
||||
#define UART_SET_DLAB(uart) do { UART_PUT_LCR(uart, UART_GET_LCR(uart) | DLAB); SSYNC(); } while (0)
|
||||
#define UART_CLEAR_DLAB(uart) do { UART_PUT_LCR(uart, UART_GET_LCR(uart) & ~DLAB); SSYNC(); } while (0)
|
||||
|
||||
#define UART_GET_CTS(x) gpio_get_value(x->cts_pin)
|
||||
#define UART_SET_RTS(x) gpio_set_value(x->rts_pin, 1)
|
||||
#define UART_CLEAR_RTS(x) gpio_set_value(x->rts_pin, 0)
|
||||
#define UART_ENABLE_INTS(x, v) UART_PUT_IER(x, v)
|
||||
#define UART_DISABLE_INTS(x) UART_PUT_IER(x, 0)
|
||||
|
||||
#if defined(CONFIG_BFIN_UART0_CTSRTS) || defined(CONFIG_BFIN_UART1_CTSRTS)
|
||||
# define CONFIG_SERIAL_BFIN_CTSRTS
|
||||
|
||||
# ifndef CONFIG_UART0_CTS_PIN
|
||||
# define CONFIG_UART0_CTS_PIN -1
|
||||
# endif
|
||||
|
||||
# ifndef CONFIG_UART0_RTS_PIN
|
||||
# define CONFIG_UART0_RTS_PIN -1
|
||||
# endif
|
||||
|
||||
# ifndef CONFIG_UART1_CTS_PIN
|
||||
# define CONFIG_UART1_CTS_PIN -1
|
||||
# endif
|
||||
|
||||
# ifndef CONFIG_UART1_RTS_PIN
|
||||
# define CONFIG_UART1_RTS_PIN -1
|
||||
# endif
|
||||
#endif
|
||||
|
||||
#define BFIN_UART_TX_FIFO_SIZE 2
|
||||
|
||||
/*
|
||||
* The pin configuration is different from schematic
|
||||
*/
|
||||
struct bfin_serial_port {
|
||||
struct uart_port port;
|
||||
unsigned int old_status;
|
||||
unsigned int lsr;
|
||||
#ifdef CONFIG_SERIAL_BFIN_DMA
|
||||
int tx_done;
|
||||
int tx_count;
|
||||
struct circ_buf rx_dma_buf;
|
||||
struct timer_list rx_dma_timer;
|
||||
int rx_dma_nrows;
|
||||
unsigned int tx_dma_channel;
|
||||
unsigned int rx_dma_channel;
|
||||
struct work_struct tx_dma_workqueue;
|
||||
#endif
|
||||
#ifdef CONFIG_SERIAL_BFIN_CTSRTS
|
||||
struct timer_list cts_timer;
|
||||
int cts_pin;
|
||||
int rts_pin;
|
||||
#endif
|
||||
};
|
||||
|
||||
/* The hardware clears the LSR bits upon read, so we need to cache
|
||||
* some of the more fun bits in software so they don't get lost
|
||||
* when checking the LSR in other code paths (TX).
|
||||
*/
|
||||
static inline unsigned int UART_GET_LSR(struct bfin_serial_port *uart)
|
||||
{
|
||||
unsigned int lsr = bfin_read16(uart->port.membase + OFFSET_LSR);
|
||||
uart->lsr |= (lsr & (BI|FE|PE|OE));
|
||||
return lsr | uart->lsr;
|
||||
}
|
||||
|
||||
static inline void UART_CLEAR_LSR(struct bfin_serial_port *uart)
|
||||
{
|
||||
uart->lsr = 0;
|
||||
bfin_write16(uart->port.membase + OFFSET_LSR, -1);
|
||||
}
|
||||
|
||||
struct bfin_serial_res {
|
||||
unsigned long uart_base_addr;
|
||||
int uart_irq;
|
||||
#ifdef CONFIG_SERIAL_BFIN_DMA
|
||||
unsigned int uart_tx_dma_channel;
|
||||
unsigned int uart_rx_dma_channel;
|
||||
#endif
|
||||
#ifdef CONFIG_SERIAL_BFIN_CTSRTS
|
||||
int uart_cts_pin;
|
||||
int uart_rts_pin;
|
||||
#endif
|
||||
};
|
||||
|
||||
struct bfin_serial_res bfin_serial_resource[] = {
|
||||
#ifdef CONFIG_SERIAL_BFIN_UART0
|
||||
{
|
||||
0xFFC00400,
|
||||
IRQ_UART0_RX,
|
||||
#ifdef CONFIG_SERIAL_BFIN_DMA
|
||||
CH_UART0_TX,
|
||||
CH_UART0_RX,
|
||||
#endif
|
||||
#ifdef CONFIG_BFIN_UART0_CTSRTS
|
||||
CONFIG_UART0_CTS_PIN,
|
||||
CONFIG_UART0_RTS_PIN,
|
||||
#endif
|
||||
},
|
||||
#endif
|
||||
#ifdef CONFIG_SERIAL_BFIN_UART1
|
||||
{
|
||||
0xFFC02000,
|
||||
IRQ_UART1_RX,
|
||||
#ifdef CONFIG_SERIAL_BFIN_DMA
|
||||
CH_UART1_TX,
|
||||
CH_UART1_RX,
|
||||
#endif
|
||||
#ifdef CONFIG_BFIN_UART1_CTSRTS
|
||||
CONFIG_UART1_CTS_PIN,
|
||||
CONFIG_UART1_RTS_PIN,
|
||||
#endif
|
||||
},
|
||||
#endif
|
||||
};
|
||||
|
||||
#define DRIVER_NAME "bfin-uart"
|
||||
|
|
@ -0,0 +1,142 @@
|
|||
/*
|
||||
* Blackfin Infra-red Driver
|
||||
*
|
||||
* Copyright 2006-2008 Analog Devices Inc.
|
||||
*
|
||||
* Enter bugs at http://blackfin.uclinux.org/
|
||||
*
|
||||
* Licensed under the GPL-2 or later.
|
||||
*
|
||||
*/
|
||||
|
||||
#include <linux/serial.h>
|
||||
#include <asm/dma.h>
|
||||
#include <asm/portmux.h>
|
||||
|
||||
#define SIR_UART_GET_CHAR(port) bfin_read16((port)->membase + OFFSET_RBR)
|
||||
#define SIR_UART_GET_DLL(port) bfin_read16((port)->membase + OFFSET_DLL)
|
||||
#define SIR_UART_GET_IER(port) bfin_read16((port)->membase + OFFSET_IER)
|
||||
#define SIR_UART_GET_DLH(port) bfin_read16((port)->membase + OFFSET_DLH)
|
||||
#define SIR_UART_GET_IIR(port) bfin_read16((port)->membase + OFFSET_IIR)
|
||||
#define SIR_UART_GET_LCR(port) bfin_read16((port)->membase + OFFSET_LCR)
|
||||
#define SIR_UART_GET_GCTL(port) bfin_read16((port)->membase + OFFSET_GCTL)
|
||||
|
||||
#define SIR_UART_PUT_CHAR(port, v) bfin_write16(((port)->membase + OFFSET_THR), v)
|
||||
#define SIR_UART_PUT_DLL(port, v) bfin_write16(((port)->membase + OFFSET_DLL), v)
|
||||
#define SIR_UART_PUT_IER(port, v) bfin_write16(((port)->membase + OFFSET_IER), v)
|
||||
#define SIR_UART_PUT_DLH(port, v) bfin_write16(((port)->membase + OFFSET_DLH), v)
|
||||
#define SIR_UART_PUT_LCR(port, v) bfin_write16(((port)->membase + OFFSET_LCR), v)
|
||||
#define SIR_UART_PUT_GCTL(port, v) bfin_write16(((port)->membase + OFFSET_GCTL), v)
|
||||
|
||||
#ifdef CONFIG_SIR_BFIN_DMA
|
||||
struct dma_rx_buf {
|
||||
char *buf;
|
||||
int head;
|
||||
int tail;
|
||||
};
|
||||
#endif /* CONFIG_SIR_BFIN_DMA */
|
||||
|
||||
struct bfin_sir_port {
|
||||
unsigned char __iomem *membase;
|
||||
unsigned int irq;
|
||||
unsigned int lsr;
|
||||
unsigned long clk;
|
||||
struct net_device *dev;
|
||||
#ifdef CONFIG_SIR_BFIN_DMA
|
||||
int tx_done;
|
||||
struct dma_rx_buf rx_dma_buf;
|
||||
struct timer_list rx_dma_timer;
|
||||
int rx_dma_nrows;
|
||||
#endif /* CONFIG_SIR_BFIN_DMA */
|
||||
unsigned int tx_dma_channel;
|
||||
unsigned int rx_dma_channel;
|
||||
};
|
||||
|
||||
struct bfin_sir_port sir_ports[BFIN_UART_NR_PORTS];
|
||||
|
||||
struct bfin_sir_port_res {
|
||||
unsigned long base_addr;
|
||||
int irq;
|
||||
unsigned int rx_dma_channel;
|
||||
unsigned int tx_dma_channel;
|
||||
};
|
||||
|
||||
struct bfin_sir_port_res bfin_sir_port_resource[] = {
|
||||
#ifdef CONFIG_BFIN_SIR0
|
||||
{
|
||||
0xFFC00400,
|
||||
IRQ_UART0_RX,
|
||||
CH_UART0_RX,
|
||||
CH_UART0_TX,
|
||||
},
|
||||
#endif
|
||||
#ifdef CONFIG_BFIN_SIR1
|
||||
{
|
||||
0xFFC02000,
|
||||
IRQ_UART1_RX,
|
||||
CH_UART1_RX,
|
||||
CH_UART1_TX,
|
||||
},
|
||||
#endif
|
||||
};
|
||||
|
||||
int nr_sirs = ARRAY_SIZE(bfin_sir_port_resource);
|
||||
|
||||
struct bfin_sir_self {
|
||||
struct bfin_sir_port *sir_port;
|
||||
spinlock_t lock;
|
||||
unsigned int open;
|
||||
int speed;
|
||||
int newspeed;
|
||||
|
||||
struct sk_buff *txskb;
|
||||
struct sk_buff *rxskb;
|
||||
struct net_device_stats stats;
|
||||
struct device *dev;
|
||||
struct irlap_cb *irlap;
|
||||
struct qos_info qos;
|
||||
|
||||
iobuff_t tx_buff;
|
||||
iobuff_t rx_buff;
|
||||
|
||||
struct work_struct work;
|
||||
int mtt;
|
||||
};
|
||||
|
||||
static inline unsigned int SIR_UART_GET_LSR(struct bfin_sir_port *port)
|
||||
{
|
||||
unsigned int lsr = bfin_read16(port->membase + OFFSET_LSR);
|
||||
port->lsr |= (lsr & (BI|FE|PE|OE));
|
||||
return lsr | port->lsr;
|
||||
}
|
||||
|
||||
static inline void SIR_UART_CLEAR_LSR(struct bfin_sir_port *port)
|
||||
{
|
||||
port->lsr = 0;
|
||||
bfin_read16(port->membase + OFFSET_LSR);
|
||||
}
|
||||
|
||||
#define DRIVER_NAME "bfin_sir"
|
||||
|
||||
static int bfin_sir_hw_init(void)
|
||||
{
|
||||
int ret = -ENODEV;
|
||||
#ifdef CONFIG_BFIN_SIR0
|
||||
ret = peripheral_request(P_UART0_TX, DRIVER_NAME);
|
||||
if (ret)
|
||||
return ret;
|
||||
ret = peripheral_request(P_UART0_RX, DRIVER_NAME);
|
||||
if (ret)
|
||||
return ret;
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_BFIN_SIR1
|
||||
ret = peripheral_request(P_UART1_TX, DRIVER_NAME);
|
||||
if (ret)
|
||||
return ret;
|
||||
ret = peripheral_request(P_UART1_RX, DRIVER_NAME);
|
||||
if (ret)
|
||||
return ret;
|
||||
#endif
|
||||
return ret;
|
||||
}
|
||||
|
|
@ -0,0 +1,105 @@
|
|||
/*
|
||||
* File: include/asm-blackfin/mach-bf518/blackfin.h
|
||||
* Based on:
|
||||
* Author:
|
||||
*
|
||||
* Created:
|
||||
* Description:
|
||||
*
|
||||
* Rev:
|
||||
*
|
||||
* Modified:
|
||||
*
|
||||
*
|
||||
* Bugs: Enter bugs at http://blackfin.uclinux.org/
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2, or (at your option)
|
||||
* any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; see the file COPYING.
|
||||
* If not, write to the Free Software Foundation,
|
||||
* 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
|
||||
*/
|
||||
|
||||
#ifndef _MACH_BLACKFIN_H_
|
||||
#define _MACH_BLACKFIN_H_
|
||||
|
||||
#define BF518_FAMILY
|
||||
|
||||
#include "bf518.h"
|
||||
#include "mem_map.h"
|
||||
#include "defBF512.h"
|
||||
#include "anomaly.h"
|
||||
|
||||
#if defined(CONFIG_BF518)
|
||||
#include "defBF518.h"
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_BF516)
|
||||
#include "defBF516.h"
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_BF514)
|
||||
#include "defBF514.h"
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_BF512)
|
||||
#include "defBF512.h"
|
||||
#endif
|
||||
|
||||
#if !defined(__ASSEMBLY__)
|
||||
#include "cdefBF512.h"
|
||||
|
||||
#if defined(CONFIG_BF518)
|
||||
#include "cdefBF518.h"
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_BF516)
|
||||
#include "cdefBF516.h"
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_BF514)
|
||||
#include "cdefBF514.h"
|
||||
#endif
|
||||
#endif
|
||||
|
||||
/* UART_IIR Register */
|
||||
#define STATUS(x) ((x << 1) & 0x06)
|
||||
#define STATUS_P1 0x02
|
||||
#define STATUS_P0 0x01
|
||||
|
||||
#define BFIN_UART_NR_PORTS 2
|
||||
|
||||
#define OFFSET_THR 0x00 /* Transmit Holding register */
|
||||
#define OFFSET_RBR 0x00 /* Receive Buffer register */
|
||||
#define OFFSET_DLL 0x00 /* Divisor Latch (Low-Byte) */
|
||||
#define OFFSET_IER 0x04 /* Interrupt Enable Register */
|
||||
#define OFFSET_DLH 0x04 /* Divisor Latch (High-Byte) */
|
||||
#define OFFSET_IIR 0x08 /* Interrupt Identification Register */
|
||||
#define OFFSET_LCR 0x0C /* Line Control Register */
|
||||
#define OFFSET_MCR 0x10 /* Modem Control Register */
|
||||
#define OFFSET_LSR 0x14 /* Line Status Register */
|
||||
#define OFFSET_MSR 0x18 /* Modem Status Register */
|
||||
#define OFFSET_SCR 0x1C /* SCR Scratch Register */
|
||||
#define OFFSET_GCTL 0x24 /* Global Control Register */
|
||||
|
||||
/* DPMC*/
|
||||
#define bfin_read_STOPCK_OFF() bfin_read_STOPCK()
|
||||
#define bfin_write_STOPCK_OFF(val) bfin_write_STOPCK(val)
|
||||
#define STOPCK_OFF STOPCK
|
||||
|
||||
/* PLL_DIV Masks */
|
||||
#define CCLK_DIV1 CSEL_DIV1 /* CCLK = VCO / 1 */
|
||||
#define CCLK_DIV2 CSEL_DIV2 /* CCLK = VCO / 2 */
|
||||
#define CCLK_DIV4 CSEL_DIV4 /* CCLK = VCO / 4 */
|
||||
#define CCLK_DIV8 CSEL_DIV8 /* CCLK = VCO / 8 */
|
||||
|
||||
#endif
|
||||
|
|
@ -0,0 +1,46 @@
|
|||
/*
|
||||
* File: include/asm-blackfin/mach-bf518/cdefbf512.h
|
||||
* Based on:
|
||||
* Author:
|
||||
*
|
||||
* Created:
|
||||
* Description: system mmr register map
|
||||
*
|
||||
* Rev:
|
||||
*
|
||||
* Modified:
|
||||
*
|
||||
*
|
||||
* Bugs: Enter bugs at http://blackfin.uclinux.org/
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2, or (at your option)
|
||||
* any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; see the file COPYING.
|
||||
* If not, write to the Free Software Foundation,
|
||||
* 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
|
||||
*/
|
||||
|
||||
#ifndef _CDEF_BF512_H
|
||||
#define _CDEF_BF512_H
|
||||
|
||||
/* include all Core registers and bit definitions */
|
||||
#include "defBF512.h"
|
||||
|
||||
/* include core specific register pointer definitions */
|
||||
#include <asm/cdef_LPBlackfin.h>
|
||||
|
||||
/* SYSTEM & MMR ADDRESS DEFINITIONS FOR ADSP-BF512 */
|
||||
|
||||
/* include cdefBF51x_base.h for the set of #defines that are common to all ADSP-BF51x processors */
|
||||
#include "cdefBF51x_base.h"
|
||||
|
||||
#endif /* _CDEF_BF512_H */
|
||||
|
|
@ -0,0 +1,48 @@
|
|||
/*
|
||||
* File: include/asm-blackfin/mach-bf518/cdefbf514.h
|
||||
* Based on:
|
||||
* Author:
|
||||
*
|
||||
* Created:
|
||||
* Description: system mmr register map
|
||||
*
|
||||
* Rev:
|
||||
*
|
||||
* Modified:
|
||||
*
|
||||
*
|
||||
* Bugs: Enter bugs at http://blackfin.uclinux.org/
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2, or (at your option)
|
||||
* any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; see the file COPYING.
|
||||
* If not, write to the Free Software Foundation,
|
||||
* 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
|
||||
*/
|
||||
|
||||
#ifndef _CDEF_BF514_H
|
||||
#define _CDEF_BF514_H
|
||||
|
||||
/* include all Core registers and bit definitions */
|
||||
#include "defBF514.h"
|
||||
|
||||
/* include core specific register pointer definitions */
|
||||
#include <asm/cdef_LPBlackfin.h>
|
||||
|
||||
/* SYSTEM & MMR ADDRESS DEFINITIONS FOR ADSP-BF514 */
|
||||
|
||||
/* include cdefBF51x_base.h for the set of #defines that are common to all ADSP-BF51x processors */
|
||||
#include "cdefBF51x_base.h"
|
||||
|
||||
/* The following are the #defines needed by ADSP-BF514 that are not in the common header */
|
||||
|
||||
#endif /* _CDEF_BF514_H */
|
||||
|
|
@ -0,0 +1,48 @@
|
|||
/*
|
||||
* File: include/asm-blackfin/mach-bf518/cdefbf516.h
|
||||
* Based on:
|
||||
* Author:
|
||||
*
|
||||
* Created:
|
||||
* Description: system mmr register map
|
||||
*
|
||||
* Rev:
|
||||
*
|
||||
* Modified:
|
||||
*
|
||||
*
|
||||
* Bugs: Enter bugs at http://blackfin.uclinux.org/
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2, or (at your option)
|
||||
* any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; see the file COPYING.
|
||||
* If not, write to the Free Software Foundation,
|
||||
* 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
|
||||
*/
|
||||
|
||||
#ifndef _CDEF_BF516_H
|
||||
#define _CDEF_BF516_H
|
||||
|
||||
/* include all Core registers and bit definitions */
|
||||
#include "defBF516.h"
|
||||
|
||||
/* include core specific register pointer definitions */
|
||||
#include <asm/cdef_LPBlackfin.h>
|
||||
|
||||
/* SYSTEM & MMR ADDRESS DEFINITIONS FOR ADSP-BF516 */
|
||||
|
||||
/* include cdefBF51x_base.h for the set of #defines that are common to all ADSP-BF51x processors */
|
||||
#include "cdefBF51x_base.h"
|
||||
|
||||
/* The following are the #defines needed by ADSP-BF516 that are not in the common header */
|
||||
|
||||
#endif /* _CDEF_BF516_H */
|
||||
|
|
@ -0,0 +1,48 @@
|
|||
/*
|
||||
* File: include/asm-blackfin/mach-bf518/cdefbf518.h
|
||||
* Based on:
|
||||
* Author:
|
||||
*
|
||||
* Created:
|
||||
* Description: system mmr register map
|
||||
*
|
||||
* Rev:
|
||||
*
|
||||
* Modified:
|
||||
*
|
||||
*
|
||||
* Bugs: Enter bugs at http://blackfin.uclinux.org/
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2, or (at your option)
|
||||
* any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; see the file COPYING.
|
||||
* If not, write to the Free Software Foundation,
|
||||
* 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
|
||||
*/
|
||||
|
||||
#ifndef _CDEF_BF518_H
|
||||
#define _CDEF_BF518_H
|
||||
|
||||
/* include all Core registers and bit definitions */
|
||||
#include "defBF518.h"
|
||||
|
||||
/* include core specific register pointer definitions */
|
||||
#include <asm/cdef_LPBlackfin.h>
|
||||
|
||||
/* SYSTEM & MMR ADDRESS DEFINITIONS FOR ADSP-BF518 */
|
||||
|
||||
/* include cdefBF51x_base.h for the set of #defines that are common to all ADSP-BF51x processors */
|
||||
#include "cdefBF51x_base.h"
|
||||
|
||||
/* The following are the #defines needed by ADSP-BF518 that are not in the common header */
|
||||
|
||||
#endif /* _CDEF_BF518_H */
|
||||
Разница между файлами не показана из-за своего большого размера
Загрузить разницу
|
|
@ -0,0 +1,42 @@
|
|||
/*
|
||||
* File: include/asm-blackfin/mach-bf518/defBF512.h
|
||||
* Based on:
|
||||
* Author:
|
||||
*
|
||||
* Created:
|
||||
* Description:
|
||||
*
|
||||
* Rev:
|
||||
*
|
||||
* Modified:
|
||||
*
|
||||
* Bugs: Enter bugs at http://blackfin.uclinux.org/
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2, or (at your option)
|
||||
* any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; see the file COPYING.
|
||||
* If not, write to the Free Software Foundation,
|
||||
* 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
|
||||
*/
|
||||
|
||||
#ifndef _DEF_BF512_H
|
||||
#define _DEF_BF512_H
|
||||
|
||||
/* Include all Core registers and bit definitions */
|
||||
#include <asm/def_LPBlackfin.h>
|
||||
|
||||
/* SYSTEM & MMR ADDRESS DEFINITIONS FOR ADSP-BF512 */
|
||||
|
||||
/* Include defBF51x_base.h for the set of #defines that are common to all ADSP-BF51x processors */
|
||||
#include "defBF51x_base.h"
|
||||
|
||||
#endif /* _DEF_BF512_H */
|
||||
|
|
@ -0,0 +1,113 @@
|
|||
/*
|
||||
* File: include/asm-blackfin/mach-bf518/defBF514.h
|
||||
* Based on:
|
||||
* Author:
|
||||
*
|
||||
* Created:
|
||||
* Description:
|
||||
*
|
||||
* Rev:
|
||||
*
|
||||
* Modified:
|
||||
*
|
||||
* Bugs: Enter bugs at http://blackfin.uclinux.org/
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2, or (at your option)
|
||||
* any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; see the file COPYING.
|
||||
* If not, write to the Free Software Foundation,
|
||||
* 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
|
||||
*/
|
||||
|
||||
#ifndef _DEF_BF514_H
|
||||
#define _DEF_BF514_H
|
||||
|
||||
/* Include all Core registers and bit definitions */
|
||||
#include <asm/def_LPBlackfin.h>
|
||||
|
||||
/* SYSTEM & MMR ADDRESS DEFINITIONS FOR ADSP-BF514 */
|
||||
|
||||
/* Include defBF51x_base.h for the set of #defines that are common to all ADSP-BF51x processors */
|
||||
#include "defBF51x_base.h"
|
||||
|
||||
/* The following are the #defines needed by ADSP-BF514 that are not in the common header */
|
||||
|
||||
/* SDH Registers */
|
||||
|
||||
#define SDH_PWR_CTL 0xFFC03900 /* SDH Power Control */
|
||||
#define SDH_CLK_CTL 0xFFC03904 /* SDH Clock Control */
|
||||
#define SDH_ARGUMENT 0xFFC03908 /* SDH Argument */
|
||||
#define SDH_COMMAND 0xFFC0390C /* SDH Command */
|
||||
#define SDH_RESP_CMD 0xFFC03910 /* SDH Response Command */
|
||||
#define SDH_RESPONSE0 0xFFC03914 /* SDH Response0 */
|
||||
#define SDH_RESPONSE1 0xFFC03918 /* SDH Response1 */
|
||||
#define SDH_RESPONSE2 0xFFC0391C /* SDH Response2 */
|
||||
#define SDH_RESPONSE3 0xFFC03920 /* SDH Response3 */
|
||||
#define SDH_DATA_TIMER 0xFFC03924 /* SDH Data Timer */
|
||||
#define SDH_DATA_LGTH 0xFFC03928 /* SDH Data Length */
|
||||
#define SDH_DATA_CTL 0xFFC0392C /* SDH Data Control */
|
||||
#define SDH_DATA_CNT 0xFFC03930 /* SDH Data Counter */
|
||||
#define SDH_STATUS 0xFFC03934 /* SDH Status */
|
||||
#define SDH_STATUS_CLR 0xFFC03938 /* SDH Status Clear */
|
||||
#define SDH_MASK0 0xFFC0393C /* SDH Interrupt0 Mask */
|
||||
#define SDH_MASK1 0xFFC03940 /* SDH Interrupt1 Mask */
|
||||
#define SDH_FIFO_CNT 0xFFC03948 /* SDH FIFO Counter */
|
||||
#define SDH_FIFO 0xFFC03980 /* SDH Data FIFO */
|
||||
#define SDH_E_STATUS 0xFFC039C0 /* SDH Exception Status */
|
||||
#define SDH_E_MASK 0xFFC039C4 /* SDH Exception Mask */
|
||||
#define SDH_CFG 0xFFC039C8 /* SDH Configuration */
|
||||
#define SDH_RD_WAIT_EN 0xFFC039CC /* SDH Read Wait Enable */
|
||||
#define SDH_PID0 0xFFC039D0 /* SDH Peripheral Identification0 */
|
||||
#define SDH_PID1 0xFFC039D4 /* SDH Peripheral Identification1 */
|
||||
#define SDH_PID2 0xFFC039D8 /* SDH Peripheral Identification2 */
|
||||
#define SDH_PID3 0xFFC039DC /* SDH Peripheral Identification3 */
|
||||
#define SDH_PID4 0xFFC039E0 /* SDH Peripheral Identification4 */
|
||||
#define SDH_PID5 0xFFC039E4 /* SDH Peripheral Identification5 */
|
||||
#define SDH_PID6 0xFFC039E8 /* SDH Peripheral Identification6 */
|
||||
#define SDH_PID7 0xFFC039EC /* SDH Peripheral Identification7 */
|
||||
|
||||
/* Removable Storage Interface Registers */
|
||||
|
||||
#define RSI_PWR_CONTROL 0xFFC03800 /* RSI Power Control Register */
|
||||
#define RSI_CLK_CONTROL 0xFFC03804 /* RSI Clock Control Register */
|
||||
#define RSI_ARGUMENT 0xFFC03808 /* RSI Argument Register */
|
||||
#define RSI_COMMAND 0xFFC0380C /* RSI Command Register */
|
||||
#define RSI_RESP_CMD 0xFFC03810 /* RSI Response Command Register */
|
||||
#define RSI_RESPONSE0 0xFFC03814 /* RSI Response Register */
|
||||
#define RSI_RESPONSE1 0xFFC03818 /* RSI Response Register */
|
||||
#define RSI_RESPONSE2 0xFFC0381C /* RSI Response Register */
|
||||
#define RSI_RESPONSE3 0xFFC03820 /* RSI Response Register */
|
||||
#define RSI_DATA_TIMER 0xFFC03824 /* RSI Data Timer Register */
|
||||
#define RSI_DATA_LGTH 0xFFC03828 /* RSI Data Length Register */
|
||||
#define RSI_DATA_CONTROL 0xFFC0382C /* RSI Data Control Register */
|
||||
#define RSI_DATA_CNT 0xFFC03830 /* RSI Data Counter Register */
|
||||
#define RSI_STATUS 0xFFC03834 /* RSI Status Register */
|
||||
#define RSI_STATUSCL 0xFFC03838 /* RSI Status Clear Register */
|
||||
#define RSI_MASK0 0xFFC0383C /* RSI Interrupt 0 Mask Register */
|
||||
#define RSI_MASK1 0xFFC03840 /* RSI Interrupt 1 Mask Register */
|
||||
#define RSI_FIFO_CNT 0xFFC03848 /* RSI FIFO Counter Register */
|
||||
#define RSI_CEATA_CONTROL 0xFFC0384C /* RSI CEATA Register */
|
||||
#define RSI_FIFO 0xFFC03880 /* RSI Data FIFO Register */
|
||||
#define RSI_ESTAT 0xFFC038C0 /* RSI Exception Status Register */
|
||||
#define RSI_EMASK 0xFFC038C4 /* RSI Exception Mask Register */
|
||||
#define RSI_CONFIG 0xFFC038C8 /* RSI Configuration Register */
|
||||
#define RSI_RD_WAIT_EN 0xFFC038CC /* RSI Read Wait Enable Register */
|
||||
#define RSI_PID0 0xFFC03FE0 /* RSI Peripheral ID Register 0 */
|
||||
#define RSI_PID1 0xFFC03FE4 /* RSI Peripheral ID Register 1 */
|
||||
#define RSI_PID2 0xFFC03FE8 /* RSI Peripheral ID Register 2 */
|
||||
#define RSI_PID3 0xFFC03FEC /* RSI Peripheral ID Register 3 */
|
||||
#define RSI_PID4 0xFFC03FF0 /* RSI Peripheral ID Register 4 */
|
||||
#define RSI_PID5 0xFFC03FF4 /* RSI Peripheral ID Register 5 */
|
||||
#define RSI_PID6 0xFFC03FF8 /* RSI Peripheral ID Register 6 */
|
||||
#define RSI_PID7 0xFFC03FFC /* RSI Peripheral ID Register 7 */
|
||||
|
||||
#endif /* _DEF_BF514_H */
|
||||
|
|
@ -0,0 +1,490 @@
|
|||
/*
|
||||
* File: include/asm-blackfin/mach-bf518/defBF516.h
|
||||
* Based on:
|
||||
* Author:
|
||||
*
|
||||
* Created:
|
||||
* Description:
|
||||
*
|
||||
* Rev:
|
||||
*
|
||||
* Modified:
|
||||
*
|
||||
* Bugs: Enter bugs at http://blackfin.uclinux.org/
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2, or (at your option)
|
||||
* any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; see the file COPYING.
|
||||
* If not, write to the Free Software Foundation,
|
||||
* 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
|
||||
*/
|
||||
|
||||
#ifndef _DEF_BF516_H
|
||||
#define _DEF_BF516_H
|
||||
|
||||
/* Include all Core registers and bit definitions */
|
||||
#include <asm/def_LPBlackfin.h>
|
||||
|
||||
/* SYSTEM & MMR ADDRESS DEFINITIONS FOR ADSP-BF516 */
|
||||
|
||||
/* Include defBF51x_base.h for the set of #defines that are common to all ADSP-BF51x processors */
|
||||
#include "defBF51x_base.h"
|
||||
|
||||
/* The following are the #defines needed by ADSP-BF516 that are not in the common header */
|
||||
/* 10/100 Ethernet Controller (0xFFC03000 - 0xFFC031FF) */
|
||||
|
||||
#define EMAC_OPMODE 0xFFC03000 /* Operating Mode Register */
|
||||
#define EMAC_ADDRLO 0xFFC03004 /* Address Low (32 LSBs) Register */
|
||||
#define EMAC_ADDRHI 0xFFC03008 /* Address High (16 MSBs) Register */
|
||||
#define EMAC_HASHLO 0xFFC0300C /* Multicast Hash Table Low (Bins 31-0) Register */
|
||||
#define EMAC_HASHHI 0xFFC03010 /* Multicast Hash Table High (Bins 63-32) Register */
|
||||
#define EMAC_STAADD 0xFFC03014 /* Station Management Address Register */
|
||||
#define EMAC_STADAT 0xFFC03018 /* Station Management Data Register */
|
||||
#define EMAC_FLC 0xFFC0301C /* Flow Control Register */
|
||||
#define EMAC_VLAN1 0xFFC03020 /* VLAN1 Tag Register */
|
||||
#define EMAC_VLAN2 0xFFC03024 /* VLAN2 Tag Register */
|
||||
#define EMAC_WKUP_CTL 0xFFC0302C /* Wake-Up Control/Status Register */
|
||||
#define EMAC_WKUP_FFMSK0 0xFFC03030 /* Wake-Up Frame Filter 0 Byte Mask Register */
|
||||
#define EMAC_WKUP_FFMSK1 0xFFC03034 /* Wake-Up Frame Filter 1 Byte Mask Register */
|
||||
#define EMAC_WKUP_FFMSK2 0xFFC03038 /* Wake-Up Frame Filter 2 Byte Mask Register */
|
||||
#define EMAC_WKUP_FFMSK3 0xFFC0303C /* Wake-Up Frame Filter 3 Byte Mask Register */
|
||||
#define EMAC_WKUP_FFCMD 0xFFC03040 /* Wake-Up Frame Filter Commands Register */
|
||||
#define EMAC_WKUP_FFOFF 0xFFC03044 /* Wake-Up Frame Filter Offsets Register */
|
||||
#define EMAC_WKUP_FFCRC0 0xFFC03048 /* Wake-Up Frame Filter 0,1 CRC-16 Register */
|
||||
#define EMAC_WKUP_FFCRC1 0xFFC0304C /* Wake-Up Frame Filter 2,3 CRC-16 Register */
|
||||
|
||||
#define EMAC_SYSCTL 0xFFC03060 /* EMAC System Control Register */
|
||||
#define EMAC_SYSTAT 0xFFC03064 /* EMAC System Status Register */
|
||||
#define EMAC_RX_STAT 0xFFC03068 /* RX Current Frame Status Register */
|
||||
#define EMAC_RX_STKY 0xFFC0306C /* RX Sticky Frame Status Register */
|
||||
#define EMAC_RX_IRQE 0xFFC03070 /* RX Frame Status Interrupt Enables Register */
|
||||
#define EMAC_TX_STAT 0xFFC03074 /* TX Current Frame Status Register */
|
||||
#define EMAC_TX_STKY 0xFFC03078 /* TX Sticky Frame Status Register */
|
||||
#define EMAC_TX_IRQE 0xFFC0307C /* TX Frame Status Interrupt Enables Register */
|
||||
|
||||
#define EMAC_MMC_CTL 0xFFC03080 /* MMC Counter Control Register */
|
||||
#define EMAC_MMC_RIRQS 0xFFC03084 /* MMC RX Interrupt Status Register */
|
||||
#define EMAC_MMC_RIRQE 0xFFC03088 /* MMC RX Interrupt Enables Register */
|
||||
#define EMAC_MMC_TIRQS 0xFFC0308C /* MMC TX Interrupt Status Register */
|
||||
#define EMAC_MMC_TIRQE 0xFFC03090 /* MMC TX Interrupt Enables Register */
|
||||
|
||||
#define EMAC_RXC_OK 0xFFC03100 /* RX Frame Successful Count */
|
||||
#define EMAC_RXC_FCS 0xFFC03104 /* RX Frame FCS Failure Count */
|
||||
#define EMAC_RXC_ALIGN 0xFFC03108 /* RX Alignment Error Count */
|
||||
#define EMAC_RXC_OCTET 0xFFC0310C /* RX Octets Successfully Received Count */
|
||||
#define EMAC_RXC_DMAOVF 0xFFC03110 /* Internal MAC Sublayer Error RX Frame Count */
|
||||
#define EMAC_RXC_UNICST 0xFFC03114 /* Unicast RX Frame Count */
|
||||
#define EMAC_RXC_MULTI 0xFFC03118 /* Multicast RX Frame Count */
|
||||
#define EMAC_RXC_BROAD 0xFFC0311C /* Broadcast RX Frame Count */
|
||||
#define EMAC_RXC_LNERRI 0xFFC03120 /* RX Frame In Range Error Count */
|
||||
#define EMAC_RXC_LNERRO 0xFFC03124 /* RX Frame Out Of Range Error Count */
|
||||
#define EMAC_RXC_LONG 0xFFC03128 /* RX Frame Too Long Count */
|
||||
#define EMAC_RXC_MACCTL 0xFFC0312C /* MAC Control RX Frame Count */
|
||||
#define EMAC_RXC_OPCODE 0xFFC03130 /* Unsupported Op-Code RX Frame Count */
|
||||
#define EMAC_RXC_PAUSE 0xFFC03134 /* MAC Control Pause RX Frame Count */
|
||||
#define EMAC_RXC_ALLFRM 0xFFC03138 /* Overall RX Frame Count */
|
||||
#define EMAC_RXC_ALLOCT 0xFFC0313C /* Overall RX Octet Count */
|
||||
#define EMAC_RXC_TYPED 0xFFC03140 /* Type/Length Consistent RX Frame Count */
|
||||
#define EMAC_RXC_SHORT 0xFFC03144 /* RX Frame Fragment Count - Byte Count x < 64 */
|
||||
#define EMAC_RXC_EQ64 0xFFC03148 /* Good RX Frame Count - Byte Count x = 64 */
|
||||
#define EMAC_RXC_LT128 0xFFC0314C /* Good RX Frame Count - Byte Count 64 < x < 128 */
|
||||
#define EMAC_RXC_LT256 0xFFC03150 /* Good RX Frame Count - Byte Count 128 <= x < 256 */
|
||||
#define EMAC_RXC_LT512 0xFFC03154 /* Good RX Frame Count - Byte Count 256 <= x < 512 */
|
||||
#define EMAC_RXC_LT1024 0xFFC03158 /* Good RX Frame Count - Byte Count 512 <= x < 1024 */
|
||||
#define EMAC_RXC_GE1024 0xFFC0315C /* Good RX Frame Count - Byte Count x >= 1024 */
|
||||
|
||||
#define EMAC_TXC_OK 0xFFC03180 /* TX Frame Successful Count */
|
||||
#define EMAC_TXC_1COL 0xFFC03184 /* TX Frames Successful After Single Collision Count */
|
||||
#define EMAC_TXC_GT1COL 0xFFC03188 /* TX Frames Successful After Multiple Collisions Count */
|
||||
#define EMAC_TXC_OCTET 0xFFC0318C /* TX Octets Successfully Received Count */
|
||||
#define EMAC_TXC_DEFER 0xFFC03190 /* TX Frame Delayed Due To Busy Count */
|
||||
#define EMAC_TXC_LATECL 0xFFC03194 /* Late TX Collisions Count */
|
||||
#define EMAC_TXC_XS_COL 0xFFC03198 /* TX Frame Failed Due To Excessive Collisions Count */
|
||||
#define EMAC_TXC_DMAUND 0xFFC0319C /* Internal MAC Sublayer Error TX Frame Count */
|
||||
#define EMAC_TXC_CRSERR 0xFFC031A0 /* Carrier Sense Deasserted During TX Frame Count */
|
||||
#define EMAC_TXC_UNICST 0xFFC031A4 /* Unicast TX Frame Count */
|
||||
#define EMAC_TXC_MULTI 0xFFC031A8 /* Multicast TX Frame Count */
|
||||
#define EMAC_TXC_BROAD 0xFFC031AC /* Broadcast TX Frame Count */
|
||||
#define EMAC_TXC_XS_DFR 0xFFC031B0 /* TX Frames With Excessive Deferral Count */
|
||||
#define EMAC_TXC_MACCTL 0xFFC031B4 /* MAC Control TX Frame Count */
|
||||
#define EMAC_TXC_ALLFRM 0xFFC031B8 /* Overall TX Frame Count */
|
||||
#define EMAC_TXC_ALLOCT 0xFFC031BC /* Overall TX Octet Count */
|
||||
#define EMAC_TXC_EQ64 0xFFC031C0 /* Good TX Frame Count - Byte Count x = 64 */
|
||||
#define EMAC_TXC_LT128 0xFFC031C4 /* Good TX Frame Count - Byte Count 64 < x < 128 */
|
||||
#define EMAC_TXC_LT256 0xFFC031C8 /* Good TX Frame Count - Byte Count 128 <= x < 256 */
|
||||
#define EMAC_TXC_LT512 0xFFC031CC /* Good TX Frame Count - Byte Count 256 <= x < 512 */
|
||||
#define EMAC_TXC_LT1024 0xFFC031D0 /* Good TX Frame Count - Byte Count 512 <= x < 1024 */
|
||||
#define EMAC_TXC_GE1024 0xFFC031D4 /* Good TX Frame Count - Byte Count x >= 1024 */
|
||||
#define EMAC_TXC_ABORT 0xFFC031D8 /* Total TX Frames Aborted Count */
|
||||
|
||||
/* Listing for IEEE-Supported Count Registers */
|
||||
|
||||
#define FramesReceivedOK EMAC_RXC_OK /* RX Frame Successful Count */
|
||||
#define FrameCheckSequenceErrors EMAC_RXC_FCS /* RX Frame FCS Failure Count */
|
||||
#define AlignmentErrors EMAC_RXC_ALIGN /* RX Alignment Error Count */
|
||||
#define OctetsReceivedOK EMAC_RXC_OCTET /* RX Octets Successfully Received Count */
|
||||
#define FramesLostDueToIntMACRcvError EMAC_RXC_DMAOVF /* Internal MAC Sublayer Error RX Frame Count */
|
||||
#define UnicastFramesReceivedOK EMAC_RXC_UNICST /* Unicast RX Frame Count */
|
||||
#define MulticastFramesReceivedOK EMAC_RXC_MULTI /* Multicast RX Frame Count */
|
||||
#define BroadcastFramesReceivedOK EMAC_RXC_BROAD /* Broadcast RX Frame Count */
|
||||
#define InRangeLengthErrors EMAC_RXC_LNERRI /* RX Frame In Range Error Count */
|
||||
#define OutOfRangeLengthField EMAC_RXC_LNERRO /* RX Frame Out Of Range Error Count */
|
||||
#define FrameTooLongErrors EMAC_RXC_LONG /* RX Frame Too Long Count */
|
||||
#define MACControlFramesReceived EMAC_RXC_MACCTL /* MAC Control RX Frame Count */
|
||||
#define UnsupportedOpcodesReceived EMAC_RXC_OPCODE /* Unsupported Op-Code RX Frame Count */
|
||||
#define PAUSEMACCtrlFramesReceived EMAC_RXC_PAUSE /* MAC Control Pause RX Frame Count */
|
||||
#define FramesReceivedAll EMAC_RXC_ALLFRM /* Overall RX Frame Count */
|
||||
#define OctetsReceivedAll EMAC_RXC_ALLOCT /* Overall RX Octet Count */
|
||||
#define TypedFramesReceived EMAC_RXC_TYPED /* Type/Length Consistent RX Frame Count */
|
||||
#define FramesLenLt64Received EMAC_RXC_SHORT /* RX Frame Fragment Count - Byte Count x < 64 */
|
||||
#define FramesLenEq64Received EMAC_RXC_EQ64 /* Good RX Frame Count - Byte Count x = 64 */
|
||||
#define FramesLen65_127Received EMAC_RXC_LT128 /* Good RX Frame Count - Byte Count 64 < x < 128 */
|
||||
#define FramesLen128_255Received EMAC_RXC_LT256 /* Good RX Frame Count - Byte Count 128 <= x < 256 */
|
||||
#define FramesLen256_511Received EMAC_RXC_LT512 /* Good RX Frame Count - Byte Count 256 <= x < 512 */
|
||||
#define FramesLen512_1023Received EMAC_RXC_LT1024 /* Good RX Frame Count - Byte Count 512 <= x < 1024 */
|
||||
#define FramesLen1024_MaxReceived EMAC_RXC_GE1024 /* Good RX Frame Count - Byte Count x >= 1024 */
|
||||
|
||||
#define FramesTransmittedOK EMAC_TXC_OK /* TX Frame Successful Count */
|
||||
#define SingleCollisionFrames EMAC_TXC_1COL /* TX Frames Successful After Single Collision Count */
|
||||
#define MultipleCollisionFrames EMAC_TXC_GT1COL /* TX Frames Successful After Multiple Collisions Count */
|
||||
#define OctetsTransmittedOK EMAC_TXC_OCTET /* TX Octets Successfully Received Count */
|
||||
#define FramesWithDeferredXmissions EMAC_TXC_DEFER /* TX Frame Delayed Due To Busy Count */
|
||||
#define LateCollisions EMAC_TXC_LATECL /* Late TX Collisions Count */
|
||||
#define FramesAbortedDueToXSColls EMAC_TXC_XS_COL /* TX Frame Failed Due To Excessive Collisions Count */
|
||||
#define FramesLostDueToIntMacXmitError EMAC_TXC_DMAUND /* Internal MAC Sublayer Error TX Frame Count */
|
||||
#define CarrierSenseErrors EMAC_TXC_CRSERR /* Carrier Sense Deasserted During TX Frame Count */
|
||||
#define UnicastFramesXmittedOK EMAC_TXC_UNICST /* Unicast TX Frame Count */
|
||||
#define MulticastFramesXmittedOK EMAC_TXC_MULTI /* Multicast TX Frame Count */
|
||||
#define BroadcastFramesXmittedOK EMAC_TXC_BROAD /* Broadcast TX Frame Count */
|
||||
#define FramesWithExcessiveDeferral EMAC_TXC_XS_DFR /* TX Frames With Excessive Deferral Count */
|
||||
#define MACControlFramesTransmitted EMAC_TXC_MACCTL /* MAC Control TX Frame Count */
|
||||
#define FramesTransmittedAll EMAC_TXC_ALLFRM /* Overall TX Frame Count */
|
||||
#define OctetsTransmittedAll EMAC_TXC_ALLOCT /* Overall TX Octet Count */
|
||||
#define FramesLenEq64Transmitted EMAC_TXC_EQ64 /* Good TX Frame Count - Byte Count x = 64 */
|
||||
#define FramesLen65_127Transmitted EMAC_TXC_LT128 /* Good TX Frame Count - Byte Count 64 < x < 128 */
|
||||
#define FramesLen128_255Transmitted EMAC_TXC_LT256 /* Good TX Frame Count - Byte Count 128 <= x < 256 */
|
||||
#define FramesLen256_511Transmitted EMAC_TXC_LT512 /* Good TX Frame Count - Byte Count 256 <= x < 512 */
|
||||
#define FramesLen512_1023Transmitted EMAC_TXC_LT1024 /* Good TX Frame Count - Byte Count 512 <= x < 1024 */
|
||||
#define FramesLen1024_MaxTransmitted EMAC_TXC_GE1024 /* Good TX Frame Count - Byte Count x >= 1024 */
|
||||
#define TxAbortedFrames EMAC_TXC_ABORT /* Total TX Frames Aborted Count */
|
||||
|
||||
/***********************************************************************************
|
||||
** System MMR Register Bits And Macros
|
||||
**
|
||||
** Disclaimer: All macros are intended to make C and Assembly code more readable.
|
||||
** Use these macros carefully, as any that do left shifts for field
|
||||
** depositing will result in the lower order bits being destroyed. Any
|
||||
** macro that shifts left to properly position the bit-field should be
|
||||
** used as part of an OR to initialize a register and NOT as a dynamic
|
||||
** modifier UNLESS the lower order bits are saved and ORed back in when
|
||||
** the macro is used.
|
||||
*************************************************************************************/
|
||||
|
||||
/************************ ETHERNET 10/100 CONTROLLER MASKS ************************/
|
||||
|
||||
/* EMAC_OPMODE Masks */
|
||||
|
||||
#define RE 0x00000001 /* Receiver Enable */
|
||||
#define ASTP 0x00000002 /* Enable Automatic Pad Stripping On RX Frames */
|
||||
#define HU 0x00000010 /* Hash Filter Unicast Address */
|
||||
#define HM 0x00000020 /* Hash Filter Multicast Address */
|
||||
#define PAM 0x00000040 /* Pass-All-Multicast Mode Enable */
|
||||
#define PR 0x00000080 /* Promiscuous Mode Enable */
|
||||
#define IFE 0x00000100 /* Inverse Filtering Enable */
|
||||
#define DBF 0x00000200 /* Disable Broadcast Frame Reception */
|
||||
#define PBF 0x00000400 /* Pass Bad Frames Enable */
|
||||
#define PSF 0x00000800 /* Pass Short Frames Enable */
|
||||
#define RAF 0x00001000 /* Receive-All Mode */
|
||||
#define TE 0x00010000 /* Transmitter Enable */
|
||||
#define DTXPAD 0x00020000 /* Disable Automatic TX Padding */
|
||||
#define DTXCRC 0x00040000 /* Disable Automatic TX CRC Generation */
|
||||
#define DC 0x00080000 /* Deferral Check */
|
||||
#define BOLMT 0x00300000 /* Back-Off Limit */
|
||||
#define BOLMT_10 0x00000000 /* 10-bit range */
|
||||
#define BOLMT_8 0x00100000 /* 8-bit range */
|
||||
#define BOLMT_4 0x00200000 /* 4-bit range */
|
||||
#define BOLMT_1 0x00300000 /* 1-bit range */
|
||||
#define DRTY 0x00400000 /* Disable TX Retry On Collision */
|
||||
#define LCTRE 0x00800000 /* Enable TX Retry On Late Collision */
|
||||
#define RMII 0x01000000 /* RMII/MII* Mode */
|
||||
#define RMII_10 0x02000000 /* Speed Select for RMII Port (10MBit/100MBit*) */
|
||||
#define FDMODE 0x04000000 /* Duplex Mode Enable (Full/Half*) */
|
||||
#define LB 0x08000000 /* Internal Loopback Enable */
|
||||
#define DRO 0x10000000 /* Disable Receive Own Frames (Half-Duplex Mode) */
|
||||
|
||||
/* EMAC_STAADD Masks */
|
||||
|
||||
#define STABUSY 0x00000001 /* Initiate Station Mgt Reg Access / STA Busy Stat */
|
||||
#define STAOP 0x00000002 /* Station Management Operation Code (Write/Read*) */
|
||||
#define STADISPRE 0x00000004 /* Disable Preamble Generation */
|
||||
#define STAIE 0x00000008 /* Station Mgt. Transfer Done Interrupt Enable */
|
||||
#define REGAD 0x000007C0 /* STA Register Address */
|
||||
#define PHYAD 0x0000F800 /* PHY Device Address */
|
||||
|
||||
#define SET_REGAD(x) (((x)&0x1F)<< 6 ) /* Set STA Register Address */
|
||||
#define SET_PHYAD(x) (((x)&0x1F)<< 11 ) /* Set PHY Device Address */
|
||||
|
||||
/* EMAC_STADAT Mask */
|
||||
|
||||
#define STADATA 0x0000FFFF /* Station Management Data */
|
||||
|
||||
/* EMAC_FLC Masks */
|
||||
|
||||
#define FLCBUSY 0x00000001 /* Send Flow Ctrl Frame / Flow Ctrl Busy Status */
|
||||
#define FLCE 0x00000002 /* Flow Control Enable */
|
||||
#define PCF 0x00000004 /* Pass Control Frames */
|
||||
#define BKPRSEN 0x00000008 /* Enable Backpressure */
|
||||
#define FLCPAUSE 0xFFFF0000 /* Pause Time */
|
||||
|
||||
#define SET_FLCPAUSE(x) (((x)&0xFFFF)<< 16) /* Set Pause Time */
|
||||
|
||||
/* EMAC_WKUP_CTL Masks */
|
||||
|
||||
#define CAPWKFRM 0x00000001 /* Capture Wake-Up Frames */
|
||||
#define MPKE 0x00000002 /* Magic Packet Enable */
|
||||
#define RWKE 0x00000004 /* Remote Wake-Up Frame Enable */
|
||||
#define GUWKE 0x00000008 /* Global Unicast Wake Enable */
|
||||
#define MPKS 0x00000020 /* Magic Packet Received Status */
|
||||
#define RWKS 0x00000F00 /* Wake-Up Frame Received Status, Filters 3:0 */
|
||||
|
||||
/* EMAC_WKUP_FFCMD Masks */
|
||||
|
||||
#define WF0_E 0x00000001 /* Enable Wake-Up Filter 0 */
|
||||
#define WF0_T 0x00000008 /* Wake-Up Filter 0 Addr Type (Multicast/Unicast*) */
|
||||
#define WF1_E 0x00000100 /* Enable Wake-Up Filter 1 */
|
||||
#define WF1_T 0x00000800 /* Wake-Up Filter 1 Addr Type (Multicast/Unicast*) */
|
||||
#define WF2_E 0x00010000 /* Enable Wake-Up Filter 2 */
|
||||
#define WF2_T 0x00080000 /* Wake-Up Filter 2 Addr Type (Multicast/Unicast*) */
|
||||
#define WF3_E 0x01000000 /* Enable Wake-Up Filter 3 */
|
||||
#define WF3_T 0x08000000 /* Wake-Up Filter 3 Addr Type (Multicast/Unicast*) */
|
||||
|
||||
/* EMAC_WKUP_FFOFF Masks */
|
||||
|
||||
#define WF0_OFF 0x000000FF /* Wake-Up Filter 0 Pattern Offset */
|
||||
#define WF1_OFF 0x0000FF00 /* Wake-Up Filter 1 Pattern Offset */
|
||||
#define WF2_OFF 0x00FF0000 /* Wake-Up Filter 2 Pattern Offset */
|
||||
#define WF3_OFF 0xFF000000 /* Wake-Up Filter 3 Pattern Offset */
|
||||
|
||||
#define SET_WF0_OFF(x) (((x)&0xFF)<< 0 ) /* Set Wake-Up Filter 0 Byte Offset */
|
||||
#define SET_WF1_OFF(x) (((x)&0xFF)<< 8 ) /* Set Wake-Up Filter 1 Byte Offset */
|
||||
#define SET_WF2_OFF(x) (((x)&0xFF)<< 16 ) /* Set Wake-Up Filter 2 Byte Offset */
|
||||
#define SET_WF3_OFF(x) (((x)&0xFF)<< 24 ) /* Set Wake-Up Filter 3 Byte Offset */
|
||||
/* Set ALL Offsets */
|
||||
#define SET_WF_OFFS(x0,x1,x2,x3) (SET_WF0_OFF((x0))|SET_WF1_OFF((x1))|SET_WF2_OFF((x2))|SET_WF3_OFF((x3)))
|
||||
|
||||
/* EMAC_WKUP_FFCRC0 Masks */
|
||||
|
||||
#define WF0_CRC 0x0000FFFF /* Wake-Up Filter 0 Pattern CRC */
|
||||
#define WF1_CRC 0xFFFF0000 /* Wake-Up Filter 1 Pattern CRC */
|
||||
|
||||
#define SET_WF0_CRC(x) (((x)&0xFFFF)<< 0 ) /* Set Wake-Up Filter 0 Target CRC */
|
||||
#define SET_WF1_CRC(x) (((x)&0xFFFF)<< 16 ) /* Set Wake-Up Filter 1 Target CRC */
|
||||
|
||||
/* EMAC_WKUP_FFCRC1 Masks */
|
||||
|
||||
#define WF2_CRC 0x0000FFFF /* Wake-Up Filter 2 Pattern CRC */
|
||||
#define WF3_CRC 0xFFFF0000 /* Wake-Up Filter 3 Pattern CRC */
|
||||
|
||||
#define SET_WF2_CRC(x) (((x)&0xFFFF)<< 0 ) /* Set Wake-Up Filter 2 Target CRC */
|
||||
#define SET_WF3_CRC(x) (((x)&0xFFFF)<< 16 ) /* Set Wake-Up Filter 3 Target CRC */
|
||||
|
||||
/* EMAC_SYSCTL Masks */
|
||||
|
||||
#define PHYIE 0x00000001 /* PHY_INT Interrupt Enable */
|
||||
#define RXDWA 0x00000002 /* Receive Frame DMA Word Alignment (Odd/Even*) */
|
||||
#define RXCKS 0x00000004 /* Enable RX Frame TCP/UDP Checksum Computation */
|
||||
#define TXDWA 0x00000010 /* Transmit Frame DMA Word Alignment (Odd/Even*) */
|
||||
#define MDCDIV 0x00003F00 /* SCLK:MDC Clock Divisor [MDC=SCLK/(2*(N+1))] */
|
||||
|
||||
#define SET_MDCDIV(x) (((x)&0x3F)<< 8) /* Set MDC Clock Divisor */
|
||||
|
||||
/* EMAC_SYSTAT Masks */
|
||||
|
||||
#define PHYINT 0x00000001 /* PHY_INT Interrupt Status */
|
||||
#define MMCINT 0x00000002 /* MMC Counter Interrupt Status */
|
||||
#define RXFSINT 0x00000004 /* RX Frame-Status Interrupt Status */
|
||||
#define TXFSINT 0x00000008 /* TX Frame-Status Interrupt Status */
|
||||
#define WAKEDET 0x00000010 /* Wake-Up Detected Status */
|
||||
#define RXDMAERR 0x00000020 /* RX DMA Direction Error Status */
|
||||
#define TXDMAERR 0x00000040 /* TX DMA Direction Error Status */
|
||||
#define STMDONE 0x00000080 /* Station Mgt. Transfer Done Interrupt Status */
|
||||
|
||||
/* EMAC_RX_STAT, EMAC_RX_STKY, and EMAC_RX_IRQE Masks */
|
||||
|
||||
#define RX_FRLEN 0x000007FF /* Frame Length In Bytes */
|
||||
#define RX_COMP 0x00001000 /* RX Frame Complete */
|
||||
#define RX_OK 0x00002000 /* RX Frame Received With No Errors */
|
||||
#define RX_LONG 0x00004000 /* RX Frame Too Long Error */
|
||||
#define RX_ALIGN 0x00008000 /* RX Frame Alignment Error */
|
||||
#define RX_CRC 0x00010000 /* RX Frame CRC Error */
|
||||
#define RX_LEN 0x00020000 /* RX Frame Length Error */
|
||||
#define RX_FRAG 0x00040000 /* RX Frame Fragment Error */
|
||||
#define RX_ADDR 0x00080000 /* RX Frame Address Filter Failed Error */
|
||||
#define RX_DMAO 0x00100000 /* RX Frame DMA Overrun Error */
|
||||
#define RX_PHY 0x00200000 /* RX Frame PHY Error */
|
||||
#define RX_LATE 0x00400000 /* RX Frame Late Collision Error */
|
||||
#define RX_RANGE 0x00800000 /* RX Frame Length Field Out of Range Error */
|
||||
#define RX_MULTI 0x01000000 /* RX Multicast Frame Indicator */
|
||||
#define RX_BROAD 0x02000000 /* RX Broadcast Frame Indicator */
|
||||
#define RX_CTL 0x04000000 /* RX Control Frame Indicator */
|
||||
#define RX_UCTL 0x08000000 /* Unsupported RX Control Frame Indicator */
|
||||
#define RX_TYPE 0x10000000 /* RX Typed Frame Indicator */
|
||||
#define RX_VLAN1 0x20000000 /* RX VLAN1 Frame Indicator */
|
||||
#define RX_VLAN2 0x40000000 /* RX VLAN2 Frame Indicator */
|
||||
#define RX_ACCEPT 0x80000000 /* RX Frame Accepted Indicator */
|
||||
|
||||
/* EMAC_TX_STAT, EMAC_TX_STKY, and EMAC_TX_IRQE Masks */
|
||||
|
||||
#define TX_COMP 0x00000001 /* TX Frame Complete */
|
||||
#define TX_OK 0x00000002 /* TX Frame Sent With No Errors */
|
||||
#define TX_ECOLL 0x00000004 /* TX Frame Excessive Collision Error */
|
||||
#define TX_LATE 0x00000008 /* TX Frame Late Collision Error */
|
||||
#define TX_DMAU 0x00000010 /* TX Frame DMA Underrun Error (STAT) */
|
||||
#define TX_MACE 0x00000010 /* Internal MAC Error Detected (STKY and IRQE) */
|
||||
#define TX_EDEFER 0x00000020 /* TX Frame Excessive Deferral Error */
|
||||
#define TX_BROAD 0x00000040 /* TX Broadcast Frame Indicator */
|
||||
#define TX_MULTI 0x00000080 /* TX Multicast Frame Indicator */
|
||||
#define TX_CCNT 0x00000F00 /* TX Frame Collision Count */
|
||||
#define TX_DEFER 0x00001000 /* TX Frame Deferred Indicator */
|
||||
#define TX_CRS 0x00002000 /* TX Frame Carrier Sense Not Asserted Error */
|
||||
#define TX_LOSS 0x00004000 /* TX Frame Carrier Lost During TX Error */
|
||||
#define TX_RETRY 0x00008000 /* TX Frame Successful After Retry */
|
||||
#define TX_FRLEN 0x07FF0000 /* TX Frame Length (Bytes) */
|
||||
|
||||
/* EMAC_MMC_CTL Masks */
|
||||
#define RSTC 0x00000001 /* Reset All Counters */
|
||||
#define CROLL 0x00000002 /* Counter Roll-Over Enable */
|
||||
#define CCOR 0x00000004 /* Counter Clear-On-Read Mode Enable */
|
||||
#define MMCE 0x00000008 /* Enable MMC Counter Operation */
|
||||
|
||||
/* EMAC_MMC_RIRQS and EMAC_MMC_RIRQE Masks */
|
||||
#define RX_OK_CNT 0x00000001 /* RX Frames Received With No Errors */
|
||||
#define RX_FCS_CNT 0x00000002 /* RX Frames W/Frame Check Sequence Errors */
|
||||
#define RX_ALIGN_CNT 0x00000004 /* RX Frames With Alignment Errors */
|
||||
#define RX_OCTET_CNT 0x00000008 /* RX Octets Received OK */
|
||||
#define RX_LOST_CNT 0x00000010 /* RX Frames Lost Due To Internal MAC RX Error */
|
||||
#define RX_UNI_CNT 0x00000020 /* Unicast RX Frames Received OK */
|
||||
#define RX_MULTI_CNT 0x00000040 /* Multicast RX Frames Received OK */
|
||||
#define RX_BROAD_CNT 0x00000080 /* Broadcast RX Frames Received OK */
|
||||
#define RX_IRL_CNT 0x00000100 /* RX Frames With In-Range Length Errors */
|
||||
#define RX_ORL_CNT 0x00000200 /* RX Frames With Out-Of-Range Length Errors */
|
||||
#define RX_LONG_CNT 0x00000400 /* RX Frames With Frame Too Long Errors */
|
||||
#define RX_MACCTL_CNT 0x00000800 /* MAC Control RX Frames Received */
|
||||
#define RX_OPCODE_CTL 0x00001000 /* Unsupported Op-Code RX Frames Received */
|
||||
#define RX_PAUSE_CNT 0x00002000 /* PAUSEMAC Control RX Frames Received */
|
||||
#define RX_ALLF_CNT 0x00004000 /* All RX Frames Received */
|
||||
#define RX_ALLO_CNT 0x00008000 /* All RX Octets Received */
|
||||
#define RX_TYPED_CNT 0x00010000 /* Typed RX Frames Received */
|
||||
#define RX_SHORT_CNT 0x00020000 /* RX Frame Fragments (< 64 Bytes) Received */
|
||||
#define RX_EQ64_CNT 0x00040000 /* 64-Byte RX Frames Received */
|
||||
#define RX_LT128_CNT 0x00080000 /* 65-127-Byte RX Frames Received */
|
||||
#define RX_LT256_CNT 0x00100000 /* 128-255-Byte RX Frames Received */
|
||||
#define RX_LT512_CNT 0x00200000 /* 256-511-Byte RX Frames Received */
|
||||
#define RX_LT1024_CNT 0x00400000 /* 512-1023-Byte RX Frames Received */
|
||||
#define RX_GE1024_CNT 0x00800000 /* 1024-Max-Byte RX Frames Received */
|
||||
|
||||
/* EMAC_MMC_TIRQS and EMAC_MMC_TIRQE Masks */
|
||||
|
||||
#define TX_OK_CNT 0x00000001 /* TX Frames Sent OK */
|
||||
#define TX_SCOLL_CNT 0x00000002 /* TX Frames With Single Collisions */
|
||||
#define TX_MCOLL_CNT 0x00000004 /* TX Frames With Multiple Collisions */
|
||||
#define TX_OCTET_CNT 0x00000008 /* TX Octets Sent OK */
|
||||
#define TX_DEFER_CNT 0x00000010 /* TX Frames With Deferred Transmission */
|
||||
#define TX_LATE_CNT 0x00000020 /* TX Frames With Late Collisions */
|
||||
#define TX_ABORTC_CNT 0x00000040 /* TX Frames Aborted Due To Excess Collisions */
|
||||
#define TX_LOST_CNT 0x00000080 /* TX Frames Lost Due To Internal MAC TX Error */
|
||||
#define TX_CRS_CNT 0x00000100 /* TX Frames With Carrier Sense Errors */
|
||||
#define TX_UNI_CNT 0x00000200 /* Unicast TX Frames Sent */
|
||||
#define TX_MULTI_CNT 0x00000400 /* Multicast TX Frames Sent */
|
||||
#define TX_BROAD_CNT 0x00000800 /* Broadcast TX Frames Sent */
|
||||
#define TX_EXDEF_CTL 0x00001000 /* TX Frames With Excessive Deferral */
|
||||
#define TX_MACCTL_CNT 0x00002000 /* MAC Control TX Frames Sent */
|
||||
#define TX_ALLF_CNT 0x00004000 /* All TX Frames Sent */
|
||||
#define TX_ALLO_CNT 0x00008000 /* All TX Octets Sent */
|
||||
#define TX_EQ64_CNT 0x00010000 /* 64-Byte TX Frames Sent */
|
||||
#define TX_LT128_CNT 0x00020000 /* 65-127-Byte TX Frames Sent */
|
||||
#define TX_LT256_CNT 0x00040000 /* 128-255-Byte TX Frames Sent */
|
||||
#define TX_LT512_CNT 0x00080000 /* 256-511-Byte TX Frames Sent */
|
||||
#define TX_LT1024_CNT 0x00100000 /* 512-1023-Byte TX Frames Sent */
|
||||
#define TX_GE1024_CNT 0x00200000 /* 1024-Max-Byte TX Frames Sent */
|
||||
#define TX_ABORT_CNT 0x00400000 /* TX Frames Aborted */
|
||||
|
||||
/* SDH Registers */
|
||||
|
||||
#define SDH_PWR_CTL 0xFFC03900 /* SDH Power Control */
|
||||
#define SDH_CLK_CTL 0xFFC03904 /* SDH Clock Control */
|
||||
#define SDH_ARGUMENT 0xFFC03908 /* SDH Argument */
|
||||
#define SDH_COMMAND 0xFFC0390C /* SDH Command */
|
||||
#define SDH_RESP_CMD 0xFFC03910 /* SDH Response Command */
|
||||
#define SDH_RESPONSE0 0xFFC03914 /* SDH Response0 */
|
||||
#define SDH_RESPONSE1 0xFFC03918 /* SDH Response1 */
|
||||
#define SDH_RESPONSE2 0xFFC0391C /* SDH Response2 */
|
||||
#define SDH_RESPONSE3 0xFFC03920 /* SDH Response3 */
|
||||
#define SDH_DATA_TIMER 0xFFC03924 /* SDH Data Timer */
|
||||
#define SDH_DATA_LGTH 0xFFC03928 /* SDH Data Length */
|
||||
#define SDH_DATA_CTL 0xFFC0392C /* SDH Data Control */
|
||||
#define SDH_DATA_CNT 0xFFC03930 /* SDH Data Counter */
|
||||
#define SDH_STATUS 0xFFC03934 /* SDH Status */
|
||||
#define SDH_STATUS_CLR 0xFFC03938 /* SDH Status Clear */
|
||||
#define SDH_MASK0 0xFFC0393C /* SDH Interrupt0 Mask */
|
||||
#define SDH_MASK1 0xFFC03940 /* SDH Interrupt1 Mask */
|
||||
#define SDH_FIFO_CNT 0xFFC03948 /* SDH FIFO Counter */
|
||||
#define SDH_FIFO 0xFFC03980 /* SDH Data FIFO */
|
||||
#define SDH_E_STATUS 0xFFC039C0 /* SDH Exception Status */
|
||||
#define SDH_E_MASK 0xFFC039C4 /* SDH Exception Mask */
|
||||
#define SDH_CFG 0xFFC039C8 /* SDH Configuration */
|
||||
#define SDH_RD_WAIT_EN 0xFFC039CC /* SDH Read Wait Enable */
|
||||
#define SDH_PID0 0xFFC039D0 /* SDH Peripheral Identification0 */
|
||||
#define SDH_PID1 0xFFC039D4 /* SDH Peripheral Identification1 */
|
||||
#define SDH_PID2 0xFFC039D8 /* SDH Peripheral Identification2 */
|
||||
#define SDH_PID3 0xFFC039DC /* SDH Peripheral Identification3 */
|
||||
#define SDH_PID4 0xFFC039E0 /* SDH Peripheral Identification4 */
|
||||
#define SDH_PID5 0xFFC039E4 /* SDH Peripheral Identification5 */
|
||||
#define SDH_PID6 0xFFC039E8 /* SDH Peripheral Identification6 */
|
||||
#define SDH_PID7 0xFFC039EC /* SDH Peripheral Identification7 */
|
||||
|
||||
/* Removable Storage Interface Registers */
|
||||
|
||||
#define RSI_PWR_CONTROL 0xFFC03800 /* RSI Power Control Register */
|
||||
#define RSI_CLK_CONTROL 0xFFC03804 /* RSI Clock Control Register */
|
||||
#define RSI_ARGUMENT 0xFFC03808 /* RSI Argument Register */
|
||||
#define RSI_COMMAND 0xFFC0380C /* RSI Command Register */
|
||||
#define RSI_RESP_CMD 0xFFC03810 /* RSI Response Command Register */
|
||||
#define RSI_RESPONSE0 0xFFC03814 /* RSI Response Register */
|
||||
#define RSI_RESPONSE1 0xFFC03818 /* RSI Response Register */
|
||||
#define RSI_RESPONSE2 0xFFC0381C /* RSI Response Register */
|
||||
#define RSI_RESPONSE3 0xFFC03820 /* RSI Response Register */
|
||||
#define RSI_DATA_TIMER 0xFFC03824 /* RSI Data Timer Register */
|
||||
#define RSI_DATA_LGTH 0xFFC03828 /* RSI Data Length Register */
|
||||
#define RSI_DATA_CONTROL 0xFFC0382C /* RSI Data Control Register */
|
||||
#define RSI_DATA_CNT 0xFFC03830 /* RSI Data Counter Register */
|
||||
#define RSI_STATUS 0xFFC03834 /* RSI Status Register */
|
||||
#define RSI_STATUSCL 0xFFC03838 /* RSI Status Clear Register */
|
||||
#define RSI_MASK0 0xFFC0383C /* RSI Interrupt 0 Mask Register */
|
||||
#define RSI_MASK1 0xFFC03840 /* RSI Interrupt 1 Mask Register */
|
||||
#define RSI_FIFO_CNT 0xFFC03848 /* RSI FIFO Counter Register */
|
||||
#define RSI_CEATA_CONTROL 0xFFC0384C /* RSI CEATA Register */
|
||||
#define RSI_FIFO 0xFFC03880 /* RSI Data FIFO Register */
|
||||
#define RSI_ESTAT 0xFFC038C0 /* RSI Exception Status Register */
|
||||
#define RSI_EMASK 0xFFC038C4 /* RSI Exception Mask Register */
|
||||
#define RSI_CONFIG 0xFFC038C8 /* RSI Configuration Register */
|
||||
#define RSI_RD_WAIT_EN 0xFFC038CC /* RSI Read Wait Enable Register */
|
||||
#define RSI_PID0 0xFFC03FE0 /* RSI Peripheral ID Register 0 */
|
||||
#define RSI_PID1 0xFFC03FE4 /* RSI Peripheral ID Register 1 */
|
||||
#define RSI_PID2 0xFFC03FE8 /* RSI Peripheral ID Register 2 */
|
||||
#define RSI_PID3 0xFFC03FEC /* RSI Peripheral ID Register 3 */
|
||||
#define RSI_PID4 0xFFC03FF0 /* RSI Peripheral ID Register 4 */
|
||||
#define RSI_PID5 0xFFC03FF4 /* RSI Peripheral ID Register 5 */
|
||||
#define RSI_PID6 0xFFC03FF8 /* RSI Peripheral ID Register 6 */
|
||||
#define RSI_PID7 0xFFC03FFC /* RSI Peripheral ID Register 7 */
|
||||
|
||||
#endif /* _DEF_BF516_H */
|
||||
|
|
@ -0,0 +1,516 @@
|
|||
/*
|
||||
* File: include/asm-blackfin/mach-bf518/defBF518.h
|
||||
* Based on:
|
||||
* Author:
|
||||
*
|
||||
* Created:
|
||||
* Description:
|
||||
*
|
||||
* Rev:
|
||||
*
|
||||
* Modified:
|
||||
*
|
||||
* Bugs: Enter bugs at http://blackfin.uclinux.org/
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2, or (at your option)
|
||||
* any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; see the file COPYING.
|
||||
* If not, write to the Free Software Foundation,
|
||||
* 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
|
||||
*/
|
||||
|
||||
#ifndef _DEF_BF518_H
|
||||
#define _DEF_BF518_H
|
||||
|
||||
/* Include all Core registers and bit definitions */
|
||||
#include <asm/def_LPBlackfin.h>
|
||||
|
||||
/* SYSTEM & MMR ADDRESS DEFINITIONS FOR ADSP-BF518 */
|
||||
|
||||
/* Include defBF51x_base.h for the set of #defines that are common to all ADSP-BF51x processors */
|
||||
#include "defBF51x_base.h"
|
||||
|
||||
/* The following are the #defines needed by ADSP-BF518 that are not in the common header */
|
||||
/* 10/100 Ethernet Controller (0xFFC03000 - 0xFFC031FF) */
|
||||
|
||||
#define EMAC_OPMODE 0xFFC03000 /* Operating Mode Register */
|
||||
#define EMAC_ADDRLO 0xFFC03004 /* Address Low (32 LSBs) Register */
|
||||
#define EMAC_ADDRHI 0xFFC03008 /* Address High (16 MSBs) Register */
|
||||
#define EMAC_HASHLO 0xFFC0300C /* Multicast Hash Table Low (Bins 31-0) Register */
|
||||
#define EMAC_HASHHI 0xFFC03010 /* Multicast Hash Table High (Bins 63-32) Register */
|
||||
#define EMAC_STAADD 0xFFC03014 /* Station Management Address Register */
|
||||
#define EMAC_STADAT 0xFFC03018 /* Station Management Data Register */
|
||||
#define EMAC_FLC 0xFFC0301C /* Flow Control Register */
|
||||
#define EMAC_VLAN1 0xFFC03020 /* VLAN1 Tag Register */
|
||||
#define EMAC_VLAN2 0xFFC03024 /* VLAN2 Tag Register */
|
||||
#define EMAC_WKUP_CTL 0xFFC0302C /* Wake-Up Control/Status Register */
|
||||
#define EMAC_WKUP_FFMSK0 0xFFC03030 /* Wake-Up Frame Filter 0 Byte Mask Register */
|
||||
#define EMAC_WKUP_FFMSK1 0xFFC03034 /* Wake-Up Frame Filter 1 Byte Mask Register */
|
||||
#define EMAC_WKUP_FFMSK2 0xFFC03038 /* Wake-Up Frame Filter 2 Byte Mask Register */
|
||||
#define EMAC_WKUP_FFMSK3 0xFFC0303C /* Wake-Up Frame Filter 3 Byte Mask Register */
|
||||
#define EMAC_WKUP_FFCMD 0xFFC03040 /* Wake-Up Frame Filter Commands Register */
|
||||
#define EMAC_WKUP_FFOFF 0xFFC03044 /* Wake-Up Frame Filter Offsets Register */
|
||||
#define EMAC_WKUP_FFCRC0 0xFFC03048 /* Wake-Up Frame Filter 0,1 CRC-16 Register */
|
||||
#define EMAC_WKUP_FFCRC1 0xFFC0304C /* Wake-Up Frame Filter 2,3 CRC-16 Register */
|
||||
|
||||
#define EMAC_SYSCTL 0xFFC03060 /* EMAC System Control Register */
|
||||
#define EMAC_SYSTAT 0xFFC03064 /* EMAC System Status Register */
|
||||
#define EMAC_RX_STAT 0xFFC03068 /* RX Current Frame Status Register */
|
||||
#define EMAC_RX_STKY 0xFFC0306C /* RX Sticky Frame Status Register */
|
||||
#define EMAC_RX_IRQE 0xFFC03070 /* RX Frame Status Interrupt Enables Register */
|
||||
#define EMAC_TX_STAT 0xFFC03074 /* TX Current Frame Status Register */
|
||||
#define EMAC_TX_STKY 0xFFC03078 /* TX Sticky Frame Status Register */
|
||||
#define EMAC_TX_IRQE 0xFFC0307C /* TX Frame Status Interrupt Enables Register */
|
||||
|
||||
#define EMAC_MMC_CTL 0xFFC03080 /* MMC Counter Control Register */
|
||||
#define EMAC_MMC_RIRQS 0xFFC03084 /* MMC RX Interrupt Status Register */
|
||||
#define EMAC_MMC_RIRQE 0xFFC03088 /* MMC RX Interrupt Enables Register */
|
||||
#define EMAC_MMC_TIRQS 0xFFC0308C /* MMC TX Interrupt Status Register */
|
||||
#define EMAC_MMC_TIRQE 0xFFC03090 /* MMC TX Interrupt Enables Register */
|
||||
|
||||
#define EMAC_RXC_OK 0xFFC03100 /* RX Frame Successful Count */
|
||||
#define EMAC_RXC_FCS 0xFFC03104 /* RX Frame FCS Failure Count */
|
||||
#define EMAC_RXC_ALIGN 0xFFC03108 /* RX Alignment Error Count */
|
||||
#define EMAC_RXC_OCTET 0xFFC0310C /* RX Octets Successfully Received Count */
|
||||
#define EMAC_RXC_DMAOVF 0xFFC03110 /* Internal MAC Sublayer Error RX Frame Count */
|
||||
#define EMAC_RXC_UNICST 0xFFC03114 /* Unicast RX Frame Count */
|
||||
#define EMAC_RXC_MULTI 0xFFC03118 /* Multicast RX Frame Count */
|
||||
#define EMAC_RXC_BROAD 0xFFC0311C /* Broadcast RX Frame Count */
|
||||
#define EMAC_RXC_LNERRI 0xFFC03120 /* RX Frame In Range Error Count */
|
||||
#define EMAC_RXC_LNERRO 0xFFC03124 /* RX Frame Out Of Range Error Count */
|
||||
#define EMAC_RXC_LONG 0xFFC03128 /* RX Frame Too Long Count */
|
||||
#define EMAC_RXC_MACCTL 0xFFC0312C /* MAC Control RX Frame Count */
|
||||
#define EMAC_RXC_OPCODE 0xFFC03130 /* Unsupported Op-Code RX Frame Count */
|
||||
#define EMAC_RXC_PAUSE 0xFFC03134 /* MAC Control Pause RX Frame Count */
|
||||
#define EMAC_RXC_ALLFRM 0xFFC03138 /* Overall RX Frame Count */
|
||||
#define EMAC_RXC_ALLOCT 0xFFC0313C /* Overall RX Octet Count */
|
||||
#define EMAC_RXC_TYPED 0xFFC03140 /* Type/Length Consistent RX Frame Count */
|
||||
#define EMAC_RXC_SHORT 0xFFC03144 /* RX Frame Fragment Count - Byte Count x < 64 */
|
||||
#define EMAC_RXC_EQ64 0xFFC03148 /* Good RX Frame Count - Byte Count x = 64 */
|
||||
#define EMAC_RXC_LT128 0xFFC0314C /* Good RX Frame Count - Byte Count 64 < x < 128 */
|
||||
#define EMAC_RXC_LT256 0xFFC03150 /* Good RX Frame Count - Byte Count 128 <= x < 256 */
|
||||
#define EMAC_RXC_LT512 0xFFC03154 /* Good RX Frame Count - Byte Count 256 <= x < 512 */
|
||||
#define EMAC_RXC_LT1024 0xFFC03158 /* Good RX Frame Count - Byte Count 512 <= x < 1024 */
|
||||
#define EMAC_RXC_GE1024 0xFFC0315C /* Good RX Frame Count - Byte Count x >= 1024 */
|
||||
|
||||
#define EMAC_TXC_OK 0xFFC03180 /* TX Frame Successful Count */
|
||||
#define EMAC_TXC_1COL 0xFFC03184 /* TX Frames Successful After Single Collision Count */
|
||||
#define EMAC_TXC_GT1COL 0xFFC03188 /* TX Frames Successful After Multiple Collisions Count */
|
||||
#define EMAC_TXC_OCTET 0xFFC0318C /* TX Octets Successfully Received Count */
|
||||
#define EMAC_TXC_DEFER 0xFFC03190 /* TX Frame Delayed Due To Busy Count */
|
||||
#define EMAC_TXC_LATECL 0xFFC03194 /* Late TX Collisions Count */
|
||||
#define EMAC_TXC_XS_COL 0xFFC03198 /* TX Frame Failed Due To Excessive Collisions Count */
|
||||
#define EMAC_TXC_DMAUND 0xFFC0319C /* Internal MAC Sublayer Error TX Frame Count */
|
||||
#define EMAC_TXC_CRSERR 0xFFC031A0 /* Carrier Sense Deasserted During TX Frame Count */
|
||||
#define EMAC_TXC_UNICST 0xFFC031A4 /* Unicast TX Frame Count */
|
||||
#define EMAC_TXC_MULTI 0xFFC031A8 /* Multicast TX Frame Count */
|
||||
#define EMAC_TXC_BROAD 0xFFC031AC /* Broadcast TX Frame Count */
|
||||
#define EMAC_TXC_XS_DFR 0xFFC031B0 /* TX Frames With Excessive Deferral Count */
|
||||
#define EMAC_TXC_MACCTL 0xFFC031B4 /* MAC Control TX Frame Count */
|
||||
#define EMAC_TXC_ALLFRM 0xFFC031B8 /* Overall TX Frame Count */
|
||||
#define EMAC_TXC_ALLOCT 0xFFC031BC /* Overall TX Octet Count */
|
||||
#define EMAC_TXC_EQ64 0xFFC031C0 /* Good TX Frame Count - Byte Count x = 64 */
|
||||
#define EMAC_TXC_LT128 0xFFC031C4 /* Good TX Frame Count - Byte Count 64 < x < 128 */
|
||||
#define EMAC_TXC_LT256 0xFFC031C8 /* Good TX Frame Count - Byte Count 128 <= x < 256 */
|
||||
#define EMAC_TXC_LT512 0xFFC031CC /* Good TX Frame Count - Byte Count 256 <= x < 512 */
|
||||
#define EMAC_TXC_LT1024 0xFFC031D0 /* Good TX Frame Count - Byte Count 512 <= x < 1024 */
|
||||
#define EMAC_TXC_GE1024 0xFFC031D4 /* Good TX Frame Count - Byte Count x >= 1024 */
|
||||
#define EMAC_TXC_ABORT 0xFFC031D8 /* Total TX Frames Aborted Count */
|
||||
|
||||
/* Listing for IEEE-Supported Count Registers */
|
||||
|
||||
#define FramesReceivedOK EMAC_RXC_OK /* RX Frame Successful Count */
|
||||
#define FrameCheckSequenceErrors EMAC_RXC_FCS /* RX Frame FCS Failure Count */
|
||||
#define AlignmentErrors EMAC_RXC_ALIGN /* RX Alignment Error Count */
|
||||
#define OctetsReceivedOK EMAC_RXC_OCTET /* RX Octets Successfully Received Count */
|
||||
#define FramesLostDueToIntMACRcvError EMAC_RXC_DMAOVF /* Internal MAC Sublayer Error RX Frame Count */
|
||||
#define UnicastFramesReceivedOK EMAC_RXC_UNICST /* Unicast RX Frame Count */
|
||||
#define MulticastFramesReceivedOK EMAC_RXC_MULTI /* Multicast RX Frame Count */
|
||||
#define BroadcastFramesReceivedOK EMAC_RXC_BROAD /* Broadcast RX Frame Count */
|
||||
#define InRangeLengthErrors EMAC_RXC_LNERRI /* RX Frame In Range Error Count */
|
||||
#define OutOfRangeLengthField EMAC_RXC_LNERRO /* RX Frame Out Of Range Error Count */
|
||||
#define FrameTooLongErrors EMAC_RXC_LONG /* RX Frame Too Long Count */
|
||||
#define MACControlFramesReceived EMAC_RXC_MACCTL /* MAC Control RX Frame Count */
|
||||
#define UnsupportedOpcodesReceived EMAC_RXC_OPCODE /* Unsupported Op-Code RX Frame Count */
|
||||
#define PAUSEMACCtrlFramesReceived EMAC_RXC_PAUSE /* MAC Control Pause RX Frame Count */
|
||||
#define FramesReceivedAll EMAC_RXC_ALLFRM /* Overall RX Frame Count */
|
||||
#define OctetsReceivedAll EMAC_RXC_ALLOCT /* Overall RX Octet Count */
|
||||
#define TypedFramesReceived EMAC_RXC_TYPED /* Type/Length Consistent RX Frame Count */
|
||||
#define FramesLenLt64Received EMAC_RXC_SHORT /* RX Frame Fragment Count - Byte Count x < 64 */
|
||||
#define FramesLenEq64Received EMAC_RXC_EQ64 /* Good RX Frame Count - Byte Count x = 64 */
|
||||
#define FramesLen65_127Received EMAC_RXC_LT128 /* Good RX Frame Count - Byte Count 64 < x < 128 */
|
||||
#define FramesLen128_255Received EMAC_RXC_LT256 /* Good RX Frame Count - Byte Count 128 <= x < 256 */
|
||||
#define FramesLen256_511Received EMAC_RXC_LT512 /* Good RX Frame Count - Byte Count 256 <= x < 512 */
|
||||
#define FramesLen512_1023Received EMAC_RXC_LT1024 /* Good RX Frame Count - Byte Count 512 <= x < 1024 */
|
||||
#define FramesLen1024_MaxReceived EMAC_RXC_GE1024 /* Good RX Frame Count - Byte Count x >= 1024 */
|
||||
|
||||
#define FramesTransmittedOK EMAC_TXC_OK /* TX Frame Successful Count */
|
||||
#define SingleCollisionFrames EMAC_TXC_1COL /* TX Frames Successful After Single Collision Count */
|
||||
#define MultipleCollisionFrames EMAC_TXC_GT1COL /* TX Frames Successful After Multiple Collisions Count */
|
||||
#define OctetsTransmittedOK EMAC_TXC_OCTET /* TX Octets Successfully Received Count */
|
||||
#define FramesWithDeferredXmissions EMAC_TXC_DEFER /* TX Frame Delayed Due To Busy Count */
|
||||
#define LateCollisions EMAC_TXC_LATECL /* Late TX Collisions Count */
|
||||
#define FramesAbortedDueToXSColls EMAC_TXC_XS_COL /* TX Frame Failed Due To Excessive Collisions Count */
|
||||
#define FramesLostDueToIntMacXmitError EMAC_TXC_DMAUND /* Internal MAC Sublayer Error TX Frame Count */
|
||||
#define CarrierSenseErrors EMAC_TXC_CRSERR /* Carrier Sense Deasserted During TX Frame Count */
|
||||
#define UnicastFramesXmittedOK EMAC_TXC_UNICST /* Unicast TX Frame Count */
|
||||
#define MulticastFramesXmittedOK EMAC_TXC_MULTI /* Multicast TX Frame Count */
|
||||
#define BroadcastFramesXmittedOK EMAC_TXC_BROAD /* Broadcast TX Frame Count */
|
||||
#define FramesWithExcessiveDeferral EMAC_TXC_XS_DFR /* TX Frames With Excessive Deferral Count */
|
||||
#define MACControlFramesTransmitted EMAC_TXC_MACCTL /* MAC Control TX Frame Count */
|
||||
#define FramesTransmittedAll EMAC_TXC_ALLFRM /* Overall TX Frame Count */
|
||||
#define OctetsTransmittedAll EMAC_TXC_ALLOCT /* Overall TX Octet Count */
|
||||
#define FramesLenEq64Transmitted EMAC_TXC_EQ64 /* Good TX Frame Count - Byte Count x = 64 */
|
||||
#define FramesLen65_127Transmitted EMAC_TXC_LT128 /* Good TX Frame Count - Byte Count 64 < x < 128 */
|
||||
#define FramesLen128_255Transmitted EMAC_TXC_LT256 /* Good TX Frame Count - Byte Count 128 <= x < 256 */
|
||||
#define FramesLen256_511Transmitted EMAC_TXC_LT512 /* Good TX Frame Count - Byte Count 256 <= x < 512 */
|
||||
#define FramesLen512_1023Transmitted EMAC_TXC_LT1024 /* Good TX Frame Count - Byte Count 512 <= x < 1024 */
|
||||
#define FramesLen1024_MaxTransmitted EMAC_TXC_GE1024 /* Good TX Frame Count - Byte Count x >= 1024 */
|
||||
#define TxAbortedFrames EMAC_TXC_ABORT /* Total TX Frames Aborted Count */
|
||||
|
||||
/***********************************************************************************
|
||||
** System MMR Register Bits And Macros
|
||||
**
|
||||
** Disclaimer: All macros are intended to make C and Assembly code more readable.
|
||||
** Use these macros carefully, as any that do left shifts for field
|
||||
** depositing will result in the lower order bits being destroyed. Any
|
||||
** macro that shifts left to properly position the bit-field should be
|
||||
** used as part of an OR to initialize a register and NOT as a dynamic
|
||||
** modifier UNLESS the lower order bits are saved and ORed back in when
|
||||
** the macro is used.
|
||||
*************************************************************************************/
|
||||
|
||||
/************************ ETHERNET 10/100 CONTROLLER MASKS ************************/
|
||||
|
||||
/* EMAC_OPMODE Masks */
|
||||
|
||||
#define RE 0x00000001 /* Receiver Enable */
|
||||
#define ASTP 0x00000002 /* Enable Automatic Pad Stripping On RX Frames */
|
||||
#define HU 0x00000010 /* Hash Filter Unicast Address */
|
||||
#define HM 0x00000020 /* Hash Filter Multicast Address */
|
||||
#define PAM 0x00000040 /* Pass-All-Multicast Mode Enable */
|
||||
#define PR 0x00000080 /* Promiscuous Mode Enable */
|
||||
#define IFE 0x00000100 /* Inverse Filtering Enable */
|
||||
#define DBF 0x00000200 /* Disable Broadcast Frame Reception */
|
||||
#define PBF 0x00000400 /* Pass Bad Frames Enable */
|
||||
#define PSF 0x00000800 /* Pass Short Frames Enable */
|
||||
#define RAF 0x00001000 /* Receive-All Mode */
|
||||
#define TE 0x00010000 /* Transmitter Enable */
|
||||
#define DTXPAD 0x00020000 /* Disable Automatic TX Padding */
|
||||
#define DTXCRC 0x00040000 /* Disable Automatic TX CRC Generation */
|
||||
#define DC 0x00080000 /* Deferral Check */
|
||||
#define BOLMT 0x00300000 /* Back-Off Limit */
|
||||
#define BOLMT_10 0x00000000 /* 10-bit range */
|
||||
#define BOLMT_8 0x00100000 /* 8-bit range */
|
||||
#define BOLMT_4 0x00200000 /* 4-bit range */
|
||||
#define BOLMT_1 0x00300000 /* 1-bit range */
|
||||
#define DRTY 0x00400000 /* Disable TX Retry On Collision */
|
||||
#define LCTRE 0x00800000 /* Enable TX Retry On Late Collision */
|
||||
#define RMII 0x01000000 /* RMII/MII* Mode */
|
||||
#define RMII_10 0x02000000 /* Speed Select for RMII Port (10MBit/100MBit*) */
|
||||
#define FDMODE 0x04000000 /* Duplex Mode Enable (Full/Half*) */
|
||||
#define LB 0x08000000 /* Internal Loopback Enable */
|
||||
#define DRO 0x10000000 /* Disable Receive Own Frames (Half-Duplex Mode) */
|
||||
|
||||
/* EMAC_STAADD Masks */
|
||||
|
||||
#define STABUSY 0x00000001 /* Initiate Station Mgt Reg Access / STA Busy Stat */
|
||||
#define STAOP 0x00000002 /* Station Management Operation Code (Write/Read*) */
|
||||
#define STADISPRE 0x00000004 /* Disable Preamble Generation */
|
||||
#define STAIE 0x00000008 /* Station Mgt. Transfer Done Interrupt Enable */
|
||||
#define REGAD 0x000007C0 /* STA Register Address */
|
||||
#define PHYAD 0x0000F800 /* PHY Device Address */
|
||||
|
||||
#define SET_REGAD(x) (((x)&0x1F)<< 6 ) /* Set STA Register Address */
|
||||
#define SET_PHYAD(x) (((x)&0x1F)<< 11 ) /* Set PHY Device Address */
|
||||
|
||||
/* EMAC_STADAT Mask */
|
||||
|
||||
#define STADATA 0x0000FFFF /* Station Management Data */
|
||||
|
||||
/* EMAC_FLC Masks */
|
||||
|
||||
#define FLCBUSY 0x00000001 /* Send Flow Ctrl Frame / Flow Ctrl Busy Status */
|
||||
#define FLCE 0x00000002 /* Flow Control Enable */
|
||||
#define PCF 0x00000004 /* Pass Control Frames */
|
||||
#define BKPRSEN 0x00000008 /* Enable Backpressure */
|
||||
#define FLCPAUSE 0xFFFF0000 /* Pause Time */
|
||||
|
||||
#define SET_FLCPAUSE(x) (((x)&0xFFFF)<< 16) /* Set Pause Time */
|
||||
|
||||
/* EMAC_WKUP_CTL Masks */
|
||||
|
||||
#define CAPWKFRM 0x00000001 /* Capture Wake-Up Frames */
|
||||
#define MPKE 0x00000002 /* Magic Packet Enable */
|
||||
#define RWKE 0x00000004 /* Remote Wake-Up Frame Enable */
|
||||
#define GUWKE 0x00000008 /* Global Unicast Wake Enable */
|
||||
#define MPKS 0x00000020 /* Magic Packet Received Status */
|
||||
#define RWKS 0x00000F00 /* Wake-Up Frame Received Status, Filters 3:0 */
|
||||
|
||||
/* EMAC_WKUP_FFCMD Masks */
|
||||
|
||||
#define WF0_E 0x00000001 /* Enable Wake-Up Filter 0 */
|
||||
#define WF0_T 0x00000008 /* Wake-Up Filter 0 Addr Type (Multicast/Unicast*) */
|
||||
#define WF1_E 0x00000100 /* Enable Wake-Up Filter 1 */
|
||||
#define WF1_T 0x00000800 /* Wake-Up Filter 1 Addr Type (Multicast/Unicast*) */
|
||||
#define WF2_E 0x00010000 /* Enable Wake-Up Filter 2 */
|
||||
#define WF2_T 0x00080000 /* Wake-Up Filter 2 Addr Type (Multicast/Unicast*) */
|
||||
#define WF3_E 0x01000000 /* Enable Wake-Up Filter 3 */
|
||||
#define WF3_T 0x08000000 /* Wake-Up Filter 3 Addr Type (Multicast/Unicast*) */
|
||||
|
||||
/* EMAC_WKUP_FFOFF Masks */
|
||||
|
||||
#define WF0_OFF 0x000000FF /* Wake-Up Filter 0 Pattern Offset */
|
||||
#define WF1_OFF 0x0000FF00 /* Wake-Up Filter 1 Pattern Offset */
|
||||
#define WF2_OFF 0x00FF0000 /* Wake-Up Filter 2 Pattern Offset */
|
||||
#define WF3_OFF 0xFF000000 /* Wake-Up Filter 3 Pattern Offset */
|
||||
|
||||
#define SET_WF0_OFF(x) (((x)&0xFF)<< 0 ) /* Set Wake-Up Filter 0 Byte Offset */
|
||||
#define SET_WF1_OFF(x) (((x)&0xFF)<< 8 ) /* Set Wake-Up Filter 1 Byte Offset */
|
||||
#define SET_WF2_OFF(x) (((x)&0xFF)<< 16 ) /* Set Wake-Up Filter 2 Byte Offset */
|
||||
#define SET_WF3_OFF(x) (((x)&0xFF)<< 24 ) /* Set Wake-Up Filter 3 Byte Offset */
|
||||
/* Set ALL Offsets */
|
||||
#define SET_WF_OFFS(x0,x1,x2,x3) (SET_WF0_OFF((x0))|SET_WF1_OFF((x1))|SET_WF2_OFF((x2))|SET_WF3_OFF((x3)))
|
||||
|
||||
/* EMAC_WKUP_FFCRC0 Masks */
|
||||
|
||||
#define WF0_CRC 0x0000FFFF /* Wake-Up Filter 0 Pattern CRC */
|
||||
#define WF1_CRC 0xFFFF0000 /* Wake-Up Filter 1 Pattern CRC */
|
||||
|
||||
#define SET_WF0_CRC(x) (((x)&0xFFFF)<< 0 ) /* Set Wake-Up Filter 0 Target CRC */
|
||||
#define SET_WF1_CRC(x) (((x)&0xFFFF)<< 16 ) /* Set Wake-Up Filter 1 Target CRC */
|
||||
|
||||
/* EMAC_WKUP_FFCRC1 Masks */
|
||||
|
||||
#define WF2_CRC 0x0000FFFF /* Wake-Up Filter 2 Pattern CRC */
|
||||
#define WF3_CRC 0xFFFF0000 /* Wake-Up Filter 3 Pattern CRC */
|
||||
|
||||
#define SET_WF2_CRC(x) (((x)&0xFFFF)<< 0 ) /* Set Wake-Up Filter 2 Target CRC */
|
||||
#define SET_WF3_CRC(x) (((x)&0xFFFF)<< 16 ) /* Set Wake-Up Filter 3 Target CRC */
|
||||
|
||||
/* EMAC_SYSCTL Masks */
|
||||
|
||||
#define PHYIE 0x00000001 /* PHY_INT Interrupt Enable */
|
||||
#define RXDWA 0x00000002 /* Receive Frame DMA Word Alignment (Odd/Even*) */
|
||||
#define RXCKS 0x00000004 /* Enable RX Frame TCP/UDP Checksum Computation */
|
||||
#define TXDWA 0x00000010 /* Transmit Frame DMA Word Alignment (Odd/Even*) */
|
||||
#define MDCDIV 0x00003F00 /* SCLK:MDC Clock Divisor [MDC=SCLK/(2*(N+1))] */
|
||||
|
||||
#define SET_MDCDIV(x) (((x)&0x3F)<< 8) /* Set MDC Clock Divisor */
|
||||
|
||||
/* EMAC_SYSTAT Masks */
|
||||
|
||||
#define PHYINT 0x00000001 /* PHY_INT Interrupt Status */
|
||||
#define MMCINT 0x00000002 /* MMC Counter Interrupt Status */
|
||||
#define RXFSINT 0x00000004 /* RX Frame-Status Interrupt Status */
|
||||
#define TXFSINT 0x00000008 /* TX Frame-Status Interrupt Status */
|
||||
#define WAKEDET 0x00000010 /* Wake-Up Detected Status */
|
||||
#define RXDMAERR 0x00000020 /* RX DMA Direction Error Status */
|
||||
#define TXDMAERR 0x00000040 /* TX DMA Direction Error Status */
|
||||
#define STMDONE 0x00000080 /* Station Mgt. Transfer Done Interrupt Status */
|
||||
|
||||
/* EMAC_RX_STAT, EMAC_RX_STKY, and EMAC_RX_IRQE Masks */
|
||||
|
||||
#define RX_FRLEN 0x000007FF /* Frame Length In Bytes */
|
||||
#define RX_COMP 0x00001000 /* RX Frame Complete */
|
||||
#define RX_OK 0x00002000 /* RX Frame Received With No Errors */
|
||||
#define RX_LONG 0x00004000 /* RX Frame Too Long Error */
|
||||
#define RX_ALIGN 0x00008000 /* RX Frame Alignment Error */
|
||||
#define RX_CRC 0x00010000 /* RX Frame CRC Error */
|
||||
#define RX_LEN 0x00020000 /* RX Frame Length Error */
|
||||
#define RX_FRAG 0x00040000 /* RX Frame Fragment Error */
|
||||
#define RX_ADDR 0x00080000 /* RX Frame Address Filter Failed Error */
|
||||
#define RX_DMAO 0x00100000 /* RX Frame DMA Overrun Error */
|
||||
#define RX_PHY 0x00200000 /* RX Frame PHY Error */
|
||||
#define RX_LATE 0x00400000 /* RX Frame Late Collision Error */
|
||||
#define RX_RANGE 0x00800000 /* RX Frame Length Field Out of Range Error */
|
||||
#define RX_MULTI 0x01000000 /* RX Multicast Frame Indicator */
|
||||
#define RX_BROAD 0x02000000 /* RX Broadcast Frame Indicator */
|
||||
#define RX_CTL 0x04000000 /* RX Control Frame Indicator */
|
||||
#define RX_UCTL 0x08000000 /* Unsupported RX Control Frame Indicator */
|
||||
#define RX_TYPE 0x10000000 /* RX Typed Frame Indicator */
|
||||
#define RX_VLAN1 0x20000000 /* RX VLAN1 Frame Indicator */
|
||||
#define RX_VLAN2 0x40000000 /* RX VLAN2 Frame Indicator */
|
||||
#define RX_ACCEPT 0x80000000 /* RX Frame Accepted Indicator */
|
||||
|
||||
/* EMAC_TX_STAT, EMAC_TX_STKY, and EMAC_TX_IRQE Masks */
|
||||
|
||||
#define TX_COMP 0x00000001 /* TX Frame Complete */
|
||||
#define TX_OK 0x00000002 /* TX Frame Sent With No Errors */
|
||||
#define TX_ECOLL 0x00000004 /* TX Frame Excessive Collision Error */
|
||||
#define TX_LATE 0x00000008 /* TX Frame Late Collision Error */
|
||||
#define TX_DMAU 0x00000010 /* TX Frame DMA Underrun Error (STAT) */
|
||||
#define TX_MACE 0x00000010 /* Internal MAC Error Detected (STKY and IRQE) */
|
||||
#define TX_EDEFER 0x00000020 /* TX Frame Excessive Deferral Error */
|
||||
#define TX_BROAD 0x00000040 /* TX Broadcast Frame Indicator */
|
||||
#define TX_MULTI 0x00000080 /* TX Multicast Frame Indicator */
|
||||
#define TX_CCNT 0x00000F00 /* TX Frame Collision Count */
|
||||
#define TX_DEFER 0x00001000 /* TX Frame Deferred Indicator */
|
||||
#define TX_CRS 0x00002000 /* TX Frame Carrier Sense Not Asserted Error */
|
||||
#define TX_LOSS 0x00004000 /* TX Frame Carrier Lost During TX Error */
|
||||
#define TX_RETRY 0x00008000 /* TX Frame Successful After Retry */
|
||||
#define TX_FRLEN 0x07FF0000 /* TX Frame Length (Bytes) */
|
||||
|
||||
/* EMAC_MMC_CTL Masks */
|
||||
#define RSTC 0x00000001 /* Reset All Counters */
|
||||
#define CROLL 0x00000002 /* Counter Roll-Over Enable */
|
||||
#define CCOR 0x00000004 /* Counter Clear-On-Read Mode Enable */
|
||||
#define MMCE 0x00000008 /* Enable MMC Counter Operation */
|
||||
|
||||
/* EMAC_MMC_RIRQS and EMAC_MMC_RIRQE Masks */
|
||||
#define RX_OK_CNT 0x00000001 /* RX Frames Received With No Errors */
|
||||
#define RX_FCS_CNT 0x00000002 /* RX Frames W/Frame Check Sequence Errors */
|
||||
#define RX_ALIGN_CNT 0x00000004 /* RX Frames With Alignment Errors */
|
||||
#define RX_OCTET_CNT 0x00000008 /* RX Octets Received OK */
|
||||
#define RX_LOST_CNT 0x00000010 /* RX Frames Lost Due To Internal MAC RX Error */
|
||||
#define RX_UNI_CNT 0x00000020 /* Unicast RX Frames Received OK */
|
||||
#define RX_MULTI_CNT 0x00000040 /* Multicast RX Frames Received OK */
|
||||
#define RX_BROAD_CNT 0x00000080 /* Broadcast RX Frames Received OK */
|
||||
#define RX_IRL_CNT 0x00000100 /* RX Frames With In-Range Length Errors */
|
||||
#define RX_ORL_CNT 0x00000200 /* RX Frames With Out-Of-Range Length Errors */
|
||||
#define RX_LONG_CNT 0x00000400 /* RX Frames With Frame Too Long Errors */
|
||||
#define RX_MACCTL_CNT 0x00000800 /* MAC Control RX Frames Received */
|
||||
#define RX_OPCODE_CTL 0x00001000 /* Unsupported Op-Code RX Frames Received */
|
||||
#define RX_PAUSE_CNT 0x00002000 /* PAUSEMAC Control RX Frames Received */
|
||||
#define RX_ALLF_CNT 0x00004000 /* All RX Frames Received */
|
||||
#define RX_ALLO_CNT 0x00008000 /* All RX Octets Received */
|
||||
#define RX_TYPED_CNT 0x00010000 /* Typed RX Frames Received */
|
||||
#define RX_SHORT_CNT 0x00020000 /* RX Frame Fragments (< 64 Bytes) Received */
|
||||
#define RX_EQ64_CNT 0x00040000 /* 64-Byte RX Frames Received */
|
||||
#define RX_LT128_CNT 0x00080000 /* 65-127-Byte RX Frames Received */
|
||||
#define RX_LT256_CNT 0x00100000 /* 128-255-Byte RX Frames Received */
|
||||
#define RX_LT512_CNT 0x00200000 /* 256-511-Byte RX Frames Received */
|
||||
#define RX_LT1024_CNT 0x00400000 /* 512-1023-Byte RX Frames Received */
|
||||
#define RX_GE1024_CNT 0x00800000 /* 1024-Max-Byte RX Frames Received */
|
||||
|
||||
/* EMAC_MMC_TIRQS and EMAC_MMC_TIRQE Masks */
|
||||
|
||||
#define TX_OK_CNT 0x00000001 /* TX Frames Sent OK */
|
||||
#define TX_SCOLL_CNT 0x00000002 /* TX Frames With Single Collisions */
|
||||
#define TX_MCOLL_CNT 0x00000004 /* TX Frames With Multiple Collisions */
|
||||
#define TX_OCTET_CNT 0x00000008 /* TX Octets Sent OK */
|
||||
#define TX_DEFER_CNT 0x00000010 /* TX Frames With Deferred Transmission */
|
||||
#define TX_LATE_CNT 0x00000020 /* TX Frames With Late Collisions */
|
||||
#define TX_ABORTC_CNT 0x00000040 /* TX Frames Aborted Due To Excess Collisions */
|
||||
#define TX_LOST_CNT 0x00000080 /* TX Frames Lost Due To Internal MAC TX Error */
|
||||
#define TX_CRS_CNT 0x00000100 /* TX Frames With Carrier Sense Errors */
|
||||
#define TX_UNI_CNT 0x00000200 /* Unicast TX Frames Sent */
|
||||
#define TX_MULTI_CNT 0x00000400 /* Multicast TX Frames Sent */
|
||||
#define TX_BROAD_CNT 0x00000800 /* Broadcast TX Frames Sent */
|
||||
#define TX_EXDEF_CTL 0x00001000 /* TX Frames With Excessive Deferral */
|
||||
#define TX_MACCTL_CNT 0x00002000 /* MAC Control TX Frames Sent */
|
||||
#define TX_ALLF_CNT 0x00004000 /* All TX Frames Sent */
|
||||
#define TX_ALLO_CNT 0x00008000 /* All TX Octets Sent */
|
||||
#define TX_EQ64_CNT 0x00010000 /* 64-Byte TX Frames Sent */
|
||||
#define TX_LT128_CNT 0x00020000 /* 65-127-Byte TX Frames Sent */
|
||||
#define TX_LT256_CNT 0x00040000 /* 128-255-Byte TX Frames Sent */
|
||||
#define TX_LT512_CNT 0x00080000 /* 256-511-Byte TX Frames Sent */
|
||||
#define TX_LT1024_CNT 0x00100000 /* 512-1023-Byte TX Frames Sent */
|
||||
#define TX_GE1024_CNT 0x00200000 /* 1024-Max-Byte TX Frames Sent */
|
||||
#define TX_ABORT_CNT 0x00400000 /* TX Frames Aborted */
|
||||
|
||||
/* SDH Registers */
|
||||
|
||||
#define SDH_PWR_CTL 0xFFC03900 /* SDH Power Control */
|
||||
#define SDH_CLK_CTL 0xFFC03904 /* SDH Clock Control */
|
||||
#define SDH_ARGUMENT 0xFFC03908 /* SDH Argument */
|
||||
#define SDH_COMMAND 0xFFC0390C /* SDH Command */
|
||||
#define SDH_RESP_CMD 0xFFC03910 /* SDH Response Command */
|
||||
#define SDH_RESPONSE0 0xFFC03914 /* SDH Response0 */
|
||||
#define SDH_RESPONSE1 0xFFC03918 /* SDH Response1 */
|
||||
#define SDH_RESPONSE2 0xFFC0391C /* SDH Response2 */
|
||||
#define SDH_RESPONSE3 0xFFC03920 /* SDH Response3 */
|
||||
#define SDH_DATA_TIMER 0xFFC03924 /* SDH Data Timer */
|
||||
#define SDH_DATA_LGTH 0xFFC03928 /* SDH Data Length */
|
||||
#define SDH_DATA_CTL 0xFFC0392C /* SDH Data Control */
|
||||
#define SDH_DATA_CNT 0xFFC03930 /* SDH Data Counter */
|
||||
#define SDH_STATUS 0xFFC03934 /* SDH Status */
|
||||
#define SDH_STATUS_CLR 0xFFC03938 /* SDH Status Clear */
|
||||
#define SDH_MASK0 0xFFC0393C /* SDH Interrupt0 Mask */
|
||||
#define SDH_MASK1 0xFFC03940 /* SDH Interrupt1 Mask */
|
||||
#define SDH_FIFO_CNT 0xFFC03948 /* SDH FIFO Counter */
|
||||
#define SDH_FIFO 0xFFC03980 /* SDH Data FIFO */
|
||||
#define SDH_E_STATUS 0xFFC039C0 /* SDH Exception Status */
|
||||
#define SDH_E_MASK 0xFFC039C4 /* SDH Exception Mask */
|
||||
#define SDH_CFG 0xFFC039C8 /* SDH Configuration */
|
||||
#define SDH_RD_WAIT_EN 0xFFC039CC /* SDH Read Wait Enable */
|
||||
#define SDH_PID0 0xFFC039D0 /* SDH Peripheral Identification0 */
|
||||
#define SDH_PID1 0xFFC039D4 /* SDH Peripheral Identification1 */
|
||||
#define SDH_PID2 0xFFC039D8 /* SDH Peripheral Identification2 */
|
||||
#define SDH_PID3 0xFFC039DC /* SDH Peripheral Identification3 */
|
||||
#define SDH_PID4 0xFFC039E0 /* SDH Peripheral Identification4 */
|
||||
#define SDH_PID5 0xFFC039E4 /* SDH Peripheral Identification5 */
|
||||
#define SDH_PID6 0xFFC039E8 /* SDH Peripheral Identification6 */
|
||||
#define SDH_PID7 0xFFC039EC /* SDH Peripheral Identification7 */
|
||||
|
||||
/* Removable Storage Interface Registers */
|
||||
|
||||
#define RSI_PWR_CONTROL 0xFFC03800 /* RSI Power Control Register */
|
||||
#define RSI_CLK_CONTROL 0xFFC03804 /* RSI Clock Control Register */
|
||||
#define RSI_ARGUMENT 0xFFC03808 /* RSI Argument Register */
|
||||
#define RSI_COMMAND 0xFFC0380C /* RSI Command Register */
|
||||
#define RSI_RESP_CMD 0xFFC03810 /* RSI Response Command Register */
|
||||
#define RSI_RESPONSE0 0xFFC03814 /* RSI Response Register */
|
||||
#define RSI_RESPONSE1 0xFFC03818 /* RSI Response Register */
|
||||
#define RSI_RESPONSE2 0xFFC0381C /* RSI Response Register */
|
||||
#define RSI_RESPONSE3 0xFFC03820 /* RSI Response Register */
|
||||
#define RSI_DATA_TIMER 0xFFC03824 /* RSI Data Timer Register */
|
||||
#define RSI_DATA_LGTH 0xFFC03828 /* RSI Data Length Register */
|
||||
#define RSI_DATA_CONTROL 0xFFC0382C /* RSI Data Control Register */
|
||||
#define RSI_DATA_CNT 0xFFC03830 /* RSI Data Counter Register */
|
||||
#define RSI_STATUS 0xFFC03834 /* RSI Status Register */
|
||||
#define RSI_STATUSCL 0xFFC03838 /* RSI Status Clear Register */
|
||||
#define RSI_MASK0 0xFFC0383C /* RSI Interrupt 0 Mask Register */
|
||||
#define RSI_MASK1 0xFFC03840 /* RSI Interrupt 1 Mask Register */
|
||||
#define RSI_FIFO_CNT 0xFFC03848 /* RSI FIFO Counter Register */
|
||||
#define RSI_CEATA_CONTROL 0xFFC0384C /* RSI CEATA Register */
|
||||
#define RSI_FIFO 0xFFC03880 /* RSI Data FIFO Register */
|
||||
#define RSI_ESTAT 0xFFC038C0 /* RSI Exception Status Register */
|
||||
#define RSI_EMASK 0xFFC038C4 /* RSI Exception Mask Register */
|
||||
#define RSI_CONFIG 0xFFC038C8 /* RSI Configuration Register */
|
||||
#define RSI_RD_WAIT_EN 0xFFC038CC /* RSI Read Wait Enable Register */
|
||||
#define RSI_PID0 0xFFC03FE0 /* RSI Peripheral ID Register 0 */
|
||||
#define RSI_PID1 0xFFC03FE4 /* RSI Peripheral ID Register 1 */
|
||||
#define RSI_PID2 0xFFC03FE8 /* RSI Peripheral ID Register 2 */
|
||||
#define RSI_PID3 0xFFC03FEC /* RSI Peripheral ID Register 3 */
|
||||
#define RSI_PID4 0xFFC03FF0 /* RSI Peripheral ID Register 4 */
|
||||
#define RSI_PID5 0xFFC03FF4 /* RSI Peripheral ID Register 5 */
|
||||
#define RSI_PID6 0xFFC03FF8 /* RSI Peripheral ID Register 6 */
|
||||
#define RSI_PID7 0xFFC03FFC /* RSI Peripheral ID Register 7 */
|
||||
|
||||
/* PTP TSYNC Registers */
|
||||
|
||||
#define EMAC_PTP_CTL 0xFFC030A0 /* PTP Block Control */
|
||||
#define EMAC_PTP_IE 0xFFC030A4 /* PTP Block Interrupt Enable */
|
||||
#define EMAC_PTP_ISTAT 0xFFC030A8 /* PTP Block Interrupt Status */
|
||||
#define EMAC_PTP_FOFF 0xFFC030AC /* PTP Filter offset Register */
|
||||
#define EMAC_PTP_FV1 0xFFC030B0 /* PTP Filter Value Register 1 */
|
||||
#define EMAC_PTP_FV2 0xFFC030B4 /* PTP Filter Value Register 2 */
|
||||
#define EMAC_PTP_FV3 0xFFC030B8 /* PTP Filter Value Register 3 */
|
||||
#define EMAC_PTP_ADDEND 0xFFC030BC /* PTP Addend for Frequency Compensation */
|
||||
#define EMAC_PTP_ACCR 0xFFC030C0 /* PTP Accumulator for Frequency Compensation */
|
||||
#define EMAC_PTP_OFFSET 0xFFC030C4 /* PTP Time Offset Register */
|
||||
#define EMAC_PTP_TIMELO 0xFFC030C8 /* PTP Precision Clock Time Low */
|
||||
#define EMAC_PTP_TIMEHI 0xFFC030CC /* PTP Precision Clock Time High */
|
||||
#define EMAC_PTP_RXSNAPLO 0xFFC030D0 /* PTP Receive Snapshot Register Low */
|
||||
#define EMAC_PTP_RXSNAPHI 0xFFC030D4 /* PTP Receive Snapshot Register High */
|
||||
#define EMAC_PTP_TXSNAPLO 0xFFC030D8 /* PTP Transmit Snapshot Register Low */
|
||||
#define EMAC_PTP_TXSNAPHI 0xFFC030DC /* PTP Transmit Snapshot Register High */
|
||||
#define EMAC_PTP_ALARMLO 0xFFC030E0 /* PTP Alarm time Low */
|
||||
#define EMAC_PTP_ALARMHI 0xFFC030E4 /* PTP Alarm time High */
|
||||
#define EMAC_PTP_ID_OFF 0xFFC030E8 /* PTP Capture ID offset register */
|
||||
#define EMAC_PTP_ID_SNAP 0xFFC030EC /* PTP Capture ID register */
|
||||
#define EMAC_PTP_PPS_STARTLO 0xFFC030F0 /* PPS Start Time Low */
|
||||
#define EMAC_PTP_PPS_STARTHI 0xFFC030F4 /* PPS Start Time High */
|
||||
#define EMAC_PTP_PPS_PERIOD 0xFFC030F8 /* PPS Count Register */
|
||||
|
||||
#endif /* _DEF_BF518_H */
|
||||
Разница между файлами не показана из-за своего большого размера
Загрузить разницу
|
|
@ -0,0 +1,57 @@
|
|||
/*
|
||||
* file: include/asm-blackfin/mach-bf518/dma.h
|
||||
* based on: include/asm-blackfin/mach-bf527/dma.h
|
||||
* author: Michael Hennerich (michael.hennerich@analog.com)
|
||||
*
|
||||
* created:
|
||||
* description:
|
||||
* system DMA map
|
||||
* rev:
|
||||
*
|
||||
* modified:
|
||||
*
|
||||
*
|
||||
* bugs: enter bugs at http://blackfin.uclinux.org/
|
||||
*
|
||||
* this program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the gnu general public license as published by
|
||||
* the free software foundation; either version 2, or (at your option)
|
||||
* any later version.
|
||||
*
|
||||
* this program is distributed in the hope that it will be useful,
|
||||
* but without any warranty; without even the implied warranty of
|
||||
* merchantability or fitness for a particular purpose. see the
|
||||
* gnu general public license for more details.
|
||||
*
|
||||
* you should have received a copy of the gnu general public license
|
||||
* along with this program; see the file copying.
|
||||
* if not, write to the free software foundation,
|
||||
* 59 temple place - suite 330, boston, ma 02111-1307, usa.
|
||||
*/
|
||||
|
||||
#ifndef _MACH_DMA_H_
|
||||
#define _MACH_DMA_H_
|
||||
|
||||
#define MAX_BLACKFIN_DMA_CHANNEL 16
|
||||
|
||||
#define CH_PPI 0 /* PPI receive/transmit */
|
||||
#define CH_EMAC_RX 1 /* Ethernet MAC receive */
|
||||
#define CH_EMAC_TX 2 /* Ethernet MAC transmit */
|
||||
#define CH_SPORT0_RX 3 /* SPORT0 receive */
|
||||
#define CH_SPORT0_TX 4 /* SPORT0 transmit */
|
||||
#define CH_RSI 4 /* RSI */
|
||||
#define CH_SPORT1_RX 5 /* SPORT1 receive */
|
||||
#define CH_SPI1 5 /* SPI1 transmit/receive */
|
||||
#define CH_SPORT1_TX 6 /* SPORT1 transmit */
|
||||
#define CH_SPI0 7 /* SPI0 transmit/receive */
|
||||
#define CH_UART0_RX 8 /* UART0 receive */
|
||||
#define CH_UART0_TX 9 /* UART0 transmit */
|
||||
#define CH_UART1_RX 10 /* UART1 receive */
|
||||
#define CH_UART1_TX 11 /* UART1 transmit */
|
||||
|
||||
#define CH_MEM_STREAM0_SRC 12 /* RX */
|
||||
#define CH_MEM_STREAM0_DEST 13 /* TX */
|
||||
#define CH_MEM_STREAM1_SRC 14 /* RX */
|
||||
#define CH_MEM_STREAM1_DEST 15 /* TX */
|
||||
|
||||
#endif
|
||||
|
|
@ -0,0 +1,260 @@
|
|||
/*
|
||||
* file: include/asm-blackfin/mach-bf518/irq.h
|
||||
* based on: include/asm-blackfin/mach-bf527/irq.h
|
||||
* author: Michael Hennerich (michael.hennerich@analog.com)
|
||||
*
|
||||
* created:
|
||||
* description:
|
||||
* system mmr register map
|
||||
* rev:
|
||||
*
|
||||
* modified:
|
||||
*
|
||||
*
|
||||
* bugs: enter bugs at http://blackfin.uclinux.org/
|
||||
*
|
||||
* this program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the gnu general public license as published by
|
||||
* the free software foundation; either version 2, or (at your option)
|
||||
* any later version.
|
||||
*
|
||||
* this program is distributed in the hope that it will be useful,
|
||||
* but without any warranty; without even the implied warranty of
|
||||
* merchantability or fitness for a particular purpose. see the
|
||||
* gnu general public license for more details.
|
||||
*
|
||||
* you should have received a copy of the gnu general public license
|
||||
* along with this program; see the file copying.
|
||||
* if not, write to the free software foundation,
|
||||
* 59 temple place - suite 330, boston, ma 02111-1307, usa.
|
||||
*/
|
||||
|
||||
#ifndef _BF518_IRQ_H_
|
||||
#define _BF518_IRQ_H_
|
||||
|
||||
/*
|
||||
* Interrupt source definitions
|
||||
Event Source Core Event Name
|
||||
Core Emulation **
|
||||
Events (highest priority) EMU 0
|
||||
Reset RST 1
|
||||
NMI NMI 2
|
||||
Exception EVX 3
|
||||
Reserved -- 4
|
||||
Hardware Error IVHW 5
|
||||
Core Timer IVTMR 6 *
|
||||
|
||||
.....
|
||||
|
||||
Software Interrupt 1 IVG14 31
|
||||
Software Interrupt 2 --
|
||||
(lowest priority) IVG15 32 *
|
||||
*/
|
||||
|
||||
#define NR_PERI_INTS (2 * 32)
|
||||
|
||||
/* The ABSTRACT IRQ definitions */
|
||||
/** the first seven of the following are fixed, the rest you change if you need to **/
|
||||
#define IRQ_EMU 0 /* Emulation */
|
||||
#define IRQ_RST 1 /* reset */
|
||||
#define IRQ_NMI 2 /* Non Maskable */
|
||||
#define IRQ_EVX 3 /* Exception */
|
||||
#define IRQ_UNUSED 4 /* - unused interrupt */
|
||||
#define IRQ_HWERR 5 /* Hardware Error */
|
||||
#define IRQ_CORETMR 6 /* Core timer */
|
||||
|
||||
#define BFIN_IRQ(x) ((x) + 7)
|
||||
|
||||
#define IRQ_PLL_WAKEUP BFIN_IRQ(0) /* PLL Wakeup Interrupt */
|
||||
#define IRQ_DMA0_ERROR BFIN_IRQ(1) /* DMA Error 0 (generic) */
|
||||
#define IRQ_DMAR0_BLK BFIN_IRQ(2) /* DMAR0 Block Interrupt */
|
||||
#define IRQ_DMAR1_BLK BFIN_IRQ(3) /* DMAR1 Block Interrupt */
|
||||
#define IRQ_DMAR0_OVR BFIN_IRQ(4) /* DMAR0 Overflow Error */
|
||||
#define IRQ_DMAR1_OVR BFIN_IRQ(5) /* DMAR1 Overflow Error */
|
||||
#define IRQ_PPI_ERROR BFIN_IRQ(6) /* PPI Error */
|
||||
#define IRQ_MAC_ERROR BFIN_IRQ(7) /* MAC Status */
|
||||
#define IRQ_SPORT0_ERROR BFIN_IRQ(8) /* SPORT0 Status */
|
||||
#define IRQ_SPORT1_ERROR BFIN_IRQ(9) /* SPORT1 Status */
|
||||
#define IRQ_PTP_ERROR BFIN_IRQ(10) /* PTP Error Interrupt */
|
||||
#define IRQ_UART0_ERROR BFIN_IRQ(12) /* UART0 Status */
|
||||
#define IRQ_UART1_ERROR BFIN_IRQ(13) /* UART1 Status */
|
||||
#define IRQ_RTC BFIN_IRQ(14) /* RTC */
|
||||
#define IRQ_PPI BFIN_IRQ(15) /* DMA Channel 0 (PPI) */
|
||||
#define IRQ_SPORT0_RX BFIN_IRQ(16) /* DMA 3 Channel (SPORT0 RX) */
|
||||
#define IRQ_SPORT0_TX BFIN_IRQ(17) /* DMA 4 Channel (SPORT0 TX) */
|
||||
#define IRQ_RSI BFIN_IRQ(17) /* DMA 4 Channel (RSI) */
|
||||
#define IRQ_SPORT1_RX BFIN_IRQ(18) /* DMA 5 Channel (SPORT1 RX/SPI) */
|
||||
#define IRQ_SPI1 BFIN_IRQ(18) /* DMA 5 Channel (SPI1) */
|
||||
#define IRQ_SPORT1_TX BFIN_IRQ(19) /* DMA 6 Channel (SPORT1 TX) */
|
||||
#define IRQ_TWI BFIN_IRQ(20) /* TWI */
|
||||
#define IRQ_SPI0 BFIN_IRQ(21) /* DMA 7 Channel (SPI0) */
|
||||
#define IRQ_UART0_RX BFIN_IRQ(22) /* DMA8 Channel (UART0 RX) */
|
||||
#define IRQ_UART0_TX BFIN_IRQ(23) /* DMA9 Channel (UART0 TX) */
|
||||
#define IRQ_UART1_RX BFIN_IRQ(24) /* DMA10 Channel (UART1 RX) */
|
||||
#define IRQ_UART1_TX BFIN_IRQ(25) /* DMA11 Channel (UART1 TX) */
|
||||
#define IRQ_OPTSEC BFIN_IRQ(26) /* OTPSEC Interrupt */
|
||||
#define IRQ_CNT BFIN_IRQ(27) /* GP Counter */
|
||||
#define IRQ_MAC_RX BFIN_IRQ(28) /* DMA1 Channel (MAC RX) */
|
||||
#define IRQ_PORTH_INTA BFIN_IRQ(29) /* Port H Interrupt A */
|
||||
#define IRQ_MAC_TX BFIN_IRQ(30) /* DMA2 Channel (MAC TX) */
|
||||
#define IRQ_PORTH_INTB BFIN_IRQ(31) /* Port H Interrupt B */
|
||||
#define IRQ_TMR0 BFIN_IRQ(32) /* Timer 0 */
|
||||
#define IRQ_TMR1 BFIN_IRQ(33) /* Timer 1 */
|
||||
#define IRQ_TMR2 BFIN_IRQ(34) /* Timer 2 */
|
||||
#define IRQ_TMR3 BFIN_IRQ(35) /* Timer 3 */
|
||||
#define IRQ_TMR4 BFIN_IRQ(36) /* Timer 4 */
|
||||
#define IRQ_TMR5 BFIN_IRQ(37) /* Timer 5 */
|
||||
#define IRQ_TMR6 BFIN_IRQ(38) /* Timer 6 */
|
||||
#define IRQ_TMR7 BFIN_IRQ(39) /* Timer 7 */
|
||||
#define IRQ_PORTG_INTA BFIN_IRQ(40) /* Port G Interrupt A */
|
||||
#define IRQ_PORTG_INTB BFIN_IRQ(41) /* Port G Interrupt B */
|
||||
#define IRQ_MEM_DMA0 BFIN_IRQ(42) /* MDMA Stream 0 */
|
||||
#define IRQ_MEM_DMA1 BFIN_IRQ(43) /* MDMA Stream 1 */
|
||||
#define IRQ_WATCH BFIN_IRQ(44) /* Software Watchdog Timer */
|
||||
#define IRQ_PORTF_INTA BFIN_IRQ(45) /* Port F Interrupt A */
|
||||
#define IRQ_PORTF_INTB BFIN_IRQ(46) /* Port F Interrupt B */
|
||||
#define IRQ_SPI0_ERROR BFIN_IRQ(47) /* SPI0 Status */
|
||||
#define IRQ_SPI1_ERROR BFIN_IRQ(48) /* SPI1 Error */
|
||||
#define IRQ_RSI_INT0 BFIN_IRQ(51) /* RSI Interrupt0 */
|
||||
#define IRQ_RSI_INT1 BFIN_IRQ(52) /* RSI Interrupt1 */
|
||||
#define IRQ_PWM_TRIP BFIN_IRQ(53) /* PWM Trip Interrupt */
|
||||
#define IRQ_PWM_SYNC BFIN_IRQ(54) /* PWM Sync Interrupt */
|
||||
#define IRQ_PTP_STAT BFIN_IRQ(55) /* PTP Stat Interrupt */
|
||||
|
||||
#define SYS_IRQS BFIN_IRQ(63) /* 70 */
|
||||
|
||||
#define IRQ_PF0 71
|
||||
#define IRQ_PF1 72
|
||||
#define IRQ_PF2 73
|
||||
#define IRQ_PF3 74
|
||||
#define IRQ_PF4 75
|
||||
#define IRQ_PF5 76
|
||||
#define IRQ_PF6 77
|
||||
#define IRQ_PF7 78
|
||||
#define IRQ_PF8 79
|
||||
#define IRQ_PF9 80
|
||||
#define IRQ_PF10 81
|
||||
#define IRQ_PF11 82
|
||||
#define IRQ_PF12 83
|
||||
#define IRQ_PF13 84
|
||||
#define IRQ_PF14 85
|
||||
#define IRQ_PF15 86
|
||||
|
||||
#define IRQ_PG0 87
|
||||
#define IRQ_PG1 88
|
||||
#define IRQ_PG2 89
|
||||
#define IRQ_PG3 90
|
||||
#define IRQ_PG4 91
|
||||
#define IRQ_PG5 92
|
||||
#define IRQ_PG6 93
|
||||
#define IRQ_PG7 94
|
||||
#define IRQ_PG8 95
|
||||
#define IRQ_PG9 96
|
||||
#define IRQ_PG10 97
|
||||
#define IRQ_PG11 98
|
||||
#define IRQ_PG12 99
|
||||
#define IRQ_PG13 100
|
||||
#define IRQ_PG14 101
|
||||
#define IRQ_PG15 102
|
||||
|
||||
#define IRQ_PH0 103
|
||||
#define IRQ_PH1 104
|
||||
#define IRQ_PH2 105
|
||||
#define IRQ_PH3 106
|
||||
#define IRQ_PH4 107
|
||||
#define IRQ_PH5 108
|
||||
#define IRQ_PH6 109
|
||||
#define IRQ_PH7 110
|
||||
#define IRQ_PH8 111
|
||||
#define IRQ_PH9 112
|
||||
#define IRQ_PH10 113
|
||||
#define IRQ_PH11 114
|
||||
#define IRQ_PH12 115
|
||||
#define IRQ_PH13 116
|
||||
#define IRQ_PH14 117
|
||||
#define IRQ_PH15 118
|
||||
|
||||
#define GPIO_IRQ_BASE IRQ_PF0
|
||||
|
||||
#define NR_IRQS (IRQ_PH15 + 1)
|
||||
|
||||
#define IVG7 7
|
||||
#define IVG8 8
|
||||
#define IVG9 9
|
||||
#define IVG10 10
|
||||
#define IVG11 11
|
||||
#define IVG12 12
|
||||
#define IVG13 13
|
||||
#define IVG14 14
|
||||
#define IVG15 15
|
||||
|
||||
/* IAR0 BIT FIELDS */
|
||||
#define IRQ_PLL_WAKEUP_POS 0
|
||||
#define IRQ_DMA0_ERROR_POS 4
|
||||
#define IRQ_DMAR0_BLK_POS 8
|
||||
#define IRQ_DMAR1_BLK_POS 12
|
||||
#define IRQ_DMAR0_OVR_POS 16
|
||||
#define IRQ_DMAR1_OVR_POS 20
|
||||
#define IRQ_PPI_ERROR_POS 24
|
||||
#define IRQ_MAC_ERROR_POS 28
|
||||
|
||||
/* IAR1 BIT FIELDS */
|
||||
#define IRQ_SPORT0_ERROR_POS 0
|
||||
#define IRQ_SPORT1_ERROR_POS 4
|
||||
#define IRQ_PTP_ERROR_POS 8
|
||||
#define IRQ_UART0_ERROR_POS 16
|
||||
#define IRQ_UART1_ERROR_POS 20
|
||||
#define IRQ_RTC_POS 24
|
||||
#define IRQ_PPI_POS 28
|
||||
|
||||
/* IAR2 BIT FIELDS */
|
||||
#define IRQ_SPORT0_RX_POS 0
|
||||
#define IRQ_SPORT0_TX_POS 4
|
||||
#define IRQ_RSI_POS 4
|
||||
#define IRQ_SPORT1_RX_POS 8
|
||||
#define IRQ_SPI1_POS 8
|
||||
#define IRQ_SPORT1_TX_POS 12
|
||||
#define IRQ_TWI_POS 16
|
||||
#define IRQ_SPI0_POS 20
|
||||
#define IRQ_UART0_RX_POS 24
|
||||
#define IRQ_UART0_TX_POS 28
|
||||
|
||||
/* IAR3 BIT FIELDS */
|
||||
#define IRQ_UART1_RX_POS 0
|
||||
#define IRQ_UART1_TX_POS 4
|
||||
#define IRQ_OPTSEC_POS 8
|
||||
#define IRQ_CNT_POS 12
|
||||
#define IRQ_MAC_RX_POS 16
|
||||
#define IRQ_PORTH_INTA_POS 20
|
||||
#define IRQ_MAC_TX_POS 24
|
||||
#define IRQ_PORTH_INTB_POS 28
|
||||
|
||||
/* IAR4 BIT FIELDS */
|
||||
#define IRQ_TMR0_POS 0
|
||||
#define IRQ_TMR1_POS 4
|
||||
#define IRQ_TMR2_POS 8
|
||||
#define IRQ_TMR3_POS 12
|
||||
#define IRQ_TMR4_POS 16
|
||||
#define IRQ_TMR5_POS 20
|
||||
#define IRQ_TMR6_POS 24
|
||||
#define IRQ_TMR7_POS 28
|
||||
|
||||
/* IAR5 BIT FIELDS */
|
||||
#define IRQ_PORTG_INTA_POS 0
|
||||
#define IRQ_PORTG_INTB_POS 4
|
||||
#define IRQ_MEM_DMA0_POS 8
|
||||
#define IRQ_MEM_DMA1_POS 12
|
||||
#define IRQ_WATCH_POS 16
|
||||
#define IRQ_PORTF_INTA_POS 20
|
||||
#define IRQ_PORTF_INTB_POS 24
|
||||
#define IRQ_SPI0_ERROR_POS 28
|
||||
|
||||
/* IAR6 BIT FIELDS */
|
||||
#define IRQ_SPI1_ERROR_POS 0
|
||||
#define IRQ_RSI_INT0_POS 12
|
||||
#define IRQ_RSI_INT1_POS 16
|
||||
#define IRQ_PWM_TRIP_POS 20
|
||||
#define IRQ_PWM_SYNC_POS 24
|
||||
#define IRQ_PTP_STAT_POS 28
|
||||
|
||||
#endif /* _BF518_IRQ_H_ */
|
||||
|
|
@ -0,0 +1,310 @@
|
|||
/*
|
||||
* File: include/asm-blackfin/mach-bf518/mem_init.h
|
||||
* Based on:
|
||||
* Author:
|
||||
*
|
||||
* Created:
|
||||
* Description:
|
||||
*
|
||||
* Rev:
|
||||
*
|
||||
* Modified:
|
||||
* Copyright 2004-2007 Analog Devices Inc.
|
||||
*
|
||||
* Bugs: Enter bugs at http://blackfin.uclinux.org/
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2, or (at your option)
|
||||
* any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; see the file COPYING.
|
||||
* If not, write to the Free Software Foundation,
|
||||
* 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
|
||||
*/
|
||||
|
||||
#if (CONFIG_MEM_MT48LC16M16A2TG_75 || CONFIG_MEM_MT48LC64M4A2FB_7E || CONFIG_MEM_MT48LC16M8A2TG_75 || CONFIG_MEM_GENERIC_BOARD || CONFIG_MEM_MT48LC32M8A2_75 || CONFIG_MEM_MT48LC32M16A2TG_75)
|
||||
#if (CONFIG_SCLK_HZ > 119402985)
|
||||
#define SDRAM_tRP TRP_2
|
||||
#define SDRAM_tRP_num 2
|
||||
#define SDRAM_tRAS TRAS_7
|
||||
#define SDRAM_tRAS_num 7
|
||||
#define SDRAM_tRCD TRCD_2
|
||||
#define SDRAM_tWR TWR_2
|
||||
#endif
|
||||
#if (CONFIG_SCLK_HZ > 104477612) && (CONFIG_SCLK_HZ <= 119402985)
|
||||
#define SDRAM_tRP TRP_2
|
||||
#define SDRAM_tRP_num 2
|
||||
#define SDRAM_tRAS TRAS_6
|
||||
#define SDRAM_tRAS_num 6
|
||||
#define SDRAM_tRCD TRCD_2
|
||||
#define SDRAM_tWR TWR_2
|
||||
#endif
|
||||
#if (CONFIG_SCLK_HZ > 89552239) && (CONFIG_SCLK_HZ <= 104477612)
|
||||
#define SDRAM_tRP TRP_2
|
||||
#define SDRAM_tRP_num 2
|
||||
#define SDRAM_tRAS TRAS_5
|
||||
#define SDRAM_tRAS_num 5
|
||||
#define SDRAM_tRCD TRCD_2
|
||||
#define SDRAM_tWR TWR_2
|
||||
#endif
|
||||
#if (CONFIG_SCLK_HZ > 74626866) && (CONFIG_SCLK_HZ <= 89552239)
|
||||
#define SDRAM_tRP TRP_2
|
||||
#define SDRAM_tRP_num 2
|
||||
#define SDRAM_tRAS TRAS_4
|
||||
#define SDRAM_tRAS_num 4
|
||||
#define SDRAM_tRCD TRCD_2
|
||||
#define SDRAM_tWR TWR_2
|
||||
#endif
|
||||
#if (CONFIG_SCLK_HZ > 66666667) && (CONFIG_SCLK_HZ <= 74626866)
|
||||
#define SDRAM_tRP TRP_2
|
||||
#define SDRAM_tRP_num 2
|
||||
#define SDRAM_tRAS TRAS_3
|
||||
#define SDRAM_tRAS_num 3
|
||||
#define SDRAM_tRCD TRCD_2
|
||||
#define SDRAM_tWR TWR_2
|
||||
#endif
|
||||
#if (CONFIG_SCLK_HZ > 59701493) && (CONFIG_SCLK_HZ <= 66666667)
|
||||
#define SDRAM_tRP TRP_1
|
||||
#define SDRAM_tRP_num 1
|
||||
#define SDRAM_tRAS TRAS_4
|
||||
#define SDRAM_tRAS_num 3
|
||||
#define SDRAM_tRCD TRCD_1
|
||||
#define SDRAM_tWR TWR_2
|
||||
#endif
|
||||
#if (CONFIG_SCLK_HZ > 44776119) && (CONFIG_SCLK_HZ <= 59701493)
|
||||
#define SDRAM_tRP TRP_1
|
||||
#define SDRAM_tRP_num 1
|
||||
#define SDRAM_tRAS TRAS_3
|
||||
#define SDRAM_tRAS_num 3
|
||||
#define SDRAM_tRCD TRCD_1
|
||||
#define SDRAM_tWR TWR_2
|
||||
#endif
|
||||
#if (CONFIG_SCLK_HZ > 29850746) && (CONFIG_SCLK_HZ <= 44776119)
|
||||
#define SDRAM_tRP TRP_1
|
||||
#define SDRAM_tRP_num 1
|
||||
#define SDRAM_tRAS TRAS_2
|
||||
#define SDRAM_tRAS_num 2
|
||||
#define SDRAM_tRCD TRCD_1
|
||||
#define SDRAM_tWR TWR_2
|
||||
#endif
|
||||
#if (CONFIG_SCLK_HZ <= 29850746)
|
||||
#define SDRAM_tRP TRP_1
|
||||
#define SDRAM_tRP_num 1
|
||||
#define SDRAM_tRAS TRAS_1
|
||||
#define SDRAM_tRAS_num 1
|
||||
#define SDRAM_tRCD TRCD_1
|
||||
#define SDRAM_tWR TWR_2
|
||||
#endif
|
||||
#endif
|
||||
|
||||
#if (CONFIG_MEM_MT48LC16M16A2TG_75)
|
||||
/*SDRAM INFORMATION: */
|
||||
#define SDRAM_Tref 64 /* Refresh period in milliseconds */
|
||||
#define SDRAM_NRA 8192 /* Number of row addresses in SDRAM */
|
||||
#define SDRAM_CL CL_3
|
||||
#endif
|
||||
|
||||
#if (CONFIG_MEM_MT48LC16M8A2TG_75)
|
||||
/*SDRAM INFORMATION: */
|
||||
#define SDRAM_Tref 64 /* Refresh period in milliseconds */
|
||||
#define SDRAM_NRA 4096 /* Number of row addresses in SDRAM */
|
||||
#define SDRAM_CL CL_3
|
||||
#endif
|
||||
|
||||
#if (CONFIG_MEM_MT48LC32M8A2_75)
|
||||
/*SDRAM INFORMATION: */
|
||||
#define SDRAM_Tref 64 /* Refresh period in milliseconds */
|
||||
#define SDRAM_NRA 8192 /* Number of row addresses in SDRAM */
|
||||
#define SDRAM_CL CL_3
|
||||
#endif
|
||||
|
||||
#if (CONFIG_MEM_MT48LC64M4A2FB_7E)
|
||||
/*SDRAM INFORMATION: */
|
||||
#define SDRAM_Tref 64 /* Refresh period in milliseconds */
|
||||
#define SDRAM_NRA 8192 /* Number of row addresses in SDRAM */
|
||||
#define SDRAM_CL CL_3
|
||||
#endif
|
||||
|
||||
#if (CONFIG_MEM_GENERIC_BOARD)
|
||||
/*SDRAM INFORMATION: Modify this for your board */
|
||||
#define SDRAM_Tref 64 /* Refresh period in milliseconds */
|
||||
#define SDRAM_NRA 8192 /* Number of row addresses in SDRAM */
|
||||
#define SDRAM_CL CL_3
|
||||
#endif
|
||||
|
||||
#if (CONFIG_MEM_MT48LC32M16A2TG_75)
|
||||
/*SDRAM INFORMATION: */
|
||||
#define SDRAM_Tref 64 /* Refresh period in milliseconds */
|
||||
#define SDRAM_NRA 8192 /* Number of row addresses in SDRAM */
|
||||
#define SDRAM_CL CL_3
|
||||
#endif
|
||||
|
||||
/* Equation from section 17 (p17-46) of BF533 HRM */
|
||||
#define mem_SDRRC (((CONFIG_SCLK_HZ / 1000) * SDRAM_Tref) / SDRAM_NRA) - (SDRAM_tRAS_num + SDRAM_tRP_num)
|
||||
|
||||
/* Enable SCLK Out */
|
||||
#define mem_SDGCTL (SCTLE | SDRAM_CL | SDRAM_tRAS | SDRAM_tRP | SDRAM_tRCD | SDRAM_tWR | PSS)
|
||||
|
||||
#if defined CONFIG_CLKIN_HALF
|
||||
#define CLKIN_HALF 1
|
||||
#else
|
||||
#define CLKIN_HALF 0
|
||||
#endif
|
||||
|
||||
#if defined CONFIG_PLL_BYPASS
|
||||
#define PLL_BYPASS 1
|
||||
#else
|
||||
#define PLL_BYPASS 0
|
||||
#endif
|
||||
|
||||
/***************************************Currently Not Being Used *********************************/
|
||||
#define flash_EBIU_AMBCTL_WAT ((CONFIG_FLASH_SPEED_BWAT * 4) / (4000000000 / CONFIG_SCLK_HZ)) + 1
|
||||
#define flash_EBIU_AMBCTL_RAT ((CONFIG_FLASH_SPEED_BRAT * 4) / (4000000000 / CONFIG_SCLK_HZ)) + 1
|
||||
#define flash_EBIU_AMBCTL_HT ((CONFIG_FLASH_SPEED_BHT * 4) / (4000000000 / CONFIG_SCLK_HZ))
|
||||
#define flash_EBIU_AMBCTL_ST ((CONFIG_FLASH_SPEED_BST * 4) / (4000000000 / CONFIG_SCLK_HZ)) + 1
|
||||
#define flash_EBIU_AMBCTL_TT ((CONFIG_FLASH_SPEED_BTT * 4) / (4000000000 / CONFIG_SCLK_HZ)) + 1
|
||||
|
||||
#if (flash_EBIU_AMBCTL_TT > 3)
|
||||
#define flash_EBIU_AMBCTL0_TT B0TT_4
|
||||
#endif
|
||||
#if (flash_EBIU_AMBCTL_TT == 3)
|
||||
#define flash_EBIU_AMBCTL0_TT B0TT_3
|
||||
#endif
|
||||
#if (flash_EBIU_AMBCTL_TT == 2)
|
||||
#define flash_EBIU_AMBCTL0_TT B0TT_2
|
||||
#endif
|
||||
#if (flash_EBIU_AMBCTL_TT < 2)
|
||||
#define flash_EBIU_AMBCTL0_TT B0TT_1
|
||||
#endif
|
||||
|
||||
#if (flash_EBIU_AMBCTL_ST > 3)
|
||||
#define flash_EBIU_AMBCTL0_ST B0ST_4
|
||||
#endif
|
||||
#if (flash_EBIU_AMBCTL_ST == 3)
|
||||
#define flash_EBIU_AMBCTL0_ST B0ST_3
|
||||
#endif
|
||||
#if (flash_EBIU_AMBCTL_ST == 2)
|
||||
#define flash_EBIU_AMBCTL0_ST B0ST_2
|
||||
#endif
|
||||
#if (flash_EBIU_AMBCTL_ST < 2)
|
||||
#define flash_EBIU_AMBCTL0_ST B0ST_1
|
||||
#endif
|
||||
|
||||
#if (flash_EBIU_AMBCTL_HT > 2)
|
||||
#define flash_EBIU_AMBCTL0_HT B0HT_3
|
||||
#endif
|
||||
#if (flash_EBIU_AMBCTL_HT == 2)
|
||||
#define flash_EBIU_AMBCTL0_HT B0HT_2
|
||||
#endif
|
||||
#if (flash_EBIU_AMBCTL_HT == 1)
|
||||
#define flash_EBIU_AMBCTL0_HT B0HT_1
|
||||
#endif
|
||||
#if (flash_EBIU_AMBCTL_HT == 0 && CONFIG_FLASH_SPEED_BHT == 0)
|
||||
#define flash_EBIU_AMBCTL0_HT B0HT_0
|
||||
#endif
|
||||
#if (flash_EBIU_AMBCTL_HT == 0 && CONFIG_FLASH_SPEED_BHT != 0)
|
||||
#define flash_EBIU_AMBCTL0_HT B0HT_1
|
||||
#endif
|
||||
|
||||
#if (flash_EBIU_AMBCTL_WAT > 14)
|
||||
#define flash_EBIU_AMBCTL0_WAT B0WAT_15
|
||||
#endif
|
||||
#if (flash_EBIU_AMBCTL_WAT == 14)
|
||||
#define flash_EBIU_AMBCTL0_WAT B0WAT_14
|
||||
#endif
|
||||
#if (flash_EBIU_AMBCTL_WAT == 13)
|
||||
#define flash_EBIU_AMBCTL0_WAT B0WAT_13
|
||||
#endif
|
||||
#if (flash_EBIU_AMBCTL_WAT == 12)
|
||||
#define flash_EBIU_AMBCTL0_WAT B0WAT_12
|
||||
#endif
|
||||
#if (flash_EBIU_AMBCTL_WAT == 11)
|
||||
#define flash_EBIU_AMBCTL0_WAT B0WAT_11
|
||||
#endif
|
||||
#if (flash_EBIU_AMBCTL_WAT == 10)
|
||||
#define flash_EBIU_AMBCTL0_WAT B0WAT_10
|
||||
#endif
|
||||
#if (flash_EBIU_AMBCTL_WAT == 9)
|
||||
#define flash_EBIU_AMBCTL0_WAT B0WAT_9
|
||||
#endif
|
||||
#if (flash_EBIU_AMBCTL_WAT == 8)
|
||||
#define flash_EBIU_AMBCTL0_WAT B0WAT_8
|
||||
#endif
|
||||
#if (flash_EBIU_AMBCTL_WAT == 7)
|
||||
#define flash_EBIU_AMBCTL0_WAT B0WAT_7
|
||||
#endif
|
||||
#if (flash_EBIU_AMBCTL_WAT == 6)
|
||||
#define flash_EBIU_AMBCTL0_WAT B0WAT_6
|
||||
#endif
|
||||
#if (flash_EBIU_AMBCTL_WAT == 5)
|
||||
#define flash_EBIU_AMBCTL0_WAT B0WAT_5
|
||||
#endif
|
||||
#if (flash_EBIU_AMBCTL_WAT == 4)
|
||||
#define flash_EBIU_AMBCTL0_WAT B0WAT_4
|
||||
#endif
|
||||
#if (flash_EBIU_AMBCTL_WAT == 3)
|
||||
#define flash_EBIU_AMBCTL0_WAT B0WAT_3
|
||||
#endif
|
||||
#if (flash_EBIU_AMBCTL_WAT == 2)
|
||||
#define flash_EBIU_AMBCTL0_WAT B0WAT_2
|
||||
#endif
|
||||
#if (flash_EBIU_AMBCTL_WAT == 1)
|
||||
#define flash_EBIU_AMBCTL0_WAT B0WAT_1
|
||||
#endif
|
||||
|
||||
#if (flash_EBIU_AMBCTL_RAT > 14)
|
||||
#define flash_EBIU_AMBCTL0_RAT B0RAT_15
|
||||
#endif
|
||||
#if (flash_EBIU_AMBCTL_RAT == 14)
|
||||
#define flash_EBIU_AMBCTL0_RAT B0RAT_14
|
||||
#endif
|
||||
#if (flash_EBIU_AMBCTL_RAT == 13)
|
||||
#define flash_EBIU_AMBCTL0_RAT B0RAT_13
|
||||
#endif
|
||||
#if (flash_EBIU_AMBCTL_RAT == 12)
|
||||
#define flash_EBIU_AMBCTL0_RAT B0RAT_12
|
||||
#endif
|
||||
#if (flash_EBIU_AMBCTL_RAT == 11)
|
||||
#define flash_EBIU_AMBCTL0_RAT B0RAT_11
|
||||
#endif
|
||||
#if (flash_EBIU_AMBCTL_RAT == 10)
|
||||
#define flash_EBIU_AMBCTL0_RAT B0RAT_10
|
||||
#endif
|
||||
#if (flash_EBIU_AMBCTL_RAT == 9)
|
||||
#define flash_EBIU_AMBCTL0_RAT B0RAT_9
|
||||
#endif
|
||||
#if (flash_EBIU_AMBCTL_RAT == 8)
|
||||
#define flash_EBIU_AMBCTL0_RAT B0RAT_8
|
||||
#endif
|
||||
#if (flash_EBIU_AMBCTL_RAT == 7)
|
||||
#define flash_EBIU_AMBCTL0_RAT B0RAT_7
|
||||
#endif
|
||||
#if (flash_EBIU_AMBCTL_RAT == 6)
|
||||
#define flash_EBIU_AMBCTL0_RAT B0RAT_6
|
||||
#endif
|
||||
#if (flash_EBIU_AMBCTL_RAT == 5)
|
||||
#define flash_EBIU_AMBCTL0_RAT B0RAT_5
|
||||
#endif
|
||||
#if (flash_EBIU_AMBCTL_RAT == 4)
|
||||
#define flash_EBIU_AMBCTL0_RAT B0RAT_4
|
||||
#endif
|
||||
#if (flash_EBIU_AMBCTL_RAT == 3)
|
||||
#define flash_EBIU_AMBCTL0_RAT B0RAT_3
|
||||
#endif
|
||||
#if (flash_EBIU_AMBCTL_RAT == 2)
|
||||
#define flash_EBIU_AMBCTL0_RAT B0RAT_2
|
||||
#endif
|
||||
#if (flash_EBIU_AMBCTL_RAT == 1)
|
||||
#define flash_EBIU_AMBCTL0_RAT B0RAT_1
|
||||
#endif
|
||||
|
||||
#define flash_EBIU_AMBCTL0 \
|
||||
(flash_EBIU_AMBCTL0_WAT | flash_EBIU_AMBCTL0_RAT | flash_EBIU_AMBCTL0_HT | \
|
||||
flash_EBIU_AMBCTL0_ST | flash_EBIU_AMBCTL0_TT | CONFIG_FLASH_SPEED_RDYEN)
|
||||
|
|
@ -0,0 +1,102 @@
|
|||
/*
|
||||
* file: include/asm-blackfin/mach-bf518/mem_map.h
|
||||
* based on: include/asm-blackfin/mach-bf527/mem_map.h
|
||||
* author: Bryan Wu <cooloney@kernel.org>
|
||||
*
|
||||
* created:
|
||||
* description:
|
||||
* Memory MAP Common header file for blackfin BF518/6/4/2 of processors.
|
||||
* rev:
|
||||
*
|
||||
* modified:
|
||||
*
|
||||
* bugs: enter bugs at http://blackfin.uclinux.org/
|
||||
*
|
||||
* this program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the gnu general public license as published by
|
||||
* the free software foundation; either version 2, or (at your option)
|
||||
* any later version.
|
||||
*
|
||||
* this program is distributed in the hope that it will be useful,
|
||||
* but without any warranty; without even the implied warranty of
|
||||
* merchantability or fitness for a particular purpose. see the
|
||||
* gnu general public license for more details.
|
||||
*
|
||||
* you should have received a copy of the gnu general public license
|
||||
* along with this program; see the file copying.
|
||||
* if not, write to the free software foundation,
|
||||
* 59 temple place - suite 330, boston, ma 02111-1307, usa.
|
||||
*/
|
||||
|
||||
#ifndef _MEM_MAP_518_H_
|
||||
#define _MEM_MAP_518_H_
|
||||
|
||||
#define COREMMR_BASE 0xFFE00000 /* Core MMRs */
|
||||
#define SYSMMR_BASE 0xFFC00000 /* System MMRs */
|
||||
|
||||
/* Async Memory Banks */
|
||||
#define ASYNC_BANK3_BASE 0x20300000 /* Async Bank 3 */
|
||||
#define ASYNC_BANK3_SIZE 0x00100000 /* 1M */
|
||||
#define ASYNC_BANK2_BASE 0x20200000 /* Async Bank 2 */
|
||||
#define ASYNC_BANK2_SIZE 0x00100000 /* 1M */
|
||||
#define ASYNC_BANK1_BASE 0x20100000 /* Async Bank 1 */
|
||||
#define ASYNC_BANK1_SIZE 0x00100000 /* 1M */
|
||||
#define ASYNC_BANK0_BASE 0x20000000 /* Async Bank 0 */
|
||||
#define ASYNC_BANK0_SIZE 0x00100000 /* 1M */
|
||||
|
||||
/* Boot ROM Memory */
|
||||
|
||||
#define BOOT_ROM_START 0xEF000000
|
||||
#define BOOT_ROM_LENGTH 0x8000
|
||||
|
||||
/* Level 1 Memory */
|
||||
|
||||
/* Memory Map for ADSP-BF518/6/4/2 processors */
|
||||
|
||||
#ifdef CONFIG_BFIN_ICACHE
|
||||
#define BFIN_ICACHESIZE (16 * 1024)
|
||||
#else
|
||||
#define BFIN_ICACHESIZE (0)
|
||||
#endif
|
||||
|
||||
#define L1_CODE_START 0xFFA00000
|
||||
#define L1_DATA_A_START 0xFF800000
|
||||
#define L1_DATA_B_START 0xFF900000
|
||||
|
||||
#define L1_CODE_LENGTH 0xC000
|
||||
|
||||
#ifdef CONFIG_BFIN_DCACHE
|
||||
|
||||
#ifdef CONFIG_BFIN_DCACHE_BANKA
|
||||
#define DMEM_CNTR (ACACHE_BSRAM | ENDCPLB | PORT_PREF0)
|
||||
#define L1_DATA_A_LENGTH (0x8000 - 0x4000)
|
||||
#define L1_DATA_B_LENGTH 0x8000
|
||||
#define BFIN_DCACHESIZE (16 * 1024)
|
||||
#define BFIN_DSUPBANKS 1
|
||||
#else
|
||||
#define DMEM_CNTR (ACACHE_BCACHE | ENDCPLB | PORT_PREF0)
|
||||
#define L1_DATA_A_LENGTH (0x8000 - 0x4000)
|
||||
#define L1_DATA_B_LENGTH (0x8000 - 0x4000)
|
||||
#define BFIN_DCACHESIZE (32 * 1024)
|
||||
#define BFIN_DSUPBANKS 2
|
||||
#endif
|
||||
|
||||
#else
|
||||
#define DMEM_CNTR (ASRAM_BSRAM | ENDCPLB | PORT_PREF0)
|
||||
#define L1_DATA_A_LENGTH 0x8000
|
||||
#define L1_DATA_B_LENGTH 0x8000
|
||||
#define BFIN_DCACHESIZE 0
|
||||
#define BFIN_DSUPBANKS 0
|
||||
#endif /*CONFIG_BFIN_DCACHE */
|
||||
|
||||
/* Level 2 Memory - none */
|
||||
|
||||
#define L2_START 0
|
||||
#define L2_LENGTH 0
|
||||
|
||||
/* Scratch Pad Memory */
|
||||
|
||||
#define L1_SCRATCH_START 0xFFB00000
|
||||
#define L1_SCRATCH_LENGTH 0x1000
|
||||
|
||||
#endif /* _MEM_MAP_518_H_ */
|
||||
|
|
@ -0,0 +1,188 @@
|
|||
#ifndef _MACH_PORTMUX_H_
|
||||
#define _MACH_PORTMUX_H_
|
||||
|
||||
#define MAX_RESOURCES MAX_BLACKFIN_GPIOS
|
||||
|
||||
/* EMAC MII/RMII Port Mux */
|
||||
#define P_MII0_ETxD2 (P_DEFINED | P_IDENT(GPIO_PF0) | P_FUNCT(0))
|
||||
#define P_MII0_ERxD2 (P_DEFINED | P_IDENT(GPIO_PF1) | P_FUNCT(0))
|
||||
#define P_MII0_ETxD3 (P_DEFINED | P_IDENT(GPIO_PF2) | P_FUNCT(0))
|
||||
#define P_MII0_ERxD3 (P_DEFINED | P_IDENT(GPIO_PF3) | P_FUNCT(0))
|
||||
#define P_MII0_ERxCLK (P_DEFINED | P_IDENT(GPIO_PF4) | P_FUNCT(0))
|
||||
#define P_MII0_ERxDV (P_DEFINED | P_IDENT(GPIO_PF5) | P_FUNCT(0))
|
||||
#define P_MII0_COL (P_DEFINED | P_IDENT(GPIO_PF6) | P_FUNCT(0))
|
||||
|
||||
#define P_MII0_MDC (P_DEFINED | P_IDENT(GPIO_PF8) | P_FUNCT(0))
|
||||
#define P_MII0_MDIO (P_DEFINED | P_IDENT(GPIO_PF9) | P_FUNCT(0))
|
||||
#define P_MII0_ETxD0 (P_DEFINED | P_IDENT(GPIO_PF10) | P_FUNCT(0))
|
||||
#define P_MII0_ERxD0 (P_DEFINED | P_IDENT(GPIO_PF11) | P_FUNCT(0))
|
||||
#define P_MII0_ETxD1 (P_DEFINED | P_IDENT(GPIO_PF12) | P_FUNCT(0))
|
||||
#define P_MII0_ERxD1 (P_DEFINED | P_IDENT(GPIO_PF13) | P_FUNCT(0))
|
||||
#define P_MII0_ETxEn (P_DEFINED | P_IDENT(GPIO_PF14) | P_FUNCT(0))
|
||||
#define P_MII0_PHYINT (P_DEFINED | P_IDENT(GPIO_PF15) | P_FUNCT(0))
|
||||
#define P_MII0_CRS (P_DEFINED | P_IDENT(GPIO_PG0) | P_FUNCT(0))
|
||||
#define P_MII0_ERxER (P_DEFINED | P_IDENT(GPIO_PG1) | P_FUNCT(0))
|
||||
#define P_MII0_ETxCLK (P_DEFINED | P_IDENT(GPIO_PG2) | P_FUNCT(0))
|
||||
|
||||
#define P_MII {\
|
||||
P_MII0_ETxD0, \
|
||||
P_MII0_ETxD1, \
|
||||
P_MII0_ETxD2, \
|
||||
P_MII0_ETxD3, \
|
||||
P_MII0_ETxEN, \
|
||||
P_MII0_TxCLK, \
|
||||
P_MII0_PHYINT, \
|
||||
P_MII0_COL, \
|
||||
P_MII0_ERxD0, \
|
||||
P_MII0_ERxD1, \
|
||||
P_MII0_ERxD2, \
|
||||
P_MII0_ERxD3, \
|
||||
P_MII0_ERxDV, \
|
||||
P_MII0_ERxCLK, \
|
||||
P_MII0_ERxER, \
|
||||
P_MII0_CRS, \
|
||||
P_MII0_MDC, \
|
||||
P_MII0_MDIO, 0}
|
||||
|
||||
#define P_RMII {\
|
||||
P_MII0_ETxD0, \
|
||||
P_MII0_ETxD1, \
|
||||
P_MII0_ETxEN, \
|
||||
P_MII0_ERxD0, \
|
||||
P_MII0_ERxD1, \
|
||||
P_MII0_ERxER, \
|
||||
P_MII0_TxCLK, \
|
||||
P_MII0_PHYINT, \
|
||||
P_MII0_CRS, \
|
||||
P_MII0_MDC, \
|
||||
P_MII0_MDIO, 0}
|
||||
|
||||
/* PPI Port Mux */
|
||||
#define P_PPI0_D0 (P_DEFINED | P_IDENT(GPIO_PF0) | P_FUNCT(1))
|
||||
#define P_PPI0_D1 (P_DEFINED | P_IDENT(GPIO_PF1) | P_FUNCT(1))
|
||||
#define P_PPI0_D2 (P_DEFINED | P_IDENT(GPIO_PF2) | P_FUNCT(1))
|
||||
#define P_PPI0_D3 (P_DEFINED | P_IDENT(GPIO_PF3) | P_FUNCT(1))
|
||||
#define P_PPI0_D4 (P_DEFINED | P_IDENT(GPIO_PF4) | P_FUNCT(1))
|
||||
#define P_PPI0_D5 (P_DEFINED | P_IDENT(GPIO_PF5) | P_FUNCT(1))
|
||||
#define P_PPI0_D6 (P_DEFINED | P_IDENT(GPIO_PF6) | P_FUNCT(1))
|
||||
#define P_PPI0_D7 (P_DEFINED | P_IDENT(GPIO_PF7) | P_FUNCT(1))
|
||||
#define P_PPI0_D8 (P_DEFINED | P_IDENT(GPIO_PF8) | P_FUNCT(1))
|
||||
#define P_PPI0_D9 (P_DEFINED | P_IDENT(GPIO_PF9) | P_FUNCT(1))
|
||||
#define P_PPI0_D10 (P_DEFINED | P_IDENT(GPIO_PF10) | P_FUNCT(1))
|
||||
#define P_PPI0_D11 (P_DEFINED | P_IDENT(GPIO_PF11) | P_FUNCT(1))
|
||||
#define P_PPI0_D12 (P_DEFINED | P_IDENT(GPIO_PF12) | P_FUNCT(1))
|
||||
#define P_PPI0_D13 (P_DEFINED | P_IDENT(GPIO_PF13) | P_FUNCT(1))
|
||||
#define P_PPI0_D14 (P_DEFINED | P_IDENT(GPIO_PF14) | P_FUNCT(1))
|
||||
#define P_PPI0_D15 (P_DEFINED | P_IDENT(GPIO_PF15) | P_FUNCT(1))
|
||||
|
||||
#define P_PPI0_CLK (P_DEFINED | P_IDENT(GPIO_PG12) | P_FUNCT(1))
|
||||
#define P_PPI0_FS1 (P_DEFINED | P_IDENT(GPIO_PG13) | P_FUNCT(1))
|
||||
#define P_PPI0_FS2 (P_DEFINED | P_IDENT(GPIO_PG14) | P_FUNCT(1))
|
||||
#define P_PPI0_FS3 (P_DEFINED | P_IDENT(GPIO_PG15) | P_FUNCT(1))
|
||||
|
||||
/* SPI Port Mux */
|
||||
#define P_SPI0_SS (P_DEFINED | P_IDENT(GPIO_PG11) | P_FUNCT(0))
|
||||
#define P_SPI0_SCK (P_DEFINED | P_IDENT(GPIO_PG12) | P_FUNCT(0))
|
||||
#define P_SPI0_MISO (P_DEFINED | P_IDENT(GPIO_PG13) | P_FUNCT(0))
|
||||
#define P_SPI0_MOSI (P_DEFINED | P_IDENT(GPIO_PG14) | P_FUNCT(0))
|
||||
|
||||
#define P_SPI0_SSEL1 (P_DEFINED | P_IDENT(GPIO_PF7) | P_FUNCT(0))
|
||||
#define P_SPI0_SSEL2 (P_DEFINED | P_IDENT(GPIO_PG15) | P_FUNCT(0))
|
||||
#define P_SPI0_SSEL3 (P_DEFINED | P_IDENT(GPIO_PH4) | P_FUNCT(2))
|
||||
#define P_SPI0_SSEL4 (P_DEFINED | P_IDENT(GPIO_PG10) | P_FUNCT(2))
|
||||
#define P_SPI0_SSEL5 (P_DEFINED | P_IDENT(GPIO_PG3) | P_FUNCT(2))
|
||||
|
||||
#define P_SPI1_SS (P_DEFINED | P_IDENT(GPIO_PH0) | P_FUNCT(1))
|
||||
#define P_SPI1_SCK (P_DEFINED | P_IDENT(GPIO_PH1) | P_FUNCT(1))
|
||||
#define P_SPI1_MISO (P_DEFINED | P_IDENT(GPIO_PH2) | P_FUNCT(1))
|
||||
#define P_SPI1_MOSI (P_DEFINED | P_IDENT(GPIO_PH3) | P_FUNCT(1))
|
||||
|
||||
#define P_SPI1_SSEL1 (P_DEFINED | P_IDENT(GPIO_PH6) | P_FUNCT(2))
|
||||
#define P_SPI1_SSEL2 (P_DEFINED | P_IDENT(GPIO_PF0) | P_FUNCT(2))
|
||||
#define P_SPI1_SSEL3 (P_DEFINED | P_IDENT(GPIO_PG0) | P_FUNCT(2))
|
||||
#define P_SPI1_SSEL4 (P_DEFINED | P_IDENT(GPIO_PF8) | P_FUNCT(2))
|
||||
#define P_SPI1_SSEL5 (P_DEFINED | P_IDENT(GPIO_PG11) | P_FUNCT(2))
|
||||
|
||||
/* SPORT Port Mux */
|
||||
#define P_SPORT0_DRPRI (P_DEFINED | P_IDENT(GPIO_PG3) | P_FUNCT(0))
|
||||
#define P_SPORT0_RSCLK (P_DEFINED | P_IDENT(GPIO_PG4) | P_FUNCT(0))
|
||||
#define P_SPORT0_RFS (P_DEFINED | P_IDENT(GPIO_PG5) | P_FUNCT(0))
|
||||
#define P_SPORT0_TFS (P_DEFINED | P_IDENT(GPIO_PG6) | P_FUNCT(0))
|
||||
#define P_SPORT0_DTPRI (P_DEFINED | P_IDENT(GPIO_PG7) | P_FUNCT(0))
|
||||
#define P_SPORT0_TSCLK (P_DEFINED | P_IDENT(GPIO_PG8) | P_FUNCT(0))
|
||||
#define P_SPORT0_DTSEC (P_DEFINED | P_IDENT(GPIO_PG9) | P_FUNCT(0))
|
||||
#define P_SPORT0_DRSEC (P_DEFINED | P_IDENT(GPIO_PG10) | P_FUNCT(0))
|
||||
|
||||
#define P_SPORT1_DRPRI (P_DEFINED | P_IDENT(GPIO_PH0) | P_FUNCT(0))
|
||||
#define P_SPORT1_RFS (P_DEFINED | P_IDENT(GPIO_PH1) | P_FUNCT(0))
|
||||
#define P_SPORT1_RSCLK (P_DEFINED | P_IDENT(GPIO_PH2) | P_FUNCT(0))
|
||||
#define P_SPORT1_DTPRI (P_DEFINED | P_IDENT(GPIO_PH3) | P_FUNCT(0))
|
||||
#define P_SPORT1_TFS (P_DEFINED | P_IDENT(GPIO_PH4) | P_FUNCT(0))
|
||||
#define P_SPORT1_TSCLK (P_DEFINED | P_IDENT(GPIO_PH5) | P_FUNCT(0))
|
||||
#define P_SPORT1_DTSEC (P_DEFINED | P_IDENT(GPIO_PH6) | P_FUNCT(0))
|
||||
#define P_SPORT1_DRSEC (P_DEFINED | P_IDENT(GPIO_PH7) | P_FUNCT(0))
|
||||
|
||||
/* UART Port Mux */
|
||||
#define P_UART0_TX (P_DEFINED | P_IDENT(GPIO_PG9) | P_FUNCT(1))
|
||||
#define P_UART0_RX (P_DEFINED | P_IDENT(GPIO_PG10) | P_FUNCT(1))
|
||||
|
||||
#define P_UART1_TX (P_DEFINED | P_IDENT(GPIO_PH6) | P_FUNCT(1))
|
||||
#define P_UART1_RX (P_DEFINED | P_IDENT(GPIO_PH7) | P_FUNCT(1))
|
||||
|
||||
/* Timer */
|
||||
#define P_TMRCLK (P_DEFINED | P_IDENT(GPIO_PG5) | P_FUNCT(2))
|
||||
#define P_TMR0 (P_DEFINED | P_IDENT(GPIO_PG6) | P_FUNCT(2))
|
||||
#define P_TMR1 (P_DEFINED | P_IDENT(GPIO_PG7) | P_FUNCT(2))
|
||||
#define P_TMR2 (P_DEFINED | P_IDENT(GPIO_PF9) | P_FUNCT(2))
|
||||
#define P_TMR3 (P_DEFINED | P_IDENT(GPIO_PF10) | P_FUNCT(2))
|
||||
#define P_TMR4 (P_DEFINED | P_IDENT(GPIO_PG9) | P_FUNCT(2))
|
||||
#define P_TMR5 (P_DEFINED | P_IDENT(GPIO_PG4) | P_FUNCT(2))
|
||||
#define P_TMR6 (P_DEFINED | P_IDENT(GPIO_PG8) | P_FUNCT(2))
|
||||
#define P_TMR7 (P_DEFINED | P_IDENT(GPIO_PH7) | P_FUNCT(2))
|
||||
|
||||
/* DMA */
|
||||
#define P_DMAR1 (P_DEFINED | P_IDENT(GPIO_PG1) | P_FUNCT(1))
|
||||
#define P_DMAR0 (P_DEFINED | P_IDENT(GPIO_PG2) | P_FUNCT(1))
|
||||
|
||||
/* TWI */
|
||||
#define P_TWI0_SCL (P_DONTCARE)
|
||||
#define P_TWI0_SDA (P_DONTCARE)
|
||||
|
||||
/* PWM */
|
||||
#define P_PWM0_AH (P_DEFINED | P_IDENT(GPIO_PF1) | P_FUNCT(2))
|
||||
#define P_PWM0_AL (P_DEFINED | P_IDENT(GPIO_PF2) | P_FUNCT(2))
|
||||
#define P_PWM0_BH (P_DEFINED | P_IDENT(GPIO_PF3) | P_FUNCT(2))
|
||||
#define P_PWM0_BL (P_DEFINED | P_IDENT(GPIO_PF4) | P_FUNCT(2))
|
||||
#define P_PWM0_CH (P_DEFINED | P_IDENT(GPIO_PF5) | P_FUNCT(2))
|
||||
#define P_PWM0_CL (P_DEFINED | P_IDENT(GPIO_PF6) | P_FUNCT(2))
|
||||
#define P_PWM0_SYNC (P_DEFINED | P_IDENT(GPIO_PF7) | P_FUNCT(2))
|
||||
|
||||
#define P_PWM1_AH (P_DEFINED | P_IDENT(GPIO_PF11) | P_FUNCT(2))
|
||||
#define P_PWM1_AL (P_DEFINED | P_IDENT(GPIO_PF12) | P_FUNCT(2))
|
||||
#define P_PWM1_BH (P_DEFINED | P_IDENT(GPIO_PF13) | P_FUNCT(2))
|
||||
#define P_PWM1_BL (P_DEFINED | P_IDENT(GPIO_PF14) | P_FUNCT(2))
|
||||
#define P_PWM1_CH (P_DEFINED | P_IDENT(GPIO_PG1) | P_FUNCT(2))
|
||||
#define P_PWM1_CL (P_DEFINED | P_IDENT(GPIO_PG2) | P_FUNCT(2))
|
||||
#define P_PWM1_SYNC (P_DEFINED | P_IDENT(GPIO_PF15) | P_FUNCT(2))
|
||||
|
||||
#define P_PWM_TRIPB (P_DEFINED | P_IDENT(GPIO_PG14) | P_FUNCT(2))
|
||||
|
||||
/* RSI */
|
||||
#define P_RSI_DATA0 (P_DEFINED | P_IDENT(GPIO_PG3) | P_FUNCT(1))
|
||||
#define P_RSI_DATA1 (P_DEFINED | P_IDENT(GPIO_PG4) | P_FUNCT(1))
|
||||
#define P_RSI_DATA2 (P_DEFINED | P_IDENT(GPIO_PG5) | P_FUNCT(1))
|
||||
#define P_RSI_DATA3 (P_DEFINED | P_IDENT(GPIO_PG6) | P_FUNCT(1))
|
||||
#define P_RSI_DATA4 (P_DEFINED | P_IDENT(GPIO_PH0) | P_FUNCT(2))
|
||||
#define P_RSI_DATA5 (P_DEFINED | P_IDENT(GPIO_PH1) | P_FUNCT(2))
|
||||
#define P_RSI_DATA6 (P_DEFINED | P_IDENT(GPIO_PH2) | P_FUNCT(2))
|
||||
#define P_RSI_DATA7 (P_DEFINED | P_IDENT(GPIO_PH3) | P_FUNCT(2))
|
||||
#define P_RSI_CMD (P_DEFINED | P_IDENT(GPIO_PG7) | P_FUNCT(1))
|
||||
#define P_RSI_CLK (P_DEFINED | P_IDENT(GPIO_PG8) | P_FUNCT(1))
|
||||
|
||||
/* PTP */
|
||||
#define P_PTP_PPS (P_DEFINED | P_IDENT(GPIO_PG12) | P_FUNCT(2))
|
||||
#define P_PTP_CLKOUT (P_DEFINED | P_IDENT(GPIO_PG13) | P_FUNCT(2))
|
||||
|
||||
#define P_HWAIT (P_DEFINED | P_IDENT(GPIO_PG000000000) | P_FUNCT(1))
|
||||
|
||||
#endif /* _MACH_PORTMUX_H_ */
|
||||
|
|
@ -0,0 +1,99 @@
|
|||
/*
|
||||
* File: arch/blackfin/mach-bf518/ints-priority.c
|
||||
* Based on: arch/blackfin/mach-bf527/ints-priority.c
|
||||
* Author: Bryan Wu <cooloney@kernel.org>
|
||||
*
|
||||
* Created:
|
||||
* Description: Set up the interrupt priorities
|
||||
*
|
||||
* Modified:
|
||||
* Copyright 2004-2007 Analog Devices Inc.
|
||||
*
|
||||
* Bugs: Enter bugs at http://blackfin.uclinux.org/
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, see the file COPYING, or write
|
||||
* to the Free Software Foundation, Inc.,
|
||||
* 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
*/
|
||||
|
||||
#include <linux/module.h>
|
||||
#include <linux/irq.h>
|
||||
#include <asm/blackfin.h>
|
||||
|
||||
void __init program_IAR(void)
|
||||
{
|
||||
/* Program the IAR0 Register with the configured priority */
|
||||
bfin_write_SIC_IAR0(((CONFIG_IRQ_PLL_WAKEUP - 7) << IRQ_PLL_WAKEUP_POS) |
|
||||
((CONFIG_IRQ_DMA0_ERROR - 7) << IRQ_DMA0_ERROR_POS) |
|
||||
((CONFIG_IRQ_DMAR0_BLK - 7) << IRQ_DMAR0_BLK_POS) |
|
||||
((CONFIG_IRQ_DMAR1_BLK - 7) << IRQ_DMAR1_BLK_POS) |
|
||||
((CONFIG_IRQ_DMAR0_OVR - 7) << IRQ_DMAR0_OVR_POS) |
|
||||
((CONFIG_IRQ_DMAR1_OVR - 7) << IRQ_DMAR1_OVR_POS) |
|
||||
((CONFIG_IRQ_PPI_ERROR - 7) << IRQ_PPI_ERROR_POS) |
|
||||
((CONFIG_IRQ_MAC_ERROR - 7) << IRQ_MAC_ERROR_POS));
|
||||
|
||||
|
||||
bfin_write_SIC_IAR1(((CONFIG_IRQ_SPORT0_ERROR - 7) << IRQ_SPORT0_ERROR_POS) |
|
||||
((CONFIG_IRQ_SPORT1_ERROR - 7) << IRQ_SPORT1_ERROR_POS) |
|
||||
((CONFIG_IRQ_PTP_ERROR - 7) << IRQ_PTP_ERROR_POS) |
|
||||
((CONFIG_IRQ_UART0_ERROR - 7) << IRQ_UART0_ERROR_POS) |
|
||||
((CONFIG_IRQ_UART1_ERROR - 7) << IRQ_UART1_ERROR_POS) |
|
||||
((CONFIG_IRQ_RTC - 7) << IRQ_RTC_POS) |
|
||||
((CONFIG_IRQ_PPI - 7) << IRQ_PPI_POS));
|
||||
|
||||
bfin_write_SIC_IAR2(((CONFIG_IRQ_SPORT0_RX - 7) << IRQ_SPORT0_RX_POS) |
|
||||
((CONFIG_IRQ_SPORT0_TX - 7) << IRQ_SPORT0_TX_POS) |
|
||||
((CONFIG_IRQ_SPORT1_RX - 7) << IRQ_SPORT1_RX_POS) |
|
||||
((CONFIG_IRQ_SPORT1_TX - 7) << IRQ_SPORT1_TX_POS) |
|
||||
((CONFIG_IRQ_TWI - 7) << IRQ_TWI_POS) |
|
||||
((CONFIG_IRQ_SPI0 - 7) << IRQ_SPI0_POS) |
|
||||
((CONFIG_IRQ_UART0_RX - 7) << IRQ_UART0_RX_POS) |
|
||||
((CONFIG_IRQ_UART0_TX - 7) << IRQ_UART0_TX_POS));
|
||||
|
||||
bfin_write_SIC_IAR3(((CONFIG_IRQ_UART1_RX - 7) << IRQ_UART1_RX_POS) |
|
||||
((CONFIG_IRQ_UART1_TX - 7) << IRQ_UART1_TX_POS) |
|
||||
((CONFIG_IRQ_OPTSEC - 7) << IRQ_OPTSEC_POS) |
|
||||
((CONFIG_IRQ_CNT - 7) << IRQ_CNT_POS) |
|
||||
((CONFIG_IRQ_MAC_RX - 7) << IRQ_MAC_RX_POS) |
|
||||
((CONFIG_IRQ_PORTH_INTA - 7) << IRQ_PORTH_INTA_POS) |
|
||||
((CONFIG_IRQ_MAC_TX - 7) << IRQ_MAC_TX_POS) |
|
||||
((CONFIG_IRQ_PORTH_INTB - 7) << IRQ_PORTH_INTB_POS));
|
||||
|
||||
bfin_write_SIC_IAR4(((CONFIG_IRQ_TMR0 - 7) << IRQ_TMR0_POS) |
|
||||
((CONFIG_IRQ_TMR1 - 7) << IRQ_TMR1_POS) |
|
||||
((CONFIG_IRQ_TMR2 - 7) << IRQ_TMR2_POS) |
|
||||
((CONFIG_IRQ_TMR3 - 7) << IRQ_TMR3_POS) |
|
||||
((CONFIG_IRQ_TMR4 - 7) << IRQ_TMR4_POS) |
|
||||
((CONFIG_IRQ_TMR5 - 7) << IRQ_TMR5_POS) |
|
||||
((CONFIG_IRQ_TMR6 - 7) << IRQ_TMR6_POS) |
|
||||
((CONFIG_IRQ_TMR7 - 7) << IRQ_TMR7_POS));
|
||||
|
||||
bfin_write_SIC_IAR5(((CONFIG_IRQ_PORTG_INTA - 7) << IRQ_PORTG_INTA_POS) |
|
||||
((CONFIG_IRQ_PORTG_INTB - 7) << IRQ_PORTG_INTB_POS) |
|
||||
((CONFIG_IRQ_MEM_DMA0 - 7) << IRQ_MEM_DMA0_POS) |
|
||||
((CONFIG_IRQ_MEM_DMA1 - 7) << IRQ_MEM_DMA1_POS) |
|
||||
((CONFIG_IRQ_WATCH - 7) << IRQ_WATCH_POS) |
|
||||
((CONFIG_IRQ_PORTF_INTA - 7) << IRQ_PORTF_INTA_POS) |
|
||||
((CONFIG_IRQ_PORTF_INTB - 7) << IRQ_PORTF_INTB_POS) |
|
||||
((CONFIG_IRQ_SPI0_ERROR - 7) << IRQ_SPI0_ERROR_POS));
|
||||
|
||||
bfin_write_SIC_IAR6(((CONFIG_IRQ_SPI1_ERROR - 7) << IRQ_SPI1_ERROR_POS) |
|
||||
((CONFIG_IRQ_RSI_INT0 - 7) << IRQ_RSI_INT0_POS) |
|
||||
((CONFIG_IRQ_RSI_INT1 - 7) << IRQ_RSI_INT1_POS) |
|
||||
((CONFIG_IRQ_PWM_TRIP - 7) << IRQ_PWM_TRIP_POS) |
|
||||
((CONFIG_IRQ_PWM_SYNC - 7) << IRQ_PWM_SYNC_POS) |
|
||||
((CONFIG_IRQ_PTP_STAT - 7) << IRQ_PTP_STAT_POS));
|
||||
|
||||
SSYNC();
|
||||
}
|
||||
|
|
@ -248,7 +248,7 @@ ENDPROC(_unset_dram_srfs)
|
|||
|
||||
ENTRY(_set_sic_iwr)
|
||||
#if defined(CONFIG_BF54x) || defined(CONFIG_BF52x) || defined(CONFIG_BF561) || \
|
||||
defined(CONFIG_BF538) || defined(CONFIG_BF539)
|
||||
defined(CONFIG_BF538) || defined(CONFIG_BF539) || defined(CONFIG_BF51x)
|
||||
P0.H = hi(SIC_IWR0);
|
||||
P0.L = lo(SIC_IWR0);
|
||||
P1.H = hi(SIC_IWR1);
|
||||
|
|
|
|||
|
|
@ -104,7 +104,8 @@ static void __init search_IAR(void)
|
|||
for (irqn = 0; irqn < NR_PERI_INTS; irqn++) {
|
||||
int iar_shift = (irqn & 7) * 4;
|
||||
if (ivg == (0xf &
|
||||
#if defined(CONFIG_BF52x) || defined(CONFIG_BF538) || defined(CONFIG_BF539)
|
||||
#if defined(CONFIG_BF52x) || defined(CONFIG_BF538) \
|
||||
|| defined(CONFIG_BF539) || defined(CONFIG_BF51x)
|
||||
bfin_read32((unsigned long *)SIC_IAR0 +
|
||||
((irqn % 32) >> 3) + ((irqn / 32) *
|
||||
((SIC_IAR4 - SIC_IAR0) / 4))) >> iar_shift)) {
|
||||
|
|
@ -543,7 +544,7 @@ static void bfin_demux_gpio_irq(unsigned int inta_irq,
|
|||
case IRQ_PORTF_INTA:
|
||||
irq = IRQ_PF0;
|
||||
break;
|
||||
#elif defined(CONFIG_BF52x)
|
||||
#elif defined(CONFIG_BF52x) || defined(CONFIG_BF51x)
|
||||
case IRQ_PORTF_INTA:
|
||||
irq = IRQ_PF0;
|
||||
break;
|
||||
|
|
@ -990,7 +991,8 @@ int __init init_arch_irq(void)
|
|||
int irq;
|
||||
unsigned long ilat = 0;
|
||||
/* Disable all the peripheral intrs - page 4-29 HW Ref manual */
|
||||
#if defined(CONFIG_BF54x) || defined(CONFIG_BF52x) || defined(CONFIG_BF561) || defined(BF538_FAMILY)
|
||||
#if defined(CONFIG_BF54x) || defined(CONFIG_BF52x) || defined(CONFIG_BF561) \
|
||||
|| defined(BF538_FAMILY) || defined(CONFIG_BF51x)
|
||||
bfin_write_SIC_IMASK0(SIC_UNMASK_ALL);
|
||||
bfin_write_SIC_IMASK1(SIC_UNMASK_ALL);
|
||||
# ifdef CONFIG_BF54x
|
||||
|
|
@ -1035,7 +1037,7 @@ int __init init_arch_irq(void)
|
|||
case IRQ_PINT1:
|
||||
case IRQ_PINT2:
|
||||
case IRQ_PINT3:
|
||||
#elif defined(CONFIG_BF52x)
|
||||
#elif defined(CONFIG_BF52x) || defined(CONFIG_BF51x)
|
||||
case IRQ_PORTF_INTA:
|
||||
case IRQ_PORTG_INTA:
|
||||
case IRQ_PORTH_INTA:
|
||||
|
|
@ -1094,10 +1096,11 @@ int __init init_arch_irq(void)
|
|||
IMASK_IVG14 | IMASK_IVG13 | IMASK_IVG12 | IMASK_IVG11 |
|
||||
IMASK_IVG10 | IMASK_IVG9 | IMASK_IVG8 | IMASK_IVG7 | IMASK_IVGHW;
|
||||
|
||||
#if defined(CONFIG_BF54x) || defined(CONFIG_BF52x) || defined(CONFIG_BF561) || defined(BF538_FAMILY)
|
||||
#if defined(CONFIG_BF54x) || defined(CONFIG_BF52x) || defined(CONFIG_BF561) \
|
||||
|| defined(BF538_FAMILY) || defined(CONFIG_BF51x)
|
||||
bfin_write_SIC_IWR0(IWR_DISABLE_ALL);
|
||||
#if defined(CONFIG_BF52x)
|
||||
/* BF52x system reset does not properly reset SIC_IWR1 which
|
||||
#if defined(CONFIG_BF52x) || defined(CONFIG_BF51x)
|
||||
/* BF52x/BF51x system reset does not properly reset SIC_IWR1 which
|
||||
* will screw up the bootrom as it relies on MDMA0/1 waking it
|
||||
* up from IDLE instructions. See this report for more info:
|
||||
* http://blackfin.uclinux.org/gf/tracker/4323
|
||||
|
|
@ -1126,7 +1129,8 @@ void do_irq(int vec, struct pt_regs *fp)
|
|||
} else {
|
||||
struct ivgx *ivg = ivg7_13[vec - IVG7].ifirst;
|
||||
struct ivgx *ivg_stop = ivg7_13[vec - IVG7].istop;
|
||||
#if defined(CONFIG_BF54x) || defined(CONFIG_BF52x) || defined(CONFIG_BF561) || defined(BF538_FAMILY)
|
||||
#if defined(CONFIG_BF54x) || defined(CONFIG_BF52x) || defined(CONFIG_BF561) \
|
||||
|| defined(BF538_FAMILY) || defined(CONFIG_BF51x)
|
||||
unsigned long sic_status[3];
|
||||
|
||||
sic_status[0] = bfin_read_SIC_ISR0() & bfin_read_SIC_IMASK0();
|
||||
|
|
|
|||
|
|
@ -83,9 +83,9 @@ void bfin_pm_suspend_standby_enter(void)
|
|||
bfin_pm_standby_restore();
|
||||
|
||||
#if defined(CONFIG_BF54x) || defined(CONFIG_BF52x) || defined(CONFIG_BF561) || \
|
||||
defined(CONFIG_BF538) || defined(CONFIG_BF539)
|
||||
defined(CONFIG_BF538) || defined(CONFIG_BF539) || defined(CONFIG_BF51x)
|
||||
bfin_write_SIC_IWR0(IWR_DISABLE_ALL);
|
||||
#if defined(CONFIG_BF52x)
|
||||
#if defined(CONFIG_BF52x) || defined(CONFIG_BF51x)
|
||||
/* BF52x system reset does not properly reset SIC_IWR1 which
|
||||
* will screw up the bootrom as it relies on MDMA0/1 waking it
|
||||
* up from IDLE instructions. See this report for more info:
|
||||
|
|
|
|||
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