ncr5380: Sleep when polling, if possible
When in process context, sleep during polling if doing so won't add significant latency. In interrupt context or if the lock is held, poll briefly then give up. Keep both core drivers in sync. Calibrate busy-wait iterations to allow for variation in chip register access times between different 5380 hardware implementations. Signed-off-by: Finn Thain <fthain@telegraphics.com.au> Reviewed-by: Hannes Reinecke <hare@suse.com> Tested-by: Ondrej Zary <linux@rainbow-software.org> Tested-by: Michael Schmitz <schmitzmic@gmail.com> Signed-off-by: Martin K. Petersen <martin.petersen@oracle.com>
This commit is contained in:
Finn Thain
Martin K. Petersen
Родитель
0ad0eff98f
Коммит
2f854b82b0
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@ -293,44 +293,48 @@ static inline void initialize_SCp(struct scsi_cmnd *cmd)
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}
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/**
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* NCR5380_poll_politely - wait for NCR5380 status bits
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* @instance: controller to poll
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* @reg: 5380 register to poll
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* @bit: Bitmask to check
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* @val: Value required to exit
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* NCR5380_poll_politely - wait for chip register value
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* @instance: controller to poll
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* @reg: 5380 register to poll
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* @bit: Bitmask to check
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* @val: Value required to exit
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* @wait: Time-out in jiffies
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*
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* Polls the NCR5380 in a reasonably efficient manner waiting for
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* an event to occur, after a short quick poll we begin giving the
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* CPU back in non IRQ contexts
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* Polls the chip in a reasonably efficient manner waiting for an
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* event to occur. After a short quick poll we begin to yield the CPU
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* (if possible). In irq contexts the time-out is arbitrarily limited.
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* Callers may hold locks as long as they are held in irq mode.
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*
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* Returns the value of the register or a negative error code.
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* Returns 0 if event occurred otherwise -ETIMEDOUT.
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*/
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static int NCR5380_poll_politely(struct Scsi_Host *instance, int reg, int bit, int val, int t)
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{
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int n = 500; /* At about 8uS a cycle for the cpu access */
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unsigned long end = jiffies + t;
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int r;
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while( n-- > 0)
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{
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r = NCR5380_read(reg);
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if((r & bit) == val)
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static int NCR5380_poll_politely(struct Scsi_Host *instance,
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int reg, int bit, int val, int wait)
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{
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struct NCR5380_hostdata *hostdata = shost_priv(instance);
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unsigned long deadline = jiffies + wait;
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unsigned long n;
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/* Busy-wait for up to 10 ms */
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n = min(10000U, jiffies_to_usecs(wait));
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n *= hostdata->accesses_per_ms;
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n /= 1000;
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do {
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if ((NCR5380_read(reg) & bit) == val)
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return 0;
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cpu_relax();
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}
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/* t time yet ? */
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while(time_before(jiffies, end))
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{
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r = NCR5380_read(reg);
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if((r & bit) == val)
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} while (n--);
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if (irqs_disabled() || in_interrupt())
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return -ETIMEDOUT;
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/* Repeatedly sleep for 1 ms until deadline */
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while (time_is_after_jiffies(deadline)) {
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schedule_timeout_uninterruptible(1);
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if ((NCR5380_read(reg) & bit) == val)
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return 0;
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if(!in_interrupt())
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cond_resched();
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else
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cpu_relax();
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}
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return -ETIMEDOUT;
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}
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@ -773,6 +777,7 @@ static int NCR5380_init(struct Scsi_Host *instance, int flags)
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{
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int i;
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struct NCR5380_hostdata *hostdata = (struct NCR5380_hostdata *) instance->hostdata;
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unsigned long deadline;
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if(in_interrupt())
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printk(KERN_ERR "NCR5380_init called with interrupts off!\n");
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@ -812,6 +817,21 @@ static int NCR5380_init(struct Scsi_Host *instance, int flags)
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NCR5380_write(MODE_REG, MR_BASE);
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NCR5380_write(TARGET_COMMAND_REG, 0);
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NCR5380_write(SELECT_ENABLE_REG, 0);
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/* Calibrate register polling loop */
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i = 0;
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deadline = jiffies + 1;
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do {
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cpu_relax();
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} while (time_is_after_jiffies(deadline));
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deadline += msecs_to_jiffies(256);
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do {
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NCR5380_read(STATUS_REG);
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++i;
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cpu_relax();
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} while (time_is_after_jiffies(deadline));
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hostdata->accesses_per_ms = i / 256;
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return 0;
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}
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@ -285,6 +285,7 @@ struct NCR5380_hostdata {
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unsigned spin_max_w;
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#endif
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struct workqueue_struct *work_q;
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unsigned long accesses_per_ms; /* chip register accesses per ms */
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};
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#ifdef __KERNEL__
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@ -479,43 +479,48 @@ static inline void initialize_SCp(struct scsi_cmnd *cmd)
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}
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/**
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* NCR5380_poll_politely - wait for NCR5380 status bits
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* NCR5380_poll_politely - wait for chip register value
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* @instance: controller to poll
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* @reg: 5380 register to poll
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* @bit: Bitmask to check
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* @val: Value required to exit
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* @wait: Time-out in jiffies
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*
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* Polls the NCR5380 in a reasonably efficient manner waiting for
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* an event to occur, after a short quick poll we begin giving the
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* CPU back in non IRQ contexts
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* Polls the chip in a reasonably efficient manner waiting for an
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* event to occur. After a short quick poll we begin to yield the CPU
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* (if possible). In irq contexts the time-out is arbitrarily limited.
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* Callers may hold locks as long as they are held in irq mode.
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*
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* Returns the value of the register or a negative error code.
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* Returns 0 if event occurred otherwise -ETIMEDOUT.
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*/
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static int NCR5380_poll_politely(struct Scsi_Host *instance,
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int reg, int bit, int val, int t)
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int reg, int bit, int val, int wait)
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{
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int n = 500;
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unsigned long end = jiffies + t;
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int r;
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struct NCR5380_hostdata *hostdata = shost_priv(instance);
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unsigned long deadline = jiffies + wait;
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unsigned long n;
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while (n-- > 0) {
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r = NCR5380_read(reg);
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if ((r & bit) == val)
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/* Busy-wait for up to 10 ms */
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n = min(10000U, jiffies_to_usecs(wait));
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n *= hostdata->accesses_per_ms;
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n /= 1000;
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do {
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if ((NCR5380_read(reg) & bit) == val)
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return 0;
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cpu_relax();
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} while (n--);
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if (irqs_disabled() || in_interrupt())
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return -ETIMEDOUT;
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/* Repeatedly sleep for 1 ms until deadline */
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while (time_is_after_jiffies(deadline)) {
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schedule_timeout_uninterruptible(1);
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if ((NCR5380_read(reg) & bit) == val)
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return 0;
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}
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/* t time yet ? */
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while (time_before(jiffies, end)) {
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r = NCR5380_read(reg);
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if ((r & bit) == val)
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return 0;
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if (!in_interrupt())
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cond_resched();
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else
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cpu_relax();
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}
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return -ETIMEDOUT;
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}
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@ -811,6 +816,7 @@ static int __init NCR5380_init(struct Scsi_Host *instance, int flags)
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{
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int i;
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SETUP_HOSTDATA(instance);
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unsigned long deadline;
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hostdata->host = instance;
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hostdata->id_mask = 1 << instance->this_id;
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@ -845,6 +851,20 @@ static int __init NCR5380_init(struct Scsi_Host *instance, int flags)
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NCR5380_write(TARGET_COMMAND_REG, 0);
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NCR5380_write(SELECT_ENABLE_REG, 0);
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/* Calibrate register polling loop */
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i = 0;
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deadline = jiffies + 1;
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do {
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cpu_relax();
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} while (time_is_after_jiffies(deadline));
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deadline += msecs_to_jiffies(256);
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do {
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NCR5380_read(STATUS_REG);
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++i;
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cpu_relax();
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} while (time_is_after_jiffies(deadline));
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hostdata->accesses_per_ms = i / 256;
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return 0;
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}
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