OMAP: GPIO: prepare for platform driver
Prepare for implementing GPIO as a platform driver. Modifies omap_gpio_init() to make use of omap_gpio_chip_init() and omap_gpio_mod_init(). omap_gpio_mod_init() does the module init by clearing the status register and initializing the GPIO control register. omap_gpio_chip_init() initializes the chip request, free, get, set and other function pointers and sets the gpio irq handler. This is only to reorganize the code so that the "omap gpio platform driver implementation patch" looks cleaner and better to review. Signed-off-by: Charulatha V <charu@ti.com> Acked-by: Kevin Hilman <khilman@deeprootsystems.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
This commit is contained in:
Varadarajan, Charulatha
Tony Lindgren
Родитель
c2cdaffe0b
Коммит
2fae7fbed0
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@ -190,14 +190,12 @@ struct gpio_bank {
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u32 suspend_wakeup;
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u32 saved_wakeup;
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#endif
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#ifdef CONFIG_ARCH_OMAP2PLUS
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u32 non_wakeup_gpios;
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u32 enabled_non_wakeup_gpios;
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u32 saved_datain;
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u32 saved_fallingdetect;
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u32 saved_risingdetect;
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#endif
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u32 level_mask;
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u32 toggle_mask;
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spinlock_t lock;
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@ -1718,10 +1716,125 @@ static void __init omap_gpio_show_rev(void)
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*/
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static struct lock_class_key gpio_lock_class;
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static void omap_gpio_mod_init(struct gpio_bank *bank, int id)
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{
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if (cpu_class_is_omap2()) {
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if (cpu_is_omap44xx()) {
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__raw_writel(0xffffffff, bank->base +
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OMAP4_GPIO_IRQSTATUSCLR0);
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__raw_writel(0x00000000, bank->base +
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OMAP4_GPIO_DEBOUNCENABLE);
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/* Initialize interface clk ungated, module enabled */
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__raw_writel(0, bank->base + OMAP4_GPIO_CTRL);
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} else if (cpu_is_omap34xx()) {
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__raw_writel(0x00000000, bank->base +
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OMAP24XX_GPIO_IRQENABLE1);
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__raw_writel(0xffffffff, bank->base +
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OMAP24XX_GPIO_IRQSTATUS1);
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__raw_writel(0x00000000, bank->base +
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OMAP24XX_GPIO_DEBOUNCE_EN);
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/* Initialize interface clk ungated, module enabled */
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__raw_writel(0, bank->base + OMAP24XX_GPIO_CTRL);
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} else if (cpu_is_omap24xx()) {
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static const u32 non_wakeup_gpios[] = {
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0xe203ffc0, 0x08700040
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};
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if (id < ARRAY_SIZE(non_wakeup_gpios))
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bank->non_wakeup_gpios = non_wakeup_gpios[id];
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}
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} else if (cpu_class_is_omap1()) {
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if (bank_is_mpuio(bank))
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__raw_writew(0xffff, bank->base
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+ OMAP_MPUIO_GPIO_MASKIT);
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if (cpu_is_omap15xx() && bank->method == METHOD_GPIO_1510) {
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__raw_writew(0xffff, bank->base
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+ OMAP1510_GPIO_INT_MASK);
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__raw_writew(0x0000, bank->base
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+ OMAP1510_GPIO_INT_STATUS);
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}
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if (cpu_is_omap16xx() && bank->method == METHOD_GPIO_1610) {
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__raw_writew(0x0000, bank->base
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+ OMAP1610_GPIO_IRQENABLE1);
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__raw_writew(0xffff, bank->base
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+ OMAP1610_GPIO_IRQSTATUS1);
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__raw_writew(0x0014, bank->base
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+ OMAP1610_GPIO_SYSCONFIG);
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/*
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* Enable system clock for GPIO module.
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* The CAM_CLK_CTRL *is* really the right place.
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*/
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omap_writel(omap_readl(ULPD_CAM_CLK_CTRL) | 0x04,
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ULPD_CAM_CLK_CTRL);
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}
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if (cpu_is_omap7xx() && bank->method == METHOD_GPIO_7XX) {
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__raw_writel(0xffffffff, bank->base
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+ OMAP7XX_GPIO_INT_MASK);
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__raw_writel(0x00000000, bank->base
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+ OMAP7XX_GPIO_INT_STATUS);
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}
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}
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}
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static void __init omap_gpio_chip_init(struct gpio_bank *bank)
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{
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int j, bank_width = 16;
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static int gpio;
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if (cpu_is_omap7xx() && bank->method == METHOD_GPIO_7XX)
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bank_width = 32; /* 7xx has 32-bit GPIOs */
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if ((bank->method == METHOD_GPIO_24XX) ||
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(bank->method == METHOD_GPIO_44XX))
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bank_width = 32;
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bank->mod_usage = 0;
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/*
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* REVISIT eventually switch from OMAP-specific gpio structs
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* over to the generic ones
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*/
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bank->chip.request = omap_gpio_request;
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bank->chip.free = omap_gpio_free;
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bank->chip.direction_input = gpio_input;
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bank->chip.get = gpio_get;
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bank->chip.direction_output = gpio_output;
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bank->chip.set_debounce = gpio_debounce;
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bank->chip.set = gpio_set;
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bank->chip.to_irq = gpio_2irq;
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if (bank_is_mpuio(bank)) {
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bank->chip.label = "mpuio";
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#ifdef CONFIG_ARCH_OMAP16XX
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bank->chip.dev = &omap_mpuio_device.dev;
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#endif
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bank->chip.base = OMAP_MPUIO(0);
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} else {
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bank->chip.label = "gpio";
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bank->chip.base = gpio;
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gpio += bank_width;
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}
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bank->chip.ngpio = bank_width;
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gpiochip_add(&bank->chip);
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for (j = bank->virtual_irq_start;
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j < bank->virtual_irq_start + bank_width; j++) {
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lockdep_set_class(&irq_desc[j].lock, &gpio_lock_class);
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set_irq_chip_data(j, bank);
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if (bank_is_mpuio(bank))
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set_irq_chip(j, &mpuio_irq_chip);
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else
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set_irq_chip(j, &gpio_irq_chip);
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set_irq_handler(j, handle_simple_irq);
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set_irq_flags(j, IRQF_VALID);
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}
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set_irq_chained_handler(bank->irq, gpio_irq_handler);
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set_irq_data(bank->irq, bank);
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}
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static int __init _omap_gpio_init(void)
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{
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int i;
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int gpio = 0;
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struct gpio_bank *bank;
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int bank_size = SZ_8K; /* Module 4KB + L4 4KB except on omap1 */
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char clk_name[11];
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@ -1828,7 +1941,6 @@ static int __init _omap_gpio_init(void)
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}
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#endif
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for (i = 0; i < gpio_bank_count; i++) {
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int j, gpio_count = 16;
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bank = &gpio_bank[i];
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spin_lock_init(&bank->lock);
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@ -1840,107 +1952,8 @@ static int __init _omap_gpio_init(void)
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continue;
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}
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if (bank_is_mpuio(bank))
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__raw_writew(0xffff, bank->base + OMAP_MPUIO_GPIO_MASKIT);
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if (cpu_is_omap15xx() && bank->method == METHOD_GPIO_1510) {
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__raw_writew(0xffff, bank->base + OMAP1510_GPIO_INT_MASK);
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__raw_writew(0x0000, bank->base + OMAP1510_GPIO_INT_STATUS);
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}
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if (cpu_is_omap16xx() && bank->method == METHOD_GPIO_1610) {
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__raw_writew(0x0000, bank->base + OMAP1610_GPIO_IRQENABLE1);
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__raw_writew(0xffff, bank->base + OMAP1610_GPIO_IRQSTATUS1);
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__raw_writew(0x0014, bank->base + OMAP1610_GPIO_SYSCONFIG);
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}
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if (cpu_is_omap7xx() && bank->method == METHOD_GPIO_7XX) {
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__raw_writel(0xffffffff, bank->base + OMAP7XX_GPIO_INT_MASK);
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__raw_writel(0x00000000, bank->base + OMAP7XX_GPIO_INT_STATUS);
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gpio_count = 32; /* 7xx has 32-bit GPIOs */
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}
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#ifdef CONFIG_ARCH_OMAP2PLUS
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if ((bank->method == METHOD_GPIO_24XX) ||
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(bank->method == METHOD_GPIO_44XX)) {
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static const u32 non_wakeup_gpios[] = {
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0xe203ffc0, 0x08700040
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};
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if (cpu_is_omap44xx()) {
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__raw_writel(0xffffffff, bank->base +
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OMAP4_GPIO_IRQSTATUSCLR0);
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__raw_writew(0x0015, bank->base +
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OMAP4_GPIO_SYSCONFIG);
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__raw_writel(0x00000000, bank->base +
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OMAP4_GPIO_DEBOUNCENABLE);
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/*
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* Initialize interface clock ungated,
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* module enabled
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*/
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__raw_writel(0, bank->base + OMAP4_GPIO_CTRL);
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} else {
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__raw_writel(0x00000000, bank->base +
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OMAP24XX_GPIO_IRQENABLE1);
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__raw_writel(0xffffffff, bank->base +
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OMAP24XX_GPIO_IRQSTATUS1);
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__raw_writew(0x0015, bank->base +
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OMAP24XX_GPIO_SYSCONFIG);
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__raw_writel(0x00000000, bank->base +
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OMAP24XX_GPIO_DEBOUNCE_EN);
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/*
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* Initialize interface clock ungated,
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* module enabled
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*/
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__raw_writel(0, bank->base +
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OMAP24XX_GPIO_CTRL);
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}
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if (cpu_is_omap24xx() &&
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i < ARRAY_SIZE(non_wakeup_gpios))
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bank->non_wakeup_gpios = non_wakeup_gpios[i];
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gpio_count = 32;
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}
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#endif
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bank->mod_usage = 0;
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/* REVISIT eventually switch from OMAP-specific gpio structs
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* over to the generic ones
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*/
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bank->chip.request = omap_gpio_request;
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bank->chip.free = omap_gpio_free;
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bank->chip.direction_input = gpio_input;
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bank->chip.get = gpio_get;
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bank->chip.direction_output = gpio_output;
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bank->chip.set_debounce = gpio_debounce;
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bank->chip.set = gpio_set;
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bank->chip.to_irq = gpio_2irq;
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if (bank_is_mpuio(bank)) {
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bank->chip.label = "mpuio";
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#ifdef CONFIG_ARCH_OMAP16XX
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bank->chip.dev = &omap_mpuio_device.dev;
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#endif
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bank->chip.base = OMAP_MPUIO(0);
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} else {
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bank->chip.label = "gpio";
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bank->chip.base = gpio;
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gpio += gpio_count;
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}
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bank->chip.ngpio = gpio_count;
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gpiochip_add(&bank->chip);
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for (j = bank->virtual_irq_start;
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j < bank->virtual_irq_start + gpio_count; j++) {
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lockdep_set_class(&irq_desc[j].lock, &gpio_lock_class);
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set_irq_chip_data(j, bank);
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if (bank_is_mpuio(bank))
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set_irq_chip(j, &mpuio_irq_chip);
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else
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set_irq_chip(j, &gpio_irq_chip);
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set_irq_handler(j, handle_simple_irq);
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set_irq_flags(j, IRQF_VALID);
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}
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set_irq_chained_handler(bank->irq, gpio_irq_handler);
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set_irq_data(bank->irq, bank);
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omap_gpio_mod_init(bank, i);
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omap_gpio_chip_init(bank);
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if (cpu_is_omap34xx() || cpu_is_omap44xx()) {
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sprintf(clk_name, "gpio%d_dbck", i + 1);
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@ -1950,17 +1963,6 @@ static int __init _omap_gpio_init(void)
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}
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}
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/* Enable system clock for GPIO module.
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* The CAM_CLK_CTRL *is* really the right place. */
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if (cpu_is_omap16xx())
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omap_writel(omap_readl(ULPD_CAM_CLK_CTRL) | 0x04, ULPD_CAM_CLK_CTRL);
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/* Enable autoidle for the OCP interface */
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if (cpu_is_omap24xx())
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omap_writel(1 << 0, 0x48019010);
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if (cpu_is_omap34xx())
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omap_writel(1 << 0, 0x48306814);
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omap_gpio_show_rev();
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return 0;
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