net: dsa: sja1105: Switch to hardware operations for PTP
Adjusting the hardware clock (PTPCLKVAL, PTPCLKADD, PTPCLKRATE) is a requirement for the auxiliary PTP functionality of the switch (TTEthernet, PPS input, PPS output). Therefore we need to switch to using these registers to keep a synchronized time in hardware, instead of the timecounter/cyclecounter implementation, which is reliant on the free-running PTPTSCLK. Signed-off-by: Vladimir Oltean <olteanv@gmail.com> Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
Vladimir Oltean
David S. Miller
Родитель
d9496f3ecf
Коммит
2fb079a28a
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@ -33,9 +33,8 @@ struct sja1105_regs {
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u64 config;
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u64 rmii_pll1;
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u64 ptp_control;
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u64 ptpclk;
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u64 ptpclkval;
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u64 ptpclkrate;
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u64 ptptsclk;
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u64 ptpegr_ts[SJA1105_NUM_PORTS];
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u64 pad_mii_tx[SJA1105_NUM_PORTS];
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u64 pad_mii_id[SJA1105_NUM_PORTS];
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@ -13,24 +13,6 @@
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#define SJA1105_MAX_ADJ_PPB 32000000
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#define SJA1105_SIZE_PTP_CMD 4
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/* Timestamps are in units of 8 ns clock ticks (equivalent to a fixed
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* 125 MHz clock) so the scale factor (MULT / SHIFT) needs to be 8.
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* Furthermore, wisely pick SHIFT as 28 bits, which translates
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* MULT into 2^31 (0x80000000). This is the same value around which
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* the hardware PTPCLKRATE is centered, so the same ppb conversion
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* arithmetic can be reused.
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*/
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#define SJA1105_CC_SHIFT 28
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#define SJA1105_CC_MULT (8 << SJA1105_CC_SHIFT)
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/* Having 33 bits of cycle counter left until a 64-bit overflow during delta
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* conversion, we multiply this by the 8 ns counter resolution and arrive at
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* a comfortable 68.71 second refresh interval until the delta would cause
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* an integer overflow, in absence of any other readout.
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* Approximate to 1 minute.
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*/
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#define SJA1105_REFRESH_INTERVAL (HZ * 60)
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/* This range is actually +/- SJA1105_MAX_ADJ_PPB
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* divided by 1000 (ppb -> ppm) and with a 16-bit
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* "fractional" part (actually fixed point).
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@ -41,7 +23,7 @@
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*
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* This forgoes a "ppb" numeric representation (up to NSEC_PER_SEC)
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* and defines the scaling factor between scaled_ppm and the actual
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* frequency adjustments (both cycle counter and hardware).
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* frequency adjustments of the PHC.
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*
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* ptpclkrate = scaled_ppm * 2^31 / (10^6 * 2^16)
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* simplifies to
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@ -49,13 +31,15 @@
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*/
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#define SJA1105_CC_MULT_NUM (1 << 9)
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#define SJA1105_CC_MULT_DEM 15625
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#define SJA1105_CC_MULT 0x80000000
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enum sja1105_ptp_clk_mode {
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PTP_ADD_MODE = 1,
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PTP_SET_MODE = 0,
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};
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#define ptp_caps_to_data(d) \
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container_of((d), struct sja1105_ptp_data, caps)
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#define cc_to_ptp_data(d) \
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container_of((d), struct sja1105_ptp_data, tstamp_cc)
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#define dw_to_ptp_data(d) \
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container_of((d), struct sja1105_ptp_data, refresh_work)
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#define ptp_data_to_sja1105(d) \
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container_of((d), struct sja1105_private, ptp_data)
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@ -220,6 +204,8 @@ int sja1105et_ptp_cmd(const struct dsa_switch *ds,
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sja1105_pack(buf, &valid, 31, 31, size);
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sja1105_pack(buf, &cmd->resptp, 2, 2, size);
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sja1105_pack(buf, &cmd->corrclk4ts, 1, 1, size);
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sja1105_pack(buf, &cmd->ptpclkadd, 0, 0, size);
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return sja1105_xfer_buf(priv, SPI_WRITE, regs->ptp_control, buf,
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SJA1105_SIZE_PTP_CMD);
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@ -237,6 +223,8 @@ int sja1105pqrs_ptp_cmd(const struct dsa_switch *ds,
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sja1105_pack(buf, &valid, 31, 31, size);
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sja1105_pack(buf, &cmd->resptp, 3, 3, size);
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sja1105_pack(buf, &cmd->corrclk4ts, 2, 2, size);
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sja1105_pack(buf, &cmd->ptpclkadd, 0, 0, size);
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return sja1105_xfer_buf(priv, SPI_WRITE, regs->ptp_control, buf,
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SJA1105_SIZE_PTP_CMD);
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@ -346,6 +334,22 @@ static int sja1105_ptpegr_ts_poll(struct dsa_switch *ds, int port, u64 *ts)
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return 0;
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}
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/* Caller must hold ptp_data->lock */
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static int sja1105_ptpclkval_read(struct sja1105_private *priv, u64 *ticks)
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{
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const struct sja1105_regs *regs = priv->info->regs;
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return sja1105_xfer_u64(priv, SPI_READ, regs->ptpclkval, ticks);
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}
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/* Caller must hold ptp_data->lock */
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static int sja1105_ptpclkval_write(struct sja1105_private *priv, u64 ticks)
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{
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const struct sja1105_regs *regs = priv->info->regs;
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return sja1105_xfer_u64(priv, SPI_WRITE, regs->ptpclkval, &ticks);
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}
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#define rxtstamp_to_tagger(d) \
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container_of((d), struct sja1105_tagger_data, rxtstamp_work)
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#define tagger_to_sja1105(d) \
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@ -363,17 +367,22 @@ static void sja1105_rxtstamp_work(struct work_struct *work)
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while ((skb = skb_dequeue(&tagger_data->skb_rxtstamp_queue)) != NULL) {
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struct skb_shared_hwtstamps *shwt = skb_hwtstamps(skb);
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u64 now, ts;
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u64 ticks, ts;
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int rc;
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now = ptp_data->tstamp_cc.read(&ptp_data->tstamp_cc);
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rc = sja1105_ptpclkval_read(priv, &ticks);
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if (rc < 0) {
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dev_err(ds->dev, "Failed to read PTP clock: %d\n", rc);
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kfree_skb(skb);
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continue;
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}
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*shwt = (struct skb_shared_hwtstamps) {0};
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ts = SJA1105_SKB_CB(skb)->meta_tstamp;
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ts = sja1105_tstamp_reconstruct(ds, now, ts);
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ts = timecounter_cyc2time(&ptp_data->tstamp_tc, ts);
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ts = sja1105_tstamp_reconstruct(ds, ticks, ts);
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shwt->hwtstamp = ns_to_ktime(ts);
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shwt->hwtstamp = ns_to_ktime(sja1105_ticks_to_ns(ts));
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netif_rx_ni(skb);
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}
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@ -427,9 +436,6 @@ int sja1105_ptp_reset(struct dsa_switch *ds)
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dev_dbg(ds->dev, "Resetting PTP clock\n");
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rc = priv->info->ptp_cmd(ds, &cmd);
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timecounter_init(&ptp_data->tstamp_tc, &ptp_data->tstamp_cc,
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ktime_to_ns(ktime_get_real()));
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mutex_unlock(&ptp_data->lock);
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return rc;
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@ -439,112 +445,106 @@ static int sja1105_ptp_gettime(struct ptp_clock_info *ptp,
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struct timespec64 *ts)
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{
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struct sja1105_ptp_data *ptp_data = ptp_caps_to_data(ptp);
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u64 ns;
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struct sja1105_private *priv = ptp_data_to_sja1105(ptp_data);
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u64 ticks = 0;
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int rc;
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mutex_lock(&ptp_data->lock);
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ns = timecounter_read(&ptp_data->tstamp_tc);
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rc = sja1105_ptpclkval_read(priv, &ticks);
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*ts = ns_to_timespec64(sja1105_ticks_to_ns(ticks));
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mutex_unlock(&ptp_data->lock);
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*ts = ns_to_timespec64(ns);
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return 0;
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return rc;
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}
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/* Caller must hold ptp_data->lock */
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static int sja1105_ptp_mode_set(struct sja1105_private *priv,
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enum sja1105_ptp_clk_mode mode)
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{
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struct sja1105_ptp_data *ptp_data = &priv->ptp_data;
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if (ptp_data->cmd.ptpclkadd == mode)
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return 0;
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ptp_data->cmd.ptpclkadd = mode;
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return priv->info->ptp_cmd(priv->ds, &ptp_data->cmd);
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}
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/* Write to PTPCLKVAL while PTPCLKADD is 0 */
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static int sja1105_ptp_settime(struct ptp_clock_info *ptp,
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const struct timespec64 *ts)
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{
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struct sja1105_ptp_data *ptp_data = ptp_caps_to_data(ptp);
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u64 ns = timespec64_to_ns(ts);
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struct sja1105_private *priv = ptp_data_to_sja1105(ptp_data);
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u64 ticks = ns_to_sja1105_ticks(timespec64_to_ns(ts));
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int rc;
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mutex_lock(&ptp_data->lock);
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timecounter_init(&ptp_data->tstamp_tc, &ptp_data->tstamp_cc, ns);
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rc = sja1105_ptp_mode_set(priv, PTP_SET_MODE);
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if (rc < 0) {
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dev_err(priv->ds->dev, "Failed to put PTPCLK in set mode\n");
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goto out;
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}
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rc = sja1105_ptpclkval_write(priv, ticks);
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out:
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mutex_unlock(&ptp_data->lock);
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return 0;
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return rc;
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}
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static int sja1105_ptp_adjfine(struct ptp_clock_info *ptp, long scaled_ppm)
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{
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struct sja1105_ptp_data *ptp_data = ptp_caps_to_data(ptp);
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struct sja1105_private *priv = ptp_data_to_sja1105(ptp_data);
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const struct sja1105_regs *regs = priv->info->regs;
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u32 clkrate32;
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s64 clkrate;
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int rc;
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clkrate = (s64)scaled_ppm * SJA1105_CC_MULT_NUM;
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clkrate = div_s64(clkrate, SJA1105_CC_MULT_DEM);
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/* Take a +/- value and re-center it around 2^31. */
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clkrate = SJA1105_CC_MULT + clkrate;
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WARN_ON(abs(clkrate) >= GENMASK_ULL(31, 0));
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clkrate32 = clkrate;
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mutex_lock(&ptp_data->lock);
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/* Force a readout to update the timer *before* changing its frequency.
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*
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* This way, its corrected time curve can at all times be modeled
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* as a linear "A * x + B" function, where:
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*
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* - B are past frequency adjustments and offset shifts, all
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* accumulated into the cycle_last variable.
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*
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* - A is the new frequency adjustments we're just about to set.
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*
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* Reading now makes B accumulate the correct amount of time,
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* corrected at the old rate, before changing it.
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*
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* Hardware timestamps then become simple points on the curve and
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* are approximated using the above function. This is still better
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* than letting the switch take the timestamps using the hardware
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* rate-corrected clock (PTPCLKVAL) - the comparison in this case would
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* be that we're shifting the ruler at the same time as we're taking
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* measurements with it.
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*
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* The disadvantage is that it's possible to receive timestamps when
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* a frequency adjustment took place in the near past.
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* In this case they will be approximated using the new ppb value
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* instead of a compound function made of two segments (one at the old
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* and the other at the new rate) - introducing some inaccuracy.
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*/
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timecounter_read(&ptp_data->tstamp_tc);
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ptp_data->tstamp_cc.mult = SJA1105_CC_MULT + clkrate;
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rc = sja1105_xfer_u32(priv, SPI_WRITE, regs->ptpclkrate, &clkrate32);
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mutex_unlock(&ptp_data->lock);
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return 0;
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return rc;
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}
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/* Write to PTPCLKVAL while PTPCLKADD is 1 */
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static int sja1105_ptp_adjtime(struct ptp_clock_info *ptp, s64 delta)
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{
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struct sja1105_ptp_data *ptp_data = ptp_caps_to_data(ptp);
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mutex_lock(&ptp_data->lock);
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timecounter_adjtime(&ptp_data->tstamp_tc, delta);
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mutex_unlock(&ptp_data->lock);
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return 0;
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}
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static u64 sja1105_ptptsclk_read(const struct cyclecounter *cc)
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{
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struct sja1105_ptp_data *ptp_data = cc_to_ptp_data(cc);
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struct sja1105_private *priv = ptp_data_to_sja1105(ptp_data);
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const struct sja1105_regs *regs = priv->info->regs;
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u64 ptptsclk = 0;
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s64 ticks = ns_to_sja1105_ticks(delta);
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int rc;
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rc = sja1105_xfer_u64(priv, SPI_READ, regs->ptptsclk, &ptptsclk);
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if (rc < 0)
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dev_err_ratelimited(priv->ds->dev,
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"failed to read ptp cycle counter: %d\n",
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rc);
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return ptptsclk;
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}
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mutex_lock(&ptp_data->lock);
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static void sja1105_ptp_overflow_check(struct work_struct *work)
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{
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struct delayed_work *dw = to_delayed_work(work);
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struct sja1105_ptp_data *ptp_data = dw_to_ptp_data(dw);
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struct timespec64 ts;
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rc = sja1105_ptp_mode_set(priv, PTP_ADD_MODE);
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if (rc < 0) {
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dev_err(priv->ds->dev, "Failed to put PTPCLK in add mode\n");
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goto out;
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}
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sja1105_ptp_gettime(&ptp_data->caps, &ts);
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rc = sja1105_ptpclkval_write(priv, ticks);
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schedule_delayed_work(&ptp_data->refresh_work,
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SJA1105_REFRESH_INTERVAL);
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out:
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mutex_unlock(&ptp_data->lock);
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return rc;
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}
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int sja1105_ptp_clock_register(struct dsa_switch *ds)
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@ -553,13 +553,6 @@ int sja1105_ptp_clock_register(struct dsa_switch *ds)
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struct sja1105_tagger_data *tagger_data = &priv->tagger_data;
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struct sja1105_ptp_data *ptp_data = &priv->ptp_data;
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/* Set up the cycle counter */
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ptp_data->tstamp_cc = (struct cyclecounter) {
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.read = sja1105_ptptsclk_read,
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.mask = CYCLECOUNTER_MASK(64),
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.shift = SJA1105_CC_SHIFT,
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.mult = SJA1105_CC_MULT,
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};
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ptp_data->caps = (struct ptp_clock_info) {
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.owner = THIS_MODULE,
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.name = "SJA1105 PHC",
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@ -578,8 +571,8 @@ int sja1105_ptp_clock_register(struct dsa_switch *ds)
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if (IS_ERR_OR_NULL(ptp_data->clock))
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return PTR_ERR(ptp_data->clock);
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INIT_DELAYED_WORK(&ptp_data->refresh_work, sja1105_ptp_overflow_check);
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schedule_delayed_work(&ptp_data->refresh_work, SJA1105_REFRESH_INTERVAL);
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ptp_data->cmd.corrclk4ts = true;
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ptp_data->cmd.ptpclkadd = PTP_SET_MODE;
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return sja1105_ptp_reset(ds);
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}
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@ -594,7 +587,6 @@ void sja1105_ptp_clock_unregister(struct dsa_switch *ds)
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cancel_work_sync(&priv->tagger_data.rxtstamp_work);
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skb_queue_purge(&priv->tagger_data.skb_rxtstamp_queue);
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cancel_delayed_work_sync(&ptp_data->refresh_work);
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ptp_clock_unregister(ptp_data->clock);
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ptp_data->clock = NULL;
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}
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@ -605,14 +597,19 @@ void sja1105_ptp_txtstamp_skb(struct dsa_switch *ds, int slot,
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struct sja1105_private *priv = ds->priv;
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struct sja1105_ptp_data *ptp_data = &priv->ptp_data;
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struct skb_shared_hwtstamps shwt = {0};
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u64 now, ts;
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u64 ticks, ts;
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int rc;
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skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
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mutex_lock(&ptp_data->lock);
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now = ptp_data->tstamp_cc.read(&ptp_data->tstamp_cc);
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rc = sja1105_ptpclkval_read(priv, &ticks);
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if (rc < 0) {
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dev_err(ds->dev, "Failed to read PTP clock: %d\n", rc);
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kfree_skb(skb);
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goto out;
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}
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rc = sja1105_ptpegr_ts_poll(ds, slot, &ts);
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if (rc < 0) {
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@ -621,10 +618,9 @@ void sja1105_ptp_txtstamp_skb(struct dsa_switch *ds, int slot,
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goto out;
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}
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ts = sja1105_tstamp_reconstruct(ds, now, ts);
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ts = timecounter_cyc2time(&ptp_data->tstamp_tc, ts);
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ts = sja1105_tstamp_reconstruct(ds, ticks, ts);
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shwt.hwtstamp = ns_to_ktime(ts);
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shwt.hwtstamp = ns_to_ktime(sja1105_ticks_to_ns(ts));
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skb_complete_tx_timestamp(skb, &shwt);
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out:
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@ -6,21 +6,32 @@
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#if IS_ENABLED(CONFIG_NET_DSA_SJA1105_PTP)
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/* Timestamps are in units of 8 ns clock ticks (equivalent to
|
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* a fixed 125 MHz clock).
|
||||
*/
|
||||
#define SJA1105_TICK_NS 8
|
||||
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||||
static inline s64 ns_to_sja1105_ticks(s64 ns)
|
||||
{
|
||||
return ns / SJA1105_TICK_NS;
|
||||
}
|
||||
|
||||
static inline s64 sja1105_ticks_to_ns(s64 ticks)
|
||||
{
|
||||
return ticks * SJA1105_TICK_NS;
|
||||
}
|
||||
|
||||
struct sja1105_ptp_cmd {
|
||||
u64 resptp; /* reset */
|
||||
u64 corrclk4ts; /* use the corrected clock for timestamps */
|
||||
u64 ptpclkadd; /* enum sja1105_ptp_clk_mode */
|
||||
};
|
||||
|
||||
struct sja1105_ptp_data {
|
||||
struct ptp_clock_info caps;
|
||||
struct ptp_clock *clock;
|
||||
struct sja1105_ptp_cmd cmd;
|
||||
/* The cycle counter translates the PTP timestamps (based on
|
||||
* a free-running counter) into a software time domain.
|
||||
*/
|
||||
struct cyclecounter tstamp_cc;
|
||||
struct timecounter tstamp_tc;
|
||||
struct delayed_work refresh_work;
|
||||
/* Serializes all operations on the cycle counter */
|
||||
/* Serializes all operations on the PTP hardware clock */
|
||||
struct mutex lock;
|
||||
};
|
||||
|
||||
|
|
|
|||
|
|
@ -516,9 +516,8 @@ static struct sja1105_regs sja1105et_regs = {
|
|||
.rmii_ext_tx_clk = {0x100018, 0x10001F, 0x100026, 0x10002D, 0x100034},
|
||||
.ptpegr_ts = {0xC0, 0xC2, 0xC4, 0xC6, 0xC8},
|
||||
.ptp_control = 0x17,
|
||||
.ptpclk = 0x18, /* Spans 0x18 to 0x19 */
|
||||
.ptpclkval = 0x18, /* Spans 0x18 to 0x19 */
|
||||
.ptpclkrate = 0x1A,
|
||||
.ptptsclk = 0x1B, /* Spans 0x1B to 0x1C */
|
||||
};
|
||||
|
||||
static struct sja1105_regs sja1105pqrs_regs = {
|
||||
|
|
@ -547,9 +546,8 @@ static struct sja1105_regs sja1105pqrs_regs = {
|
|||
.qlevel = {0x604, 0x614, 0x624, 0x634, 0x644},
|
||||
.ptpegr_ts = {0xC0, 0xC4, 0xC8, 0xCC, 0xD0},
|
||||
.ptp_control = 0x18,
|
||||
.ptpclk = 0x19,
|
||||
.ptpclkval = 0x19,
|
||||
.ptpclkrate = 0x1B,
|
||||
.ptptsclk = 0x1C,
|
||||
};
|
||||
|
||||
struct sja1105_info sja1105e_info = {
|
||||
|
|
|
|||
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