Second set of iwlwifi patches intended for v5.12
* Add some device IDs that got lost in a rebase; * A bunch of fixes in the PPAG code; * A few fixes in the debugging framework; * Fix a couple of potential crashes in error paths; * More HW IDs for new HW; * Add one more value to the device configuration code; * Support new scan config FW API; * Some more CSA fixes; * Support for RF interference mitigation (RFI); * Improvements in the NVM flows; * Bump the FW API support version; * Implement support for PNVM from BIOS; * Fix PM status when a FW crash happens; * Some other small fixes, clean-ups and improvements. -----BEGIN PGP SIGNATURE----- iQIzBAABCgAdFiEEF3LNfgb2BPWm68smoUecoho8xfoFAmAkdBoACgkQoUecoho8 xfqG0w//R+qj+ebaG6bBRgVOyY6DxwT1l722jC33DKROrH2PRZhPbYRBuCjt7Ve3 nySSFiq+o9wevmF31/TXO1y/7yf68Q/W69wQ6pSqK5dAX8bxUoNPL1g2JgLgudCM uVtzF2UfnToWWhDoYY/hgI53suiLixTYd6JFBSR8EClbszcxe7EYOYjD9iccWk6x WAZn0xJm+0q0O9WPZ+z1455PTwIU7X/OrX35PUXZNBEUV7shEYWBA/5i9ZEUP0Z6 L3kHXIQ4jQLBf1LwjfrlBqmKBnNB+rajaYsrTQ7VCsi4yEy9Ol9JHIBIt/VyRw8j 0gj/0JLFoO06eHArsPodC2fVN3A2VXyyRY/HAa+Fm2BdZrPDXpOd5tlP8vxUKW8d FriGB6aL8v50s/CDKTzs467vWYuWoMyXbG7KwHdPBuQTTu48M8Ku1ZtdLwlnElT0 fO+IBLeAwCsBVjqDQqq/dRJeBR2fhkIukJZzh8Y67xYcG++dKFcbEFEWpKOLU3l9 CgKtwPWbxp3+9R0Rs8mXX5DYkhAX/JhLYi0aO4LryqV0tbrHC27LsavPRZEPKWjF 558o4o3oN7AQeliLHjaFJ0mEsWWasQv7bb+3W8N4BvHUSOWzhuP9uC0/CrGscN+C z1GeZgvL8fXzNSFx4iJ1NHUyPPK4J5zFcM2Xa9umIHXpBGzlPJw= =l8+/ -----END PGP SIGNATURE----- Merge tag 'iwlwifi-next-for-kalle-2021-02-10' of git://git.kernel.org/pub/scm/linux/kernel/git/iwlwifi/iwlwifi-next Second set of iwlwifi patches intended for v5.12 * Add some device IDs that got lost in a rebase; * A bunch of fixes in the PPAG code; * A few fixes in the debugging framework; * Fix a couple of potential crashes in error paths; * More HW IDs for new HW; * Add one more value to the device configuration code; * Support new scan config FW API; * Some more CSA fixes; * Support for RF interference mitigation (RFI); * Improvements in the NVM flows; * Bump the FW API support version; * Implement support for PNVM from BIOS; * Fix PM status when a FW crash happens; * Some other small fixes, clean-ups and improvements. # gpg: Signature made Thu 11 Feb 2021 02:02:34 AM EET using RSA key ID 1A3CC5FA # gpg: Good signature from "Luciano Roth Coelho (Luca) <luca@coelho.fi>" # gpg: aka "Luciano Roth Coelho (Intel) <luciano.coelho@intel.com>"
This commit is contained in:
Коммит
30357f6a47
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@ -2,7 +2,7 @@
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/******************************************************************************
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*
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* Copyright(c) 2008 - 2014 Intel Corporation. All rights reserved.
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* Copyright(c) 2018 - 2019 Intel Corporation
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* Copyright(c) 2018 - 2020 Intel Corporation
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*
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* Contact Information:
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* Intel Linux Wireless <linuxwifi@intel.com>
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@ -76,8 +76,7 @@ static const struct iwl_eeprom_params iwl1000_eeprom_params = {
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.nvm_calib_ver = EEPROM_1000_TX_POWER_VERSION, \
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.trans.base_params = &iwl1000_base_params, \
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.eeprom_params = &iwl1000_eeprom_params, \
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.led_mode = IWL_LED_BLINK, \
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.max_ht_ampdu_exponent = IEEE80211_HT_MAX_AMPDU_64K
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.led_mode = IWL_LED_BLINK
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const struct iwl_cfg iwl1000_bgn_cfg = {
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.name = "Intel(R) Centrino(R) Wireless-N 1000 BGN",
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@ -102,8 +101,7 @@ const struct iwl_cfg iwl1000_bg_cfg = {
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.trans.base_params = &iwl1000_base_params, \
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.eeprom_params = &iwl1000_eeprom_params, \
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.led_mode = IWL_LED_RF_STATE, \
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.rx_with_siso_diversity = true, \
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.max_ht_ampdu_exponent = IEEE80211_HT_MAX_AMPDU_64K
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.rx_with_siso_diversity = true
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const struct iwl_cfg iwl100_bgn_cfg = {
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.name = "Intel(R) Centrino(R) Wireless-N 100 BGN",
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@ -2,7 +2,7 @@
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/******************************************************************************
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*
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* Copyright(c) 2008 - 2014 Intel Corporation. All rights reserved.
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* Copyright(c) 2018 - 2019 Intel Corporation
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* Copyright(c) 2018 - 2020 Intel Corporation
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*
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* Contact Information:
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* Intel Linux Wireless <linuxwifi@intel.com>
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@ -102,8 +102,7 @@ static const struct iwl_eeprom_params iwl20x0_eeprom_params = {
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.nvm_calib_ver = EEPROM_2000_TX_POWER_VERSION, \
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.trans.base_params = &iwl2000_base_params, \
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.eeprom_params = &iwl20x0_eeprom_params, \
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.led_mode = IWL_LED_RF_STATE, \
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.max_ht_ampdu_exponent = IEEE80211_HT_MAX_AMPDU_64K
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.led_mode = IWL_LED_RF_STATE
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const struct iwl_cfg iwl2000_2bgn_cfg = {
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@ -129,8 +128,7 @@ const struct iwl_cfg iwl2000_2bgn_d_cfg = {
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.nvm_calib_ver = EEPROM_2000_TX_POWER_VERSION, \
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.trans.base_params = &iwl2030_base_params, \
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.eeprom_params = &iwl20x0_eeprom_params, \
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.led_mode = IWL_LED_RF_STATE, \
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.max_ht_ampdu_exponent = IEEE80211_HT_MAX_AMPDU_64K
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.led_mode = IWL_LED_RF_STATE
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const struct iwl_cfg iwl2030_2bgn_cfg = {
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.name = "Intel(R) Centrino(R) Wireless-N 2230 BGN",
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@ -150,8 +148,7 @@ const struct iwl_cfg iwl2030_2bgn_cfg = {
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.trans.base_params = &iwl2000_base_params, \
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.eeprom_params = &iwl20x0_eeprom_params, \
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.led_mode = IWL_LED_RF_STATE, \
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.rx_with_siso_diversity = true, \
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.max_ht_ampdu_exponent = IEEE80211_HT_MAX_AMPDU_64K
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.rx_with_siso_diversity = true
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const struct iwl_cfg iwl105_bgn_cfg = {
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.name = "Intel(R) Centrino(R) Wireless-N 105 BGN",
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@ -177,8 +174,7 @@ const struct iwl_cfg iwl105_bgn_d_cfg = {
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.trans.base_params = &iwl2030_base_params, \
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.eeprom_params = &iwl20x0_eeprom_params, \
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.led_mode = IWL_LED_RF_STATE, \
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.rx_with_siso_diversity = true, \
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.max_ht_ampdu_exponent = IEEE80211_HT_MAX_AMPDU_64K
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.rx_with_siso_diversity = true
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const struct iwl_cfg iwl135_bgn_cfg = {
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.name = "Intel(R) Centrino(R) Wireless-N 135 BGN",
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@ -9,7 +9,7 @@
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#include "iwl-prph.h"
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/* Highest firmware API version supported */
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#define IWL_22000_UCODE_API_MAX 61
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#define IWL_22000_UCODE_API_MAX 62
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/* Lowest firmware API version supported */
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#define IWL_22000_UCODE_API_MIN 39
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@ -43,7 +43,9 @@
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#define IWL_SNJ_A_GF_A_FW_PRE "iwlwifi-SoSnj-a0-gf-a0-"
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#define IWL_SNJ_A_HR_B_FW_PRE "iwlwifi-SoSnj-a0-hr-b0-"
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#define IWL_SNJ_A_JF_B_FW_PRE "iwlwifi-SoSnj-a0-jf-b0-"
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#define IWL_MA_A_HR_B_FW_PRE "iwlwifi-ma-a0-hr-b0-"
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#define IWL_MA_A_GF_A_FW_PRE "iwlwifi-ma-a0-gf-a0-"
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#define IWL_MA_A_GF4_A_FW_PRE "iwlwifi-ma-a0-gf4-a0-"
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#define IWL_MA_A_MR_A_FW_PRE "iwlwifi-ma-a0-mr-a0-"
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#define IWL_SNJ_A_MR_A_FW_PRE "iwlwifi-SoSnj-a0-mr-a0-"
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@ -79,8 +81,12 @@
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IWL_SNJ_A_HR_B_FW_PRE __stringify(api) ".ucode"
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#define IWL_SNJ_A_JF_B_MODULE_FIRMWARE(api) \
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IWL_SNJ_A_JF_B_FW_PRE __stringify(api) ".ucode"
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#define IWL_MA_A_HR_B_FW_MODULE_FIRMWARE(api) \
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IWL_MA_A_HR_B_FW_PRE __stringify(api) ".ucode"
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#define IWL_MA_A_GF_A_FW_MODULE_FIRMWARE(api) \
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IWL_MA_A_GF_A_FW_PRE __stringify(api) ".ucode"
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#define IWL_MA_A_GF4_A_FW_MODULE_FIRMWARE(api) \
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IWL_MA_A_GF4_A_FW_PRE __stringify(api) ".ucode"
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#define IWL_MA_A_MR_A_FW_MODULE_FIRMWARE(api) \
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IWL_MA_A_MR_A_FW_PRE __stringify(api) ".ucode"
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#define IWL_SNJ_A_MR_A_MODULE_FIRMWARE(api) \
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@ -136,7 +142,6 @@ static const struct iwl_ht_params iwl_22000_ht_params = {
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.mac_addr_from_csr = true, \
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.ht_params = &iwl_22000_ht_params, \
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.nvm_ver = IWL_22000_NVM_VERSION, \
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.max_ht_ampdu_exponent = IEEE80211_HT_MAX_AMPDU_64K, \
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.trans.use_tfh = true, \
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.trans.rf_id = true, \
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.trans.gen2 = true, \
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@ -661,6 +666,13 @@ const struct iwl_cfg iwl_cfg_snj_a0_jf_b0 = {
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.num_rbds = IWL_NUM_RBDS_AX210_HE,
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};
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const struct iwl_cfg iwl_cfg_ma_a0_hr_b0 = {
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.fw_name_pre = IWL_MA_A_HR_B_FW_PRE,
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.uhb_supported = true,
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IWL_DEVICE_AX210,
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.num_rbds = IWL_NUM_RBDS_AX210_HE,
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};
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const struct iwl_cfg iwl_cfg_ma_a0_gf_a0 = {
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.fw_name_pre = IWL_MA_A_GF_A_FW_PRE,
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.uhb_supported = true,
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@ -668,6 +680,13 @@ const struct iwl_cfg iwl_cfg_ma_a0_gf_a0 = {
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.num_rbds = IWL_NUM_RBDS_AX210_HE,
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};
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const struct iwl_cfg iwl_cfg_ma_a0_gf4_a0 = {
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.fw_name_pre = IWL_MA_A_GF4_A_FW_PRE,
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.uhb_supported = true,
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IWL_DEVICE_AX210,
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.num_rbds = IWL_NUM_RBDS_AX210_HE,
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};
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const struct iwl_cfg iwl_cfg_ma_a0_mr_a0 = {
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.fw_name_pre = IWL_MA_A_MR_A_FW_PRE,
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.uhb_supported = true,
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@ -682,6 +701,24 @@ const struct iwl_cfg iwl_cfg_snj_a0_mr_a0 = {
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.num_rbds = IWL_NUM_RBDS_AX210_HE,
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};
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const struct iwl_cfg iwl_cfg_so_a0_hr_a0 = {
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.fw_name_pre = IWL_SO_A_HR_B_FW_PRE,
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IWL_DEVICE_AX210,
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.num_rbds = IWL_NUM_RBDS_AX210_HE,
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};
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const struct iwl_cfg iwl_cfg_quz_a0_hr_b0 = {
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.fw_name_pre = IWL_QUZ_A_HR_B_FW_PRE,
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IWL_DEVICE_22500,
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/*
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* This device doesn't support receiving BlockAck with a large bitmap
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* so we need to restrict the size of transmitted aggregation to the
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* HT size; mac80211 would otherwise pick the HE max (256) by default.
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*/
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.max_tx_agg_size = IEEE80211_MAX_AMPDU_BUF_HT,
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.num_rbds = IWL_NUM_RBDS_22000_HE,
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};
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MODULE_FIRMWARE(IWL_QU_B_HR_B_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX));
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MODULE_FIRMWARE(IWL_QNJ_B_HR_B_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX));
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MODULE_FIRMWARE(IWL_QU_C_HR_B_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX));
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@ -698,6 +735,8 @@ MODULE_FIRMWARE(IWL_SNJ_A_GF4_A_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX));
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MODULE_FIRMWARE(IWL_SNJ_A_GF_A_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX));
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MODULE_FIRMWARE(IWL_SNJ_A_HR_B_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX));
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MODULE_FIRMWARE(IWL_SNJ_A_JF_B_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX));
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MODULE_FIRMWARE(IWL_MA_A_HR_B_FW_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX));
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MODULE_FIRMWARE(IWL_MA_A_GF_A_FW_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX));
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MODULE_FIRMWARE(IWL_MA_A_GF4_A_FW_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX));
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MODULE_FIRMWARE(IWL_MA_A_MR_A_FW_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX));
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MODULE_FIRMWARE(IWL_SNJ_A_MR_A_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX));
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@ -2,7 +2,7 @@
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/******************************************************************************
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*
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* Copyright(c) 2007 - 2014 Intel Corporation. All rights reserved.
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* Copyright(c) 2018 - 2019 Intel Corporation
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* Copyright(c) 2018 - 2020 Intel Corporation
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*
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* Contact Information:
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* Intel Linux Wireless <linuxwifi@intel.com>
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@ -74,8 +74,7 @@ static const struct iwl_eeprom_params iwl5000_eeprom_params = {
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.nvm_calib_ver = EEPROM_5000_TX_POWER_VERSION, \
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.trans.base_params = &iwl5000_base_params, \
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.eeprom_params = &iwl5000_eeprom_params, \
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.led_mode = IWL_LED_BLINK, \
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.max_ht_ampdu_exponent = IEEE80211_HT_MAX_AMPDU_64K
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.led_mode = IWL_LED_BLINK
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const struct iwl_cfg iwl5300_agn_cfg = {
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.name = "Intel(R) Ultimate N WiFi Link 5300 AGN",
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@ -138,8 +137,7 @@ const struct iwl_cfg iwl5350_agn_cfg = {
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.trans.base_params = &iwl5000_base_params, \
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.eeprom_params = &iwl5000_eeprom_params, \
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.led_mode = IWL_LED_BLINK, \
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.internal_wimax_coex = true, \
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.max_ht_ampdu_exponent = IEEE80211_HT_MAX_AMPDU_64K
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.internal_wimax_coex = true
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const struct iwl_cfg iwl5150_agn_cfg = {
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.name = "Intel(R) WiMAX/WiFi Link 5150 AGN",
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|
|
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@ -2,7 +2,7 @@
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/******************************************************************************
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*
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* Copyright(c) 2008 - 2014 Intel Corporation. All rights reserved.
|
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* Copyright(c) 2018 - 2019 Intel Corporation
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* Copyright(c) 2018 - 2020 Intel Corporation
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*
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* Contact Information:
|
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* Intel Linux Wireless <linuxwifi@intel.com>
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@ -123,8 +123,7 @@ static const struct iwl_eeprom_params iwl6000_eeprom_params = {
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.nvm_calib_ver = EEPROM_6005_TX_POWER_VERSION, \
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.trans.base_params = &iwl6000_g2_base_params, \
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.eeprom_params = &iwl6000_eeprom_params, \
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.led_mode = IWL_LED_RF_STATE, \
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.max_ht_ampdu_exponent = IEEE80211_HT_MAX_AMPDU_64K
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.led_mode = IWL_LED_RF_STATE
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const struct iwl_cfg iwl6005_2agn_cfg = {
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.name = "Intel(R) Centrino(R) Advanced-N 6205 AGN",
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@ -177,8 +176,7 @@ const struct iwl_cfg iwl6005_2agn_mow2_cfg = {
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.nvm_calib_ver = EEPROM_6030_TX_POWER_VERSION, \
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.trans.base_params = &iwl6000_g2_base_params, \
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.eeprom_params = &iwl6000_eeprom_params, \
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.led_mode = IWL_LED_RF_STATE, \
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.max_ht_ampdu_exponent = IEEE80211_HT_MAX_AMPDU_64K
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.led_mode = IWL_LED_RF_STATE
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const struct iwl_cfg iwl6030_2agn_cfg = {
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.name = "Intel(R) Centrino(R) Advanced-N 6230 AGN",
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@ -213,8 +211,7 @@ const struct iwl_cfg iwl6030_2bg_cfg = {
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.nvm_calib_ver = EEPROM_6030_TX_POWER_VERSION, \
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.trans.base_params = &iwl6000_g2_base_params, \
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.eeprom_params = &iwl6000_eeprom_params, \
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.led_mode = IWL_LED_RF_STATE, \
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.max_ht_ampdu_exponent = IEEE80211_HT_MAX_AMPDU_64K
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.led_mode = IWL_LED_RF_STATE
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const struct iwl_cfg iwl6035_2agn_cfg = {
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.name = "Intel(R) Centrino(R) Advanced-N 6235 AGN",
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@ -268,8 +265,7 @@ const struct iwl_cfg iwl130_bg_cfg = {
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.nvm_calib_ver = EEPROM_6000_TX_POWER_VERSION, \
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.trans.base_params = &iwl6000_base_params, \
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.eeprom_params = &iwl6000_eeprom_params, \
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.led_mode = IWL_LED_BLINK, \
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.max_ht_ampdu_exponent = IEEE80211_HT_MAX_AMPDU_64K
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.led_mode = IWL_LED_BLINK
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const struct iwl_cfg iwl6000i_2agn_cfg = {
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.name = "Intel(R) Centrino(R) Advanced-N 6200 AGN",
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@ -301,8 +297,7 @@ const struct iwl_cfg iwl6000i_2bg_cfg = {
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.trans.base_params = &iwl6050_base_params, \
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.eeprom_params = &iwl6000_eeprom_params, \
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.led_mode = IWL_LED_BLINK, \
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.internal_wimax_coex = true, \
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.max_ht_ampdu_exponent = IEEE80211_HT_MAX_AMPDU_64K
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.internal_wimax_coex = true
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const struct iwl_cfg iwl6050_2agn_cfg = {
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.name = "Intel(R) Centrino(R) Advanced-N + WiMAX 6250 AGN",
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|
@ -327,8 +322,7 @@ const struct iwl_cfg iwl6050_2abg_cfg = {
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.trans.base_params = &iwl6050_base_params, \
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.eeprom_params = &iwl6000_eeprom_params, \
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.led_mode = IWL_LED_BLINK, \
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.internal_wimax_coex = true, \
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.max_ht_ampdu_exponent = IEEE80211_HT_MAX_AMPDU_64K
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.internal_wimax_coex = true
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const struct iwl_cfg iwl6150_bgn_cfg = {
|
||||
.name = "Intel(R) Centrino(R) Wireless-N + WiMAX 6150 BGN",
|
||||
|
|
|
@ -1,6 +1,6 @@
|
|||
// SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
|
||||
/*
|
||||
* Copyright (C) 2012-2014, 2018-2019 Intel Corporation
|
||||
* Copyright (C) 2012-2014, 2018-2020 Intel Corporation
|
||||
* Copyright (C) 2013-2014 Intel Mobile Communications GmbH
|
||||
* Copyright (C) 2015 Intel Deutschland GmbH
|
||||
*/
|
||||
|
@ -95,7 +95,6 @@ static const struct iwl_ht_params iwl7000_ht_params = {
|
|||
.led_mode = IWL_LED_RF_STATE, \
|
||||
.nvm_hw_section_num = 0, \
|
||||
.non_shared_ant = ANT_A, \
|
||||
.max_ht_ampdu_exponent = IEEE80211_HT_MAX_AMPDU_64K, \
|
||||
.dccm_offset = IWL7000_DCCM_OFFSET
|
||||
|
||||
#define IWL_DEVICE_7000 \
|
||||
|
|
|
@ -1,6 +1,6 @@
|
|||
// SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
|
||||
/*
|
||||
* Copyright (C) 2014, 2018-2019 Intel Corporation
|
||||
* Copyright (C) 2014, 2018-2020 Intel Corporation
|
||||
* Copyright (C) 2014-2015 Intel Mobile Communications GmbH
|
||||
* Copyright (C) 2016 Intel Deutschland GmbH
|
||||
*/
|
||||
|
@ -125,7 +125,6 @@ const struct iwl_cfg iwl8260_2ac_cfg = {
|
|||
IWL_DEVICE_8260,
|
||||
.ht_params = &iwl8000_ht_params,
|
||||
.nvm_ver = IWL8000_NVM_VERSION,
|
||||
.max_ht_ampdu_exponent = IEEE80211_HT_MAX_AMPDU_64K,
|
||||
};
|
||||
|
||||
const struct iwl_cfg iwl8265_2ac_cfg = {
|
||||
|
@ -134,7 +133,6 @@ const struct iwl_cfg iwl8265_2ac_cfg = {
|
|||
IWL_DEVICE_8265,
|
||||
.ht_params = &iwl8000_ht_params,
|
||||
.nvm_ver = IWL8000_NVM_VERSION,
|
||||
.max_ht_ampdu_exponent = IEEE80211_HT_MAX_AMPDU_64K,
|
||||
.vht_mu_mimo_supported = true,
|
||||
};
|
||||
|
||||
|
@ -144,7 +142,6 @@ const struct iwl_cfg iwl8275_2ac_cfg = {
|
|||
IWL_DEVICE_8265,
|
||||
.ht_params = &iwl8000_ht_params,
|
||||
.nvm_ver = IWL8000_NVM_VERSION,
|
||||
.max_ht_ampdu_exponent = IEEE80211_HT_MAX_AMPDU_64K,
|
||||
.vht_mu_mimo_supported = true,
|
||||
};
|
||||
|
||||
|
@ -154,7 +151,6 @@ const struct iwl_cfg iwl4165_2ac_cfg = {
|
|||
IWL_DEVICE_8000,
|
||||
.ht_params = &iwl8000_ht_params,
|
||||
.nvm_ver = IWL8000_NVM_VERSION,
|
||||
.max_ht_ampdu_exponent = IEEE80211_HT_MAX_AMPDU_64K,
|
||||
};
|
||||
|
||||
MODULE_FIRMWARE(IWL8000_MODULE_FIRMWARE(IWL8000_UCODE_API_MAX));
|
||||
|
|
|
@ -97,7 +97,6 @@ static const struct iwl_tt_params iwl9000_tt_params = {
|
|||
.d3_debug_data_length = 92 * 1024, \
|
||||
.ht_params = &iwl9000_ht_params, \
|
||||
.nvm_ver = IWL9000_NVM_VERSION, \
|
||||
.max_ht_ampdu_exponent = IEEE80211_HT_MAX_AMPDU_64K, \
|
||||
.mon_smem_regs = { \
|
||||
.write_ptr = { \
|
||||
.addr = LDBG_M2S_BUF_WPTR, \
|
||||
|
|
|
@ -406,7 +406,6 @@ static void iwl_print_cont_event_trace(struct iwl_priv *priv, u32 base,
|
|||
u32 i;
|
||||
u32 ptr; /* SRAM byte address of log data */
|
||||
u32 ev, time, data; /* event log data */
|
||||
unsigned long reg_flags;
|
||||
|
||||
if (mode == 0)
|
||||
ptr = base + (4 * sizeof(u32)) + (start_idx * 2 * sizeof(u32));
|
||||
|
@ -414,7 +413,7 @@ static void iwl_print_cont_event_trace(struct iwl_priv *priv, u32 base,
|
|||
ptr = base + (4 * sizeof(u32)) + (start_idx * 3 * sizeof(u32));
|
||||
|
||||
/* Make sure device is powered up for SRAM reads */
|
||||
if (!iwl_trans_grab_nic_access(priv->trans, ®_flags))
|
||||
if (!iwl_trans_grab_nic_access(priv->trans))
|
||||
return;
|
||||
|
||||
/* Set starting address; reads will auto-increment */
|
||||
|
@ -446,7 +445,7 @@ static void iwl_print_cont_event_trace(struct iwl_priv *priv, u32 base,
|
|||
}
|
||||
}
|
||||
/* Allow device to power down */
|
||||
iwl_trans_release_nic_access(priv->trans, ®_flags);
|
||||
iwl_trans_release_nic_access(priv->trans);
|
||||
}
|
||||
|
||||
static void iwl_continuous_event_trace(struct iwl_priv *priv)
|
||||
|
@ -1694,7 +1693,6 @@ static int iwl_print_event_log(struct iwl_priv *priv, u32 start_idx,
|
|||
u32 event_size; /* 2 u32s, or 3 u32s if timestamp recorded */
|
||||
u32 ptr; /* SRAM byte address of log data */
|
||||
u32 ev, time, data; /* event log data */
|
||||
unsigned long reg_flags;
|
||||
|
||||
struct iwl_trans *trans = priv->trans;
|
||||
|
||||
|
@ -1718,7 +1716,7 @@ static int iwl_print_event_log(struct iwl_priv *priv, u32 start_idx,
|
|||
ptr = base + EVENT_START_OFFSET + (start_idx * event_size);
|
||||
|
||||
/* Make sure device is powered up for SRAM reads */
|
||||
if (!iwl_trans_grab_nic_access(trans, ®_flags))
|
||||
if (!iwl_trans_grab_nic_access(trans))
|
||||
return pos;
|
||||
|
||||
/* Set starting address; reads will auto-increment */
|
||||
|
@ -1757,7 +1755,7 @@ static int iwl_print_event_log(struct iwl_priv *priv, u32 start_idx,
|
|||
}
|
||||
|
||||
/* Allow device to power down */
|
||||
iwl_trans_release_nic_access(trans, ®_flags);
|
||||
iwl_trans_release_nic_access(trans);
|
||||
return pos;
|
||||
}
|
||||
|
||||
|
|
|
@ -2,7 +2,7 @@
|
|||
/******************************************************************************
|
||||
*
|
||||
* Copyright(c) 2007 - 2014 Intel Corporation. All rights reserved.
|
||||
* Copyright (C) 2018 Intel Corporation
|
||||
* Copyright (C) 2018, 2020 Intel Corporation
|
||||
*
|
||||
* Portions of this file are derived from the ipw3945 project, as well
|
||||
* as portions of the ieee80211 subsystem header files.
|
||||
|
@ -155,7 +155,6 @@ static void iwl_tt_check_exit_ct_kill(struct timer_list *t)
|
|||
struct iwl_priv *priv = from_timer(priv, t,
|
||||
thermal_throttle.ct_kill_exit_tm);
|
||||
struct iwl_tt_mgmt *tt = &priv->thermal_throttle;
|
||||
unsigned long flags;
|
||||
|
||||
if (test_bit(STATUS_EXIT_PENDING, &priv->status))
|
||||
return;
|
||||
|
@ -171,8 +170,8 @@ static void iwl_tt_check_exit_ct_kill(struct timer_list *t)
|
|||
priv->thermal_throttle.ct_kill_toggle = true;
|
||||
}
|
||||
iwl_read32(priv->trans, CSR_UCODE_DRV_GP1);
|
||||
if (iwl_trans_grab_nic_access(priv->trans, &flags))
|
||||
iwl_trans_release_nic_access(priv->trans, &flags);
|
||||
if (iwl_trans_grab_nic_access(priv->trans))
|
||||
iwl_trans_release_nic_access(priv->trans);
|
||||
|
||||
/* Reschedule the ct_kill timer to occur in
|
||||
* CT_KILL_EXIT_DURATION seconds to ensure we get a
|
||||
|
|
|
@ -9,9 +9,15 @@
|
|||
#include "acpi.h"
|
||||
#include "fw/runtime.h"
|
||||
|
||||
static const guid_t intel_wifi_guid = GUID_INIT(0xF21202BF, 0x8F78, 0x4DC6,
|
||||
0xA5, 0xB3, 0x1F, 0x73,
|
||||
0x8E, 0x28, 0x5A, 0xDE);
|
||||
const guid_t iwl_guid = GUID_INIT(0xF21202BF, 0x8F78, 0x4DC6,
|
||||
0xA5, 0xB3, 0x1F, 0x73,
|
||||
0x8E, 0x28, 0x5A, 0xDE);
|
||||
IWL_EXPORT_SYMBOL(iwl_guid);
|
||||
|
||||
const guid_t iwl_rfi_guid = GUID_INIT(0x7266172C, 0x220B, 0x4B29,
|
||||
0x81, 0x4F, 0x75, 0xE4,
|
||||
0xDD, 0x26, 0xB5, 0xFD);
|
||||
IWL_EXPORT_SYMBOL(iwl_rfi_guid);
|
||||
|
||||
static int iwl_acpi_get_handle(struct device *dev, acpi_string method,
|
||||
acpi_handle *ret_handle)
|
||||
|
@ -64,11 +70,12 @@ IWL_EXPORT_SYMBOL(iwl_acpi_get_object);
|
|||
* function.
|
||||
*/
|
||||
static void *iwl_acpi_get_dsm_object(struct device *dev, int rev, int func,
|
||||
union acpi_object *args)
|
||||
union acpi_object *args,
|
||||
const guid_t *guid)
|
||||
{
|
||||
union acpi_object *obj;
|
||||
|
||||
obj = acpi_evaluate_dsm(ACPI_HANDLE(dev), &intel_wifi_guid, rev, func,
|
||||
obj = acpi_evaluate_dsm(ACPI_HANDLE(dev), guid, rev, func,
|
||||
args);
|
||||
if (!obj) {
|
||||
IWL_DEBUG_DEV_RADIO(dev,
|
||||
|
@ -87,12 +94,13 @@ static void *iwl_acpi_get_dsm_object(struct device *dev, int rev, int func,
|
|||
* return 0 in success and the appropriate errno otherwise.
|
||||
*/
|
||||
static int iwl_acpi_get_dsm_integer(struct device *dev, int rev, int func,
|
||||
u64 *value, size_t expected_size)
|
||||
const guid_t *guid, u64 *value,
|
||||
size_t expected_size)
|
||||
{
|
||||
union acpi_object *obj;
|
||||
int ret = 0;
|
||||
|
||||
obj = iwl_acpi_get_dsm_object(dev, rev, func, NULL);
|
||||
obj = iwl_acpi_get_dsm_object(dev, rev, func, NULL, guid);
|
||||
if (IS_ERR(obj)) {
|
||||
IWL_DEBUG_DEV_RADIO(dev,
|
||||
"Failed to get DSM object. func= %d\n",
|
||||
|
@ -137,12 +145,14 @@ out:
|
|||
/*
|
||||
* Evaluate a DSM with no arguments and a u8 return value,
|
||||
*/
|
||||
int iwl_acpi_get_dsm_u8(struct device *dev, int rev, int func, u8 *value)
|
||||
int iwl_acpi_get_dsm_u8(struct device *dev, int rev, int func,
|
||||
const guid_t *guid, u8 *value)
|
||||
{
|
||||
int ret;
|
||||
u64 val;
|
||||
|
||||
ret = iwl_acpi_get_dsm_integer(dev, rev, func, &val, sizeof(u8));
|
||||
ret = iwl_acpi_get_dsm_integer(dev, rev, func,
|
||||
guid, &val, sizeof(u8));
|
||||
|
||||
if (ret < 0)
|
||||
return ret;
|
||||
|
@ -478,11 +488,16 @@ int iwl_sar_get_wrds_table(struct iwl_fw_runtime *fwrt)
|
|||
|
||||
wifi_pkg = iwl_acpi_get_wifi_pkg(fwrt->dev, data,
|
||||
ACPI_WRDS_WIFI_DATA_SIZE, &tbl_rev);
|
||||
if (IS_ERR(wifi_pkg) || tbl_rev != 0) {
|
||||
if (IS_ERR(wifi_pkg)) {
|
||||
ret = PTR_ERR(wifi_pkg);
|
||||
goto out_free;
|
||||
}
|
||||
|
||||
if (tbl_rev != 0) {
|
||||
ret = -EINVAL;
|
||||
goto out_free;
|
||||
}
|
||||
|
||||
if (wifi_pkg->package.elements[1].type != ACPI_TYPE_INTEGER) {
|
||||
ret = -EINVAL;
|
||||
goto out_free;
|
||||
|
@ -516,11 +531,16 @@ int iwl_sar_get_ewrd_table(struct iwl_fw_runtime *fwrt)
|
|||
|
||||
wifi_pkg = iwl_acpi_get_wifi_pkg(fwrt->dev, data,
|
||||
ACPI_EWRD_WIFI_DATA_SIZE, &tbl_rev);
|
||||
if (IS_ERR(wifi_pkg) || tbl_rev != 0) {
|
||||
if (IS_ERR(wifi_pkg)) {
|
||||
ret = PTR_ERR(wifi_pkg);
|
||||
goto out_free;
|
||||
}
|
||||
|
||||
if (tbl_rev != 0) {
|
||||
ret = -EINVAL;
|
||||
goto out_free;
|
||||
}
|
||||
|
||||
if (wifi_pkg->package.elements[1].type != ACPI_TYPE_INTEGER ||
|
||||
wifi_pkg->package.elements[2].type != ACPI_TYPE_INTEGER) {
|
||||
ret = -EINVAL;
|
||||
|
@ -576,11 +596,17 @@ int iwl_sar_get_wgds_table(struct iwl_fw_runtime *fwrt)
|
|||
|
||||
wifi_pkg = iwl_acpi_get_wifi_pkg(fwrt->dev, data,
|
||||
ACPI_WGDS_WIFI_DATA_SIZE, &tbl_rev);
|
||||
if (IS_ERR(wifi_pkg) || tbl_rev > 1) {
|
||||
|
||||
if (IS_ERR(wifi_pkg)) {
|
||||
ret = PTR_ERR(wifi_pkg);
|
||||
goto out_free;
|
||||
}
|
||||
|
||||
if (tbl_rev > 1) {
|
||||
ret = -EINVAL;
|
||||
goto out_free;
|
||||
}
|
||||
|
||||
fwrt->geo_rev = tbl_rev;
|
||||
for (i = 0; i < ACPI_NUM_GEO_PROFILES; i++) {
|
||||
for (j = 0; j < ACPI_GEO_TABLE_SIZE; j++) {
|
||||
|
|
|
@ -54,9 +54,9 @@
|
|||
#define ACPI_WGDS_TABLE_SIZE 3
|
||||
|
||||
#define ACPI_PPAG_WIFI_DATA_SIZE ((IWL_NUM_CHAIN_LIMITS * \
|
||||
IWL_NUM_SUB_BANDS) + 3)
|
||||
IWL_NUM_SUB_BANDS) + 2)
|
||||
#define ACPI_PPAG_WIFI_DATA_SIZE_V2 ((IWL_NUM_CHAIN_LIMITS * \
|
||||
IWL_NUM_SUB_BANDS_V2) + 3)
|
||||
IWL_NUM_SUB_BANDS_V2) + 2)
|
||||
|
||||
/* PPAG gain value bounds in 1/8 dBm */
|
||||
#define ACPI_PPAG_MIN_LB -16
|
||||
|
@ -93,13 +93,27 @@ enum iwl_dsm_values_indonesia {
|
|||
DSM_VALUE_INDONESIA_MAX
|
||||
};
|
||||
|
||||
/* DSM RFI uses a different GUID, so need separate definitions */
|
||||
|
||||
#define DSM_RFI_FUNC_ENABLE 3
|
||||
|
||||
enum iwl_dsm_values_rfi {
|
||||
DSM_VALUE_RFI_ENABLE,
|
||||
DSM_VALUE_RFI_DISABLE,
|
||||
DSM_VALUE_RFI_MAX
|
||||
};
|
||||
|
||||
#ifdef CONFIG_ACPI
|
||||
|
||||
struct iwl_fw_runtime;
|
||||
|
||||
extern const guid_t iwl_guid;
|
||||
extern const guid_t iwl_rfi_guid;
|
||||
|
||||
void *iwl_acpi_get_object(struct device *dev, acpi_string method);
|
||||
|
||||
int iwl_acpi_get_dsm_u8(struct device *dev, int rev, int func, u8 *value);
|
||||
int iwl_acpi_get_dsm_u8(struct device *dev, int rev, int func,
|
||||
const guid_t *guid, u8 *value);
|
||||
|
||||
union acpi_object *iwl_acpi_get_wifi_pkg(struct device *dev,
|
||||
union acpi_object *data,
|
||||
|
@ -159,8 +173,8 @@ static inline void *iwl_acpi_get_dsm_object(struct device *dev, int rev,
|
|||
return ERR_PTR(-ENOENT);
|
||||
}
|
||||
|
||||
static inline
|
||||
int iwl_acpi_get_dsm_u8(struct device *dev, int rev, int func, u8 *value)
|
||||
static inline int iwl_acpi_get_dsm_u8(struct device *dev, int rev, int func,
|
||||
const guid_t *guid, u8 *value)
|
||||
{
|
||||
return -ENOENT;
|
||||
}
|
||||
|
|
|
@ -284,7 +284,7 @@ enum iwl_legacy_cmds {
|
|||
|
||||
/* Phy */
|
||||
/**
|
||||
* @PHY_CONFIGURATION_CMD: &struct iwl_phy_cfg_cmd
|
||||
* @PHY_CONFIGURATION_CMD: &struct iwl_phy_cfg_cmd_v1 or &struct iwl_phy_cfg_cmd_v3
|
||||
*/
|
||||
PHY_CONFIGURATION_CMD = 0x6a,
|
||||
|
||||
|
@ -606,6 +606,16 @@ enum iwl_system_subcmd_ids {
|
|||
* @FW_ERROR_RECOVERY_CMD: &struct iwl_fw_error_recovery_cmd
|
||||
*/
|
||||
FW_ERROR_RECOVERY_CMD = 0x7,
|
||||
|
||||
/**
|
||||
* @RFI_CONFIG_CMD: &struct iwl_rfi_config_cmd
|
||||
*/
|
||||
RFI_CONFIG_CMD = 0xb,
|
||||
|
||||
/**
|
||||
* @RFI_GET_FREQ_TABLE_CMD: &struct iwl_rfi_config_cmd
|
||||
*/
|
||||
RFI_GET_FREQ_TABLE_CMD = 0xc,
|
||||
};
|
||||
|
||||
#endif /* __iwl_fw_api_commands_h__ */
|
||||
|
|
|
@ -12,7 +12,12 @@
|
|||
enum iwl_location_subcmd_ids {
|
||||
/**
|
||||
* @TOF_RANGE_REQ_CMD: TOF ranging request,
|
||||
* uses &struct iwl_tof_range_req_cmd
|
||||
* uses one of &struct iwl_tof_range_req_cmd_v5,
|
||||
* &struct iwl_tof_range_req_cmd_v7,
|
||||
* &struct iwl_tof_range_req_cmd_v8,
|
||||
* &struct iwl_tof_range_req_cmd_v9,
|
||||
* &struct iwl_tof_range_req_cmd_v11,
|
||||
* &struct iwl_tof_range_req_cmd_v7
|
||||
*/
|
||||
TOF_RANGE_REQ_CMD = 0x0,
|
||||
/**
|
||||
|
|
|
@ -452,6 +452,10 @@ struct iwl_he_pkt_ext {
|
|||
* enabled AGG, i.e. both BACK and non-BACK frames in a single AGG
|
||||
* @STA_CTXT_HE_MU_EDCA_CW: indicates that there is an element of MU EDCA
|
||||
* parameter set, i.e. the backoff counters for trig-based ACs
|
||||
* @STA_CTXT_HE_NIC_NOT_ACK_ENABLED: mark that the NIC doesn't support receiving
|
||||
* ACK-enabled AGG, (i.e. both BACK and non-BACK frames in single AGG).
|
||||
* If the NIC is not ACK_ENABLED it may use the EOF-bit in first non-0
|
||||
* len delim to determine if AGG or single.
|
||||
* @STA_CTXT_HE_RU_2MHZ_BLOCK: indicates that 26-tone RU OFDMA transmission are
|
||||
* not allowed (as there are OBSS that might classify such transmissions as
|
||||
* radar pulses).
|
||||
|
@ -466,6 +470,7 @@ enum iwl_he_sta_ctxt_flags {
|
|||
STA_CTXT_HE_CONST_TRIG_RND_ALLOC = BIT(10),
|
||||
STA_CTXT_HE_ACK_ENABLED = BIT(11),
|
||||
STA_CTXT_HE_MU_EDCA_CW = BIT(12),
|
||||
STA_CTXT_HE_NIC_NOT_ACK_ENABLED = BIT(13),
|
||||
STA_CTXT_HE_RU_2MHZ_BLOCK = BIT(14),
|
||||
};
|
||||
|
||||
|
|
|
@ -415,14 +415,25 @@ enum iwl_lari_config_masks {
|
|||
};
|
||||
|
||||
/**
|
||||
* struct iwl_lari_config_change_cmd - change LARI configuration
|
||||
* struct iwl_lari_config_change_cmd_v1 - change LARI configuration
|
||||
* @config_bitmap: bit map of the config commands. each bit will trigger a
|
||||
* different predefined FW config operation
|
||||
*/
|
||||
struct iwl_lari_config_change_cmd {
|
||||
struct iwl_lari_config_change_cmd_v1 {
|
||||
__le32 config_bitmap;
|
||||
} __packed; /* LARI_CHANGE_CONF_CMD_S_VER_1 */
|
||||
|
||||
/**
|
||||
* struct iwl_lari_config_change_cmd_v2 - change LARI configuration
|
||||
* @config_bitmap: bit map of the config commands. each bit will trigger a
|
||||
* different predefined FW config operation
|
||||
* @oem_uhb_allow_bitmap: bitmap of UHB enabled MCC sets
|
||||
*/
|
||||
struct iwl_lari_config_change_cmd_v2 {
|
||||
__le32 config_bitmap;
|
||||
__le32 oem_uhb_allow_bitmap;
|
||||
} __packed; /* LARI_CHANGE_CONF_CMD_S_VER_2 */
|
||||
|
||||
/**
|
||||
* struct iwl_pnvm_init_complete_ntfy - PNVM initialization complete
|
||||
* @status: PNVM image loading status
|
||||
|
|
|
@ -0,0 +1,60 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */
|
||||
/*
|
||||
* Copyright (C) 2020 Intel Corporation
|
||||
*/
|
||||
#ifndef __iwl_fw_api_rfi_h__
|
||||
#define __iwl_fw_api_rfi_h__
|
||||
|
||||
#define IWL_RFI_LUT_ENTRY_CHANNELS_NUM 15
|
||||
#define IWL_RFI_LUT_SIZE 24
|
||||
#define IWL_RFI_LUT_INSTALLED_SIZE 4
|
||||
|
||||
/**
|
||||
* struct iwl_rfi_lut_entry - an entry in the RFI frequency LUT.
|
||||
*
|
||||
* @freq: frequency
|
||||
* @channels: channels that can be interfered at frequency freq (at most 15)
|
||||
* @bands: the corresponding bands
|
||||
*/
|
||||
struct iwl_rfi_lut_entry {
|
||||
__le16 freq;
|
||||
u8 channels[IWL_RFI_LUT_ENTRY_CHANNELS_NUM];
|
||||
u8 bands[IWL_RFI_LUT_ENTRY_CHANNELS_NUM];
|
||||
} __packed;
|
||||
|
||||
/**
|
||||
* struct iwl_rfi_config_cmd - RFI configuration table
|
||||
*
|
||||
* @entry: a table can have 24 frequency/channel mappings
|
||||
* @oem: specifies if this is the default table or set by OEM
|
||||
*/
|
||||
struct iwl_rfi_config_cmd {
|
||||
struct iwl_rfi_lut_entry table[IWL_RFI_LUT_SIZE];
|
||||
u8 oem;
|
||||
u8 reserved[3];
|
||||
} __packed; /* RFI_CONFIG_CMD_API_S_VER_1 */
|
||||
|
||||
/**
|
||||
* iwl_rfi_freq_table_status - status of the frequency table query
|
||||
* @RFI_FREQ_TABLE_OK: can be used
|
||||
* @RFI_FREQ_TABLE_DVFS_NOT_READY: DVFS is not ready yet, should try later
|
||||
* @RFI_FREQ_TABLE_DISABLED: the feature is disabled in FW
|
||||
*/
|
||||
enum iwl_rfi_freq_table_status {
|
||||
RFI_FREQ_TABLE_OK,
|
||||
RFI_FREQ_TABLE_DVFS_NOT_READY,
|
||||
RFI_FREQ_TABLE_DISABLED,
|
||||
};
|
||||
|
||||
/**
|
||||
* struct iwl_rfi_freq_table_resp_cmd - get the rfi freq table used by FW
|
||||
*
|
||||
* @table: table used by FW
|
||||
* @status: see &iwl_rfi_freq_table_status
|
||||
*/
|
||||
struct iwl_rfi_freq_table_resp_cmd {
|
||||
struct iwl_rfi_lut_entry table[IWL_RFI_LUT_INSTALLED_SIZE];
|
||||
__le32 status;
|
||||
} __packed; /* RFI_CONFIG_CMD_API_S_VER_1 */
|
||||
|
||||
#endif /* __iwl_fw_api_rfi_h__ */
|
|
@ -542,7 +542,8 @@ struct iwl_scan_config_v2 {
|
|||
* struct iwl_scan_config
|
||||
* @enable_cam_mode: whether to enable CAM mode.
|
||||
* @enable_promiscouos_mode: whether to enable promiscouos mode
|
||||
* @bcast_sta_id: the index of the station in the fw
|
||||
* @bcast_sta_id: the index of the station in the fw. Deprecated starting with
|
||||
* API version 5.
|
||||
* @reserved: reserved
|
||||
* @tx_chains: valid_tx antenna - ANT_* definitions
|
||||
* @rx_chains: valid_rx antenna - ANT_* definitions
|
||||
|
@ -554,7 +555,7 @@ struct iwl_scan_config {
|
|||
u8 reserved;
|
||||
__le32 tx_chains;
|
||||
__le32 rx_chains;
|
||||
} __packed; /* SCAN_CONFIG_DB_CMD_API_S_3 */
|
||||
} __packed; /* SCAN_CONFIG_DB_CMD_API_S_5 */
|
||||
|
||||
/**
|
||||
* enum iwl_umac_scan_flags - UMAC scan flags
|
||||
|
|
|
@ -20,6 +20,7 @@
|
|||
* @TX_CMD_FLG_VHT_NDPA: mark frame is NDPA for VHT beamformer sequence
|
||||
* @TX_CMD_FLG_HT_NDPA: mark frame is NDPA for HT beamformer sequence
|
||||
* @TX_CMD_FLG_CSI_FDBK2HOST: mark to send feedback to host (only if good CRC)
|
||||
* @TX_CMD_FLG_BT_PRIO_MASK: BT priority value
|
||||
* @TX_CMD_FLG_BT_PRIO_POS: the position of the BT priority (bit 11 is ignored
|
||||
* on old firmwares).
|
||||
* @TX_CMD_FLG_BT_DIS: disable BT priority for this frame
|
||||
|
@ -51,6 +52,7 @@ enum iwl_tx_flags {
|
|||
TX_CMD_FLG_HT_NDPA = BIT(9),
|
||||
TX_CMD_FLG_CSI_FDBK2HOST = BIT(10),
|
||||
TX_CMD_FLG_BT_PRIO_POS = 11,
|
||||
TX_CMD_FLG_BT_PRIO_MASK = BIT(11) | BIT(12),
|
||||
TX_CMD_FLG_BT_DIS = BIT(12),
|
||||
TX_CMD_FLG_SEQ_CTL = BIT(13),
|
||||
TX_CMD_FLG_MORE_FRAG = BIT(14),
|
||||
|
@ -177,7 +179,7 @@ enum iwl_tx_offload_assist_flags_pos {
|
|||
* ( TX_CMD = 0x1c )
|
||||
* @len: in bytes of the payload, see below for details
|
||||
* @offload_assist: TX offload configuration
|
||||
* @tx_flags: combination of TX_CMD_FLG_*
|
||||
* @tx_flags: combination of TX_CMD_FLG_*, see &enum iwl_tx_flags
|
||||
* @scratch: scratch buffer used by the device
|
||||
* @rate_n_flags: rate for *all* Tx attempts, if TX_CMD_FLG_STA_RATE_MSK is
|
||||
* cleared. Combination of RATE_MCS_*
|
||||
|
|
|
@ -33,12 +33,11 @@ static void iwl_read_radio_regs(struct iwl_fw_runtime *fwrt,
|
|||
struct iwl_fw_error_dump_data **dump_data)
|
||||
{
|
||||
u8 *pos = (void *)(*dump_data)->data;
|
||||
unsigned long flags;
|
||||
int i;
|
||||
|
||||
IWL_DEBUG_INFO(fwrt, "WRT radio registers dump\n");
|
||||
|
||||
if (!iwl_trans_grab_nic_access(fwrt->trans, &flags))
|
||||
if (!iwl_trans_grab_nic_access(fwrt->trans))
|
||||
return;
|
||||
|
||||
(*dump_data)->type = cpu_to_le32(IWL_FW_ERROR_DUMP_RADIO_REG);
|
||||
|
@ -56,7 +55,7 @@ static void iwl_read_radio_regs(struct iwl_fw_runtime *fwrt,
|
|||
|
||||
*dump_data = iwl_fw_error_next_data(*dump_data);
|
||||
|
||||
iwl_trans_release_nic_access(fwrt->trans, &flags);
|
||||
iwl_trans_release_nic_access(fwrt->trans);
|
||||
}
|
||||
|
||||
static void iwl_fwrt_dump_rxf(struct iwl_fw_runtime *fwrt,
|
||||
|
@ -172,11 +171,10 @@ static void iwl_fw_dump_rxf(struct iwl_fw_runtime *fwrt,
|
|||
struct iwl_fw_error_dump_data **dump_data)
|
||||
{
|
||||
struct iwl_fwrt_shared_mem_cfg *cfg = &fwrt->smem_cfg;
|
||||
unsigned long flags;
|
||||
|
||||
IWL_DEBUG_INFO(fwrt, "WRT RX FIFO dump\n");
|
||||
|
||||
if (!iwl_trans_grab_nic_access(fwrt->trans, &flags))
|
||||
if (!iwl_trans_grab_nic_access(fwrt->trans))
|
||||
return;
|
||||
|
||||
if (iwl_fw_dbg_type_on(fwrt, IWL_FW_ERROR_DUMP_RXF)) {
|
||||
|
@ -194,7 +192,7 @@ static void iwl_fw_dump_rxf(struct iwl_fw_runtime *fwrt,
|
|||
LMAC2_PRPH_OFFSET, 2);
|
||||
}
|
||||
|
||||
iwl_trans_release_nic_access(fwrt->trans, &flags);
|
||||
iwl_trans_release_nic_access(fwrt->trans);
|
||||
}
|
||||
|
||||
static void iwl_fw_dump_txf(struct iwl_fw_runtime *fwrt,
|
||||
|
@ -204,12 +202,11 @@ static void iwl_fw_dump_txf(struct iwl_fw_runtime *fwrt,
|
|||
struct iwl_fwrt_shared_mem_cfg *cfg = &fwrt->smem_cfg;
|
||||
u32 *fifo_data;
|
||||
u32 fifo_len;
|
||||
unsigned long flags;
|
||||
int i, j;
|
||||
|
||||
IWL_DEBUG_INFO(fwrt, "WRT TX FIFO dump\n");
|
||||
|
||||
if (!iwl_trans_grab_nic_access(fwrt->trans, &flags))
|
||||
if (!iwl_trans_grab_nic_access(fwrt->trans))
|
||||
return;
|
||||
|
||||
if (iwl_fw_dbg_type_on(fwrt, IWL_FW_ERROR_DUMP_TXF)) {
|
||||
|
@ -299,7 +296,7 @@ static void iwl_fw_dump_txf(struct iwl_fw_runtime *fwrt,
|
|||
}
|
||||
}
|
||||
|
||||
iwl_trans_release_nic_access(fwrt->trans, &flags);
|
||||
iwl_trans_release_nic_access(fwrt->trans);
|
||||
}
|
||||
|
||||
#define IWL8260_ICCM_OFFSET 0x44000 /* Only for B-step */
|
||||
|
@ -527,7 +524,6 @@ static void iwl_dump_prph(struct iwl_fw_runtime *fwrt,
|
|||
struct iwl_trans *trans = fwrt->trans;
|
||||
struct iwl_fw_error_dump_data **data =
|
||||
(struct iwl_fw_error_dump_data **)ptr;
|
||||
unsigned long flags;
|
||||
u32 i;
|
||||
|
||||
if (!data)
|
||||
|
@ -535,7 +531,7 @@ static void iwl_dump_prph(struct iwl_fw_runtime *fwrt,
|
|||
|
||||
IWL_DEBUG_INFO(trans, "WRT PRPH dump\n");
|
||||
|
||||
if (!iwl_trans_grab_nic_access(trans, &flags))
|
||||
if (!iwl_trans_grab_nic_access(trans))
|
||||
return;
|
||||
|
||||
for (i = 0; i < range_len; i++) {
|
||||
|
@ -558,7 +554,7 @@ static void iwl_dump_prph(struct iwl_fw_runtime *fwrt,
|
|||
*data = iwl_fw_error_next_data(*data);
|
||||
}
|
||||
|
||||
iwl_trans_release_nic_access(trans, &flags);
|
||||
iwl_trans_release_nic_access(trans);
|
||||
}
|
||||
|
||||
/*
|
||||
|
@ -1048,7 +1044,6 @@ iwl_dump_ini_prph_phy_iter(struct iwl_fw_runtime *fwrt,
|
|||
u32 addr = le32_to_cpu(reg->addrs[idx]);
|
||||
u32 dphy_state;
|
||||
u32 dphy_addr;
|
||||
unsigned long flags;
|
||||
int i;
|
||||
|
||||
range->internal_base_addr = cpu_to_le32(addr);
|
||||
|
@ -1060,7 +1055,7 @@ iwl_dump_ini_prph_phy_iter(struct iwl_fw_runtime *fwrt,
|
|||
indirect_wr_addr += le32_to_cpu(reg->dev_addr.offset);
|
||||
indirect_rd_addr += le32_to_cpu(reg->dev_addr.offset);
|
||||
|
||||
if (!iwl_trans_grab_nic_access(fwrt->trans, &flags))
|
||||
if (!iwl_trans_grab_nic_access(fwrt->trans))
|
||||
return -EBUSY;
|
||||
|
||||
dphy_addr = (reg->dev_addr.offset) ? WFPM_LMAC2_PS_CTL_RW :
|
||||
|
@ -1082,7 +1077,7 @@ iwl_dump_ini_prph_phy_iter(struct iwl_fw_runtime *fwrt,
|
|||
*val++ = cpu_to_le32(prph_val);
|
||||
}
|
||||
|
||||
iwl_trans_release_nic_access(fwrt->trans, &flags);
|
||||
iwl_trans_release_nic_access(fwrt->trans);
|
||||
return sizeof(*range) + le32_to_cpu(range->range_data_size);
|
||||
}
|
||||
|
||||
|
@ -1297,13 +1292,12 @@ static int iwl_dump_ini_txf_iter(struct iwl_fw_runtime *fwrt,
|
|||
u32 registers_num = iwl_tlv_array_len(reg_data->reg_tlv, reg, addrs);
|
||||
u32 registers_size = registers_num * sizeof(*reg_dump);
|
||||
__le32 *data;
|
||||
unsigned long flags;
|
||||
int i;
|
||||
|
||||
if (!iwl_ini_txf_iter(fwrt, reg_data, idx))
|
||||
return -EIO;
|
||||
|
||||
if (!iwl_trans_grab_nic_access(fwrt->trans, &flags))
|
||||
if (!iwl_trans_grab_nic_access(fwrt->trans))
|
||||
return -EBUSY;
|
||||
|
||||
range->fifo_hdr.fifo_num = cpu_to_le32(iter->fifo);
|
||||
|
@ -1345,7 +1339,7 @@ static int iwl_dump_ini_txf_iter(struct iwl_fw_runtime *fwrt,
|
|||
*data++ = cpu_to_le32(iwl_read_prph_no_grab(fwrt->trans, addr));
|
||||
|
||||
out:
|
||||
iwl_trans_release_nic_access(fwrt->trans, &flags);
|
||||
iwl_trans_release_nic_access(fwrt->trans);
|
||||
|
||||
return sizeof(*range) + le32_to_cpu(range->range_data_size);
|
||||
}
|
||||
|
@ -1429,14 +1423,13 @@ static int iwl_dump_ini_rxf_iter(struct iwl_fw_runtime *fwrt,
|
|||
u32 registers_num = iwl_tlv_array_len(reg_data->reg_tlv, reg, addrs);
|
||||
u32 registers_size = registers_num * sizeof(*reg_dump);
|
||||
__le32 *data;
|
||||
unsigned long flags;
|
||||
int i;
|
||||
|
||||
iwl_ini_get_rxf_data(fwrt, reg_data, &rxf_data);
|
||||
if (!rxf_data.size)
|
||||
return -EIO;
|
||||
|
||||
if (!iwl_trans_grab_nic_access(fwrt->trans, &flags))
|
||||
if (!iwl_trans_grab_nic_access(fwrt->trans))
|
||||
return -EBUSY;
|
||||
|
||||
range->fifo_hdr.fifo_num = cpu_to_le32(rxf_data.fifo_num);
|
||||
|
@ -1479,7 +1472,7 @@ static int iwl_dump_ini_rxf_iter(struct iwl_fw_runtime *fwrt,
|
|||
*data++ = cpu_to_le32(iwl_read_prph_no_grab(fwrt->trans, addr));
|
||||
|
||||
out:
|
||||
iwl_trans_release_nic_access(fwrt->trans, &flags);
|
||||
iwl_trans_release_nic_access(fwrt->trans);
|
||||
|
||||
return sizeof(*range) + le32_to_cpu(range->range_data_size);
|
||||
}
|
||||
|
@ -1596,9 +1589,8 @@ iwl_dump_ini_mon_fill_header(struct iwl_fw_runtime *fwrt,
|
|||
{
|
||||
struct iwl_fw_ini_region_tlv *reg = (void *)reg_data->reg_tlv->data;
|
||||
u32 alloc_id = le32_to_cpu(reg->dram_alloc_id);
|
||||
unsigned long flags;
|
||||
|
||||
if (!iwl_trans_grab_nic_access(fwrt->trans, &flags)) {
|
||||
if (!iwl_trans_grab_nic_access(fwrt->trans)) {
|
||||
IWL_ERR(fwrt, "Failed to get monitor header\n");
|
||||
return NULL;
|
||||
}
|
||||
|
@ -1615,7 +1607,7 @@ iwl_dump_ini_mon_fill_header(struct iwl_fw_runtime *fwrt,
|
|||
data->cur_frag = iwl_get_mon_reg(fwrt, alloc_id,
|
||||
&addrs->cur_frag);
|
||||
|
||||
iwl_trans_release_nic_access(fwrt->trans, &flags);
|
||||
iwl_trans_release_nic_access(fwrt->trans);
|
||||
|
||||
data->header.version = cpu_to_le32(IWL_INI_DUMP_VER);
|
||||
|
||||
|
@ -2073,7 +2065,8 @@ static u32 iwl_dump_ini_info(struct iwl_fw_runtime *fwrt,
|
|||
dump->umac_minor = cpu_to_le32(fwrt->dump.fw_ver.umac_minor);
|
||||
|
||||
dump->fw_mon_mode = cpu_to_le32(fwrt->trans->dbg.ini_dest);
|
||||
dump->regions_mask = trigger->regions_mask;
|
||||
dump->regions_mask = trigger->regions_mask &
|
||||
~cpu_to_le64(fwrt->trans->dbg.unsupported_region_msk);
|
||||
|
||||
dump->build_tag_len = cpu_to_le32(sizeof(dump->build_tag));
|
||||
memcpy(dump->build_tag, fwrt->fw->human_readable,
|
||||
|
@ -2202,7 +2195,8 @@ static u32 iwl_dump_ini_trigger(struct iwl_fw_runtime *fwrt,
|
|||
};
|
||||
int i;
|
||||
u32 size = 0;
|
||||
u64 regions_mask = le64_to_cpu(trigger->regions_mask);
|
||||
u64 regions_mask = le64_to_cpu(trigger->regions_mask) &
|
||||
~(fwrt->trans->dbg.unsupported_region_msk);
|
||||
|
||||
BUILD_BUG_ON(sizeof(trigger->regions_mask) != sizeof(regions_mask));
|
||||
BUILD_BUG_ON((sizeof(trigger->regions_mask) * BITS_PER_BYTE) <
|
||||
|
@ -2453,7 +2447,8 @@ int iwl_fw_dbg_error_collect(struct iwl_fw_runtime *fwrt,
|
|||
return -EIO;
|
||||
|
||||
if (iwl_trans_dbg_ini_valid(fwrt->trans)) {
|
||||
if (trig_type != FW_DBG_TRIGGER_ALIVE_TIMEOUT)
|
||||
if (trig_type != FW_DBG_TRIGGER_ALIVE_TIMEOUT &&
|
||||
trig_type != FW_DBG_TRIGGER_DRIVER)
|
||||
return -EIO;
|
||||
|
||||
iwl_dbg_tlv_time_point(fwrt,
|
||||
|
@ -2760,7 +2755,6 @@ IWL_EXPORT_SYMBOL(iwl_fw_dbg_stop_sync);
|
|||
void iwl_fw_error_print_fseq_regs(struct iwl_fw_runtime *fwrt)
|
||||
{
|
||||
struct iwl_trans *trans = fwrt->trans;
|
||||
unsigned long flags;
|
||||
int i;
|
||||
struct {
|
||||
u32 addr;
|
||||
|
@ -2780,7 +2774,7 @@ void iwl_fw_error_print_fseq_regs(struct iwl_fw_runtime *fwrt)
|
|||
FSEQ_REG(CNVR_SCU_SD_REGS_SD_REG_ACTIVE_VDIG_MIRROR),
|
||||
};
|
||||
|
||||
if (!iwl_trans_grab_nic_access(trans, &flags))
|
||||
if (!iwl_trans_grab_nic_access(trans))
|
||||
return;
|
||||
|
||||
IWL_ERR(fwrt, "Fseq Registers:\n");
|
||||
|
@ -2790,7 +2784,7 @@ void iwl_fw_error_print_fseq_regs(struct iwl_fw_runtime *fwrt)
|
|||
iwl_read_prph_no_grab(trans, fseq_regs[i].addr),
|
||||
fseq_regs[i].str);
|
||||
|
||||
iwl_trans_release_nic_access(trans, &flags);
|
||||
iwl_trans_release_nic_access(trans);
|
||||
}
|
||||
IWL_EXPORT_SYMBOL(iwl_fw_error_print_fseq_regs);
|
||||
|
||||
|
|
|
@ -441,6 +441,7 @@ enum iwl_ucode_tlv_capa {
|
|||
IWL_UCODE_TLV_CAPA_PSC_CHAN_SUPPORT = (__force iwl_ucode_tlv_capa_t)98,
|
||||
|
||||
IWL_UCODE_TLV_CAPA_BIGTK_SUPPORT = (__force iwl_ucode_tlv_capa_t)100,
|
||||
IWL_UCODE_TLV_CAPA_RFIM_SUPPORT = (__force iwl_ucode_tlv_capa_t)102,
|
||||
|
||||
NUM_IWL_UCODE_TLV_CAPA
|
||||
#ifdef __CHECKER__
|
||||
|
|
|
@ -1,9 +1,7 @@
|
|||
// SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
|
||||
/******************************************************************************
|
||||
*
|
||||
* Copyright(c) 2020 Intel Corporation
|
||||
*
|
||||
*****************************************************************************/
|
||||
/*
|
||||
* Copyright(c) 2020-2021 Intel Corporation
|
||||
*/
|
||||
|
||||
#include "iwl-drv.h"
|
||||
#include "pnvm.h"
|
||||
|
@ -12,6 +10,7 @@
|
|||
#include "fw/api/commands.h"
|
||||
#include "fw/api/nvm-reg.h"
|
||||
#include "fw/api/alive.h"
|
||||
#include <linux/efi.h>
|
||||
|
||||
struct iwl_pnvm_section {
|
||||
__le32 offset;
|
||||
|
@ -198,14 +197,14 @@ static int iwl_pnvm_parse(struct iwl_trans *trans, const u8 *data,
|
|||
le32_to_cpu(sku_id->data[1]),
|
||||
le32_to_cpu(sku_id->data[2]));
|
||||
|
||||
data += sizeof(*tlv) + ALIGN(tlv_len, 4);
|
||||
len -= ALIGN(tlv_len, 4);
|
||||
|
||||
if (trans->sku_id[0] == le32_to_cpu(sku_id->data[0]) &&
|
||||
trans->sku_id[1] == le32_to_cpu(sku_id->data[1]) &&
|
||||
trans->sku_id[2] == le32_to_cpu(sku_id->data[2])) {
|
||||
int ret;
|
||||
|
||||
data += sizeof(*tlv) + ALIGN(tlv_len, 4);
|
||||
len -= ALIGN(tlv_len, 4);
|
||||
|
||||
ret = iwl_pnvm_handle_section(trans, data, len);
|
||||
if (!ret)
|
||||
return 0;
|
||||
|
@ -221,51 +220,170 @@ static int iwl_pnvm_parse(struct iwl_trans *trans, const u8 *data,
|
|||
return -ENOENT;
|
||||
}
|
||||
|
||||
/*
|
||||
* This is known to be broken on v4.19 and to work on v5.4. Until we
|
||||
* figure out why this is the case and how to make it work, simply
|
||||
* disable the feature in old kernels.
|
||||
*/
|
||||
#if defined(CONFIG_EFI)
|
||||
|
||||
#define IWL_EFI_VAR_GUID EFI_GUID(0x92daaf2f, 0xc02b, 0x455b, \
|
||||
0xb2, 0xec, 0xf5, 0xa3, \
|
||||
0x59, 0x4f, 0x4a, 0xea)
|
||||
|
||||
#define IWL_UEFI_OEM_PNVM_NAME L"UefiCnvWlanOemSignedPnvm"
|
||||
|
||||
#define IWL_HARDCODED_PNVM_SIZE 4096
|
||||
|
||||
struct pnvm_sku_package {
|
||||
u8 rev;
|
||||
u8 reserved1[3];
|
||||
u32 total_size;
|
||||
u8 n_skus;
|
||||
u8 reserved2[11];
|
||||
u8 data[];
|
||||
};
|
||||
|
||||
static int iwl_pnvm_get_from_efi(struct iwl_trans *trans,
|
||||
u8 **data, size_t *len)
|
||||
{
|
||||
struct efivar_entry *pnvm_efivar;
|
||||
struct pnvm_sku_package *package;
|
||||
unsigned long package_size;
|
||||
int err;
|
||||
|
||||
pnvm_efivar = kzalloc(sizeof(*pnvm_efivar), GFP_KERNEL);
|
||||
if (!pnvm_efivar)
|
||||
return -ENOMEM;
|
||||
|
||||
memcpy(&pnvm_efivar->var.VariableName, IWL_UEFI_OEM_PNVM_NAME,
|
||||
sizeof(IWL_UEFI_OEM_PNVM_NAME));
|
||||
pnvm_efivar->var.VendorGuid = IWL_EFI_VAR_GUID;
|
||||
|
||||
/*
|
||||
* TODO: we hardcode a maximum length here, because reading
|
||||
* from the UEFI is not working. To implement this properly,
|
||||
* we have to call efivar_entry_size().
|
||||
*/
|
||||
package_size = IWL_HARDCODED_PNVM_SIZE;
|
||||
|
||||
package = kmalloc(package_size, GFP_KERNEL);
|
||||
if (!package) {
|
||||
err = -ENOMEM;
|
||||
goto out;
|
||||
}
|
||||
|
||||
err = efivar_entry_get(pnvm_efivar, NULL, &package_size, package);
|
||||
if (err) {
|
||||
IWL_DEBUG_FW(trans,
|
||||
"PNVM UEFI variable not found %d (len %zd)\n",
|
||||
err, package_size);
|
||||
goto out;
|
||||
}
|
||||
|
||||
IWL_DEBUG_FW(trans, "Read PNVM fro UEFI with size %zd\n", package_size);
|
||||
|
||||
*data = kmemdup(package->data, *len, GFP_KERNEL);
|
||||
if (!*data)
|
||||
err = -ENOMEM;
|
||||
*len = package_size - sizeof(*package);
|
||||
|
||||
out:
|
||||
kfree(package);
|
||||
kfree(pnvm_efivar);
|
||||
|
||||
return err;
|
||||
}
|
||||
#else /* CONFIG_EFI */
|
||||
static inline int iwl_pnvm_get_from_efi(struct iwl_trans *trans,
|
||||
u8 **data, size_t *len)
|
||||
{
|
||||
return -EOPNOTSUPP;
|
||||
}
|
||||
#endif /* CONFIG_EFI */
|
||||
|
||||
static int iwl_pnvm_get_from_fs(struct iwl_trans *trans, u8 **data, size_t *len)
|
||||
{
|
||||
const struct firmware *pnvm;
|
||||
char pnvm_name[64];
|
||||
int ret;
|
||||
|
||||
/*
|
||||
* The prefix unfortunately includes a hyphen at the end, so
|
||||
* don't add the dot here...
|
||||
*/
|
||||
snprintf(pnvm_name, sizeof(pnvm_name), "%spnvm",
|
||||
trans->cfg->fw_name_pre);
|
||||
|
||||
/* ...but replace the hyphen with the dot here. */
|
||||
if (strlen(trans->cfg->fw_name_pre) < sizeof(pnvm_name))
|
||||
pnvm_name[strlen(trans->cfg->fw_name_pre) - 1] = '.';
|
||||
|
||||
ret = firmware_request_nowarn(&pnvm, pnvm_name, trans->dev);
|
||||
if (ret) {
|
||||
IWL_DEBUG_FW(trans, "PNVM file %s not found %d\n",
|
||||
pnvm_name, ret);
|
||||
return ret;
|
||||
}
|
||||
|
||||
*data = kmemdup(pnvm->data, pnvm->size, GFP_KERNEL);
|
||||
if (!*data)
|
||||
return -ENOMEM;
|
||||
|
||||
*len = pnvm->size;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int iwl_pnvm_load(struct iwl_trans *trans,
|
||||
struct iwl_notif_wait_data *notif_wait)
|
||||
{
|
||||
u8 *data;
|
||||
size_t len;
|
||||
struct iwl_notification_wait pnvm_wait;
|
||||
static const u16 ntf_cmds[] = { WIDE_ID(REGULATORY_AND_NVM_GROUP,
|
||||
PNVM_INIT_COMPLETE_NTFY) };
|
||||
int ret;
|
||||
|
||||
/* if the SKU_ID is empty, there's nothing to do */
|
||||
if (!trans->sku_id[0] && !trans->sku_id[1] && !trans->sku_id[2])
|
||||
return 0;
|
||||
|
||||
/* load from disk only if we haven't done it (or tried) before */
|
||||
if (!trans->pnvm_loaded) {
|
||||
const struct firmware *pnvm;
|
||||
char pnvm_name[64];
|
||||
int ret;
|
||||
|
||||
/*
|
||||
* The prefix unfortunately includes a hyphen at the end, so
|
||||
* don't add the dot here...
|
||||
*/
|
||||
snprintf(pnvm_name, sizeof(pnvm_name), "%spnvm",
|
||||
trans->cfg->fw_name_pre);
|
||||
|
||||
/* ...but replace the hyphen with the dot here. */
|
||||
if (strlen(trans->cfg->fw_name_pre) < sizeof(pnvm_name))
|
||||
pnvm_name[strlen(trans->cfg->fw_name_pre) - 1] = '.';
|
||||
|
||||
ret = firmware_request_nowarn(&pnvm, pnvm_name, trans->dev);
|
||||
if (ret) {
|
||||
IWL_DEBUG_FW(trans, "PNVM file %s not found %d\n",
|
||||
pnvm_name, ret);
|
||||
/*
|
||||
* Pretend we've loaded it - at least we've tried and
|
||||
* couldn't load it at all, so there's no point in
|
||||
* trying again over and over.
|
||||
*/
|
||||
trans->pnvm_loaded = true;
|
||||
} else {
|
||||
iwl_pnvm_parse(trans, pnvm->data, pnvm->size);
|
||||
|
||||
release_firmware(pnvm);
|
||||
}
|
||||
/*
|
||||
* If we already loaded (or tried to load) it before, we just
|
||||
* need to set it again.
|
||||
*/
|
||||
if (trans->pnvm_loaded) {
|
||||
ret = iwl_trans_set_pnvm(trans, NULL, 0);
|
||||
if (ret)
|
||||
return ret;
|
||||
goto skip_parse;
|
||||
}
|
||||
|
||||
/* First attempt to get the PNVM from BIOS */
|
||||
ret = iwl_pnvm_get_from_efi(trans, &data, &len);
|
||||
if (!ret)
|
||||
goto parse;
|
||||
|
||||
/* If it's not available, try from the filesystem */
|
||||
ret = iwl_pnvm_get_from_fs(trans, &data, &len);
|
||||
if (ret) {
|
||||
/*
|
||||
* Pretend we've loaded it - at least we've tried and
|
||||
* couldn't load it at all, so there's no point in
|
||||
* trying again over and over.
|
||||
*/
|
||||
trans->pnvm_loaded = true;
|
||||
|
||||
goto skip_parse;
|
||||
}
|
||||
|
||||
parse:
|
||||
iwl_pnvm_parse(trans, data, len);
|
||||
|
||||
kfree(data);
|
||||
|
||||
skip_parse:
|
||||
iwl_init_notification_wait(notif_wait, &pnvm_wait,
|
||||
ntf_cmds, ARRAY_SIZE(ntf_cmds),
|
||||
iwl_pnvm_complete_fn, trans);
|
||||
|
|
|
@ -325,10 +325,6 @@ struct iwl_fw_mon_regs {
|
|||
* @features: hw features, any combination of feature_passlist
|
||||
* @pwr_tx_backoffs: translation table between power limits and backoffs
|
||||
* @max_tx_agg_size: max TX aggregation size of the ADDBA request/response
|
||||
* @max_ht_ampdu_factor: the exponent of the max length of A-MPDU that the
|
||||
* station can receive in HT
|
||||
* @max_vht_ampdu_exponent: the exponent of the max length of A-MPDU that the
|
||||
* station can receive in VHT
|
||||
* @dccm_offset: offset from which DCCM begins
|
||||
* @dccm_len: length of DCCM (including runtime stack CCM)
|
||||
* @dccm2_offset: offset from which the second DCCM begins
|
||||
|
@ -395,8 +391,6 @@ struct iwl_cfg {
|
|||
u8 non_shared_ant;
|
||||
u8 nvm_hw_section_num;
|
||||
u8 max_tx_agg_size;
|
||||
u8 max_ht_ampdu_exponent;
|
||||
u8 max_vht_ampdu_exponent;
|
||||
u8 ucode_api_max;
|
||||
u8 ucode_api_min;
|
||||
u16 num_rbds;
|
||||
|
@ -445,6 +439,9 @@ struct iwl_cfg {
|
|||
#define IWL_CFG_CORES_BT 0x0
|
||||
#define IWL_CFG_CORES_BT_GNSS 0x5
|
||||
|
||||
#define IWL_CFG_NO_CDB 0x0
|
||||
#define IWL_CFG_CDB 0x1
|
||||
|
||||
#define IWL_SUBDEVICE_RF_ID(subdevice) ((u16)((subdevice) & 0x00F0) >> 4)
|
||||
#define IWL_SUBDEVICE_NO_160(subdevice) ((u16)((subdevice) & 0x0200) >> 9)
|
||||
#define IWL_SUBDEVICE_CORES(subdevice) ((u16)((subdevice) & 0x1C00) >> 10)
|
||||
|
@ -458,6 +455,7 @@ struct iwl_dev_info {
|
|||
u8 rf_id;
|
||||
u8 no_160;
|
||||
u8 cores;
|
||||
u8 cdb;
|
||||
const struct iwl_cfg *cfg;
|
||||
const char *name;
|
||||
};
|
||||
|
@ -606,9 +604,13 @@ extern const struct iwl_cfg iwlax411_2ax_cfg_sosnj_gf4_a0;
|
|||
extern const struct iwl_cfg iwlax211_cfg_snj_gf_a0;
|
||||
extern const struct iwl_cfg iwl_cfg_snj_hr_b0;
|
||||
extern const struct iwl_cfg iwl_cfg_snj_a0_jf_b0;
|
||||
extern const struct iwl_cfg iwl_cfg_ma_a0_hr_b0;
|
||||
extern const struct iwl_cfg iwl_cfg_ma_a0_gf_a0;
|
||||
extern const struct iwl_cfg iwl_cfg_ma_a0_gf4_a0;
|
||||
extern const struct iwl_cfg iwl_cfg_ma_a0_mr_a0;
|
||||
extern const struct iwl_cfg iwl_cfg_snj_a0_mr_a0;
|
||||
extern const struct iwl_cfg iwl_cfg_so_a0_hr_a0;
|
||||
extern const struct iwl_cfg iwl_cfg_quz_a0_hr_b0;
|
||||
#endif /* CONFIG_IWLMVM */
|
||||
|
||||
#endif /* __IWL_CONFIG_H__ */
|
||||
|
|
|
@ -277,6 +277,8 @@
|
|||
#define CSR_HW_RFID_DASH(_val) (((_val) & 0x00000F0) >> 4)
|
||||
#define CSR_HW_RFID_STEP(_val) (((_val) & 0x0000F00) >> 8)
|
||||
#define CSR_HW_RFID_TYPE(_val) (((_val) & 0x0FFF000) >> 12)
|
||||
#define CSR_HW_RFID_IS_CDB(_val) (((_val) & 0x10000000) >> 28)
|
||||
#define CSR_HW_RFID_IS_JACKET(_val) (((_val) & 0x20000000) >> 29)
|
||||
|
||||
/**
|
||||
* hw_rev values
|
||||
|
|
|
@ -61,7 +61,8 @@ dbg_ver_table[IWL_DBG_TLV_TYPE_NUM] = {
|
|||
[IWL_DBG_TLV_TYPE_TRIGGER] = {.min_ver = 1, .max_ver = 1,},
|
||||
};
|
||||
|
||||
static int iwl_dbg_tlv_add(struct iwl_ucode_tlv *tlv, struct list_head *list)
|
||||
static int iwl_dbg_tlv_add(const struct iwl_ucode_tlv *tlv,
|
||||
struct list_head *list)
|
||||
{
|
||||
u32 len = le32_to_cpu(tlv->length);
|
||||
struct iwl_dbg_tlv_node *node;
|
||||
|
@ -76,9 +77,9 @@ static int iwl_dbg_tlv_add(struct iwl_ucode_tlv *tlv, struct list_head *list)
|
|||
return 0;
|
||||
}
|
||||
|
||||
static bool iwl_dbg_tlv_ver_support(struct iwl_ucode_tlv *tlv)
|
||||
static bool iwl_dbg_tlv_ver_support(const struct iwl_ucode_tlv *tlv)
|
||||
{
|
||||
struct iwl_fw_ini_header *hdr = (void *)&tlv->data[0];
|
||||
const struct iwl_fw_ini_header *hdr = (const void *)&tlv->data[0];
|
||||
u32 type = le32_to_cpu(tlv->type);
|
||||
u32 tlv_idx = type - IWL_UCODE_TLV_DEBUG_BASE;
|
||||
u32 ver = le32_to_cpu(hdr->version);
|
||||
|
@ -91,9 +92,9 @@ static bool iwl_dbg_tlv_ver_support(struct iwl_ucode_tlv *tlv)
|
|||
}
|
||||
|
||||
static int iwl_dbg_tlv_alloc_debug_info(struct iwl_trans *trans,
|
||||
struct iwl_ucode_tlv *tlv)
|
||||
const struct iwl_ucode_tlv *tlv)
|
||||
{
|
||||
struct iwl_fw_ini_debug_info_tlv *debug_info = (void *)tlv->data;
|
||||
const struct iwl_fw_ini_debug_info_tlv *debug_info = (const void *)tlv->data;
|
||||
|
||||
if (le32_to_cpu(tlv->length) != sizeof(*debug_info))
|
||||
return -EINVAL;
|
||||
|
@ -105,9 +106,9 @@ static int iwl_dbg_tlv_alloc_debug_info(struct iwl_trans *trans,
|
|||
}
|
||||
|
||||
static int iwl_dbg_tlv_alloc_buf_alloc(struct iwl_trans *trans,
|
||||
struct iwl_ucode_tlv *tlv)
|
||||
const struct iwl_ucode_tlv *tlv)
|
||||
{
|
||||
struct iwl_fw_ini_allocation_tlv *alloc = (void *)tlv->data;
|
||||
const struct iwl_fw_ini_allocation_tlv *alloc = (const void *)tlv->data;
|
||||
u32 buf_location;
|
||||
u32 alloc_id;
|
||||
|
||||
|
@ -145,9 +146,9 @@ err:
|
|||
}
|
||||
|
||||
static int iwl_dbg_tlv_alloc_hcmd(struct iwl_trans *trans,
|
||||
struct iwl_ucode_tlv *tlv)
|
||||
const struct iwl_ucode_tlv *tlv)
|
||||
{
|
||||
struct iwl_fw_ini_hcmd_tlv *hcmd = (void *)tlv->data;
|
||||
const struct iwl_fw_ini_hcmd_tlv *hcmd = (const void *)tlv->data;
|
||||
u32 tp = le32_to_cpu(hcmd->time_point);
|
||||
|
||||
if (le32_to_cpu(tlv->length) <= sizeof(*hcmd))
|
||||
|
@ -169,9 +170,9 @@ static int iwl_dbg_tlv_alloc_hcmd(struct iwl_trans *trans,
|
|||
}
|
||||
|
||||
static int iwl_dbg_tlv_alloc_region(struct iwl_trans *trans,
|
||||
struct iwl_ucode_tlv *tlv)
|
||||
const struct iwl_ucode_tlv *tlv)
|
||||
{
|
||||
struct iwl_fw_ini_region_tlv *reg = (void *)tlv->data;
|
||||
const struct iwl_fw_ini_region_tlv *reg = (const void *)tlv->data;
|
||||
struct iwl_ucode_tlv **active_reg;
|
||||
u32 id = le32_to_cpu(reg->id);
|
||||
u32 type = le32_to_cpu(reg->type);
|
||||
|
@ -214,9 +215,10 @@ static int iwl_dbg_tlv_alloc_region(struct iwl_trans *trans,
|
|||
}
|
||||
|
||||
static int iwl_dbg_tlv_alloc_trigger(struct iwl_trans *trans,
|
||||
struct iwl_ucode_tlv *tlv)
|
||||
const struct iwl_ucode_tlv *tlv)
|
||||
{
|
||||
struct iwl_fw_ini_trigger_tlv *trig = (void *)tlv->data;
|
||||
const struct iwl_fw_ini_trigger_tlv *trig = (const void *)tlv->data;
|
||||
struct iwl_fw_ini_trigger_tlv *dup_trig;
|
||||
u32 tp = le32_to_cpu(trig->time_point);
|
||||
struct iwl_ucode_tlv *dup = NULL;
|
||||
int ret;
|
||||
|
@ -237,8 +239,8 @@ static int iwl_dbg_tlv_alloc_trigger(struct iwl_trans *trans,
|
|||
GFP_KERNEL);
|
||||
if (!dup)
|
||||
return -ENOMEM;
|
||||
trig = (void *)dup->data;
|
||||
trig->occurrences = cpu_to_le32(-1);
|
||||
dup_trig = (void *)dup->data;
|
||||
dup_trig->occurrences = cpu_to_le32(-1);
|
||||
tlv = dup;
|
||||
}
|
||||
|
||||
|
@ -249,7 +251,7 @@ static int iwl_dbg_tlv_alloc_trigger(struct iwl_trans *trans,
|
|||
}
|
||||
|
||||
static int (*dbg_tlv_alloc[])(struct iwl_trans *trans,
|
||||
struct iwl_ucode_tlv *tlv) = {
|
||||
const struct iwl_ucode_tlv *tlv) = {
|
||||
[IWL_DBG_TLV_TYPE_DEBUG_INFO] = iwl_dbg_tlv_alloc_debug_info,
|
||||
[IWL_DBG_TLV_TYPE_BUF_ALLOC] = iwl_dbg_tlv_alloc_buf_alloc,
|
||||
[IWL_DBG_TLV_TYPE_HCMD] = iwl_dbg_tlv_alloc_hcmd,
|
||||
|
@ -257,10 +259,10 @@ static int (*dbg_tlv_alloc[])(struct iwl_trans *trans,
|
|||
[IWL_DBG_TLV_TYPE_TRIGGER] = iwl_dbg_tlv_alloc_trigger,
|
||||
};
|
||||
|
||||
void iwl_dbg_tlv_alloc(struct iwl_trans *trans, struct iwl_ucode_tlv *tlv,
|
||||
void iwl_dbg_tlv_alloc(struct iwl_trans *trans, const struct iwl_ucode_tlv *tlv,
|
||||
bool ext)
|
||||
{
|
||||
struct iwl_fw_ini_header *hdr = (void *)&tlv->data[0];
|
||||
const struct iwl_fw_ini_header *hdr = (const void *)&tlv->data[0];
|
||||
u32 type = le32_to_cpu(tlv->type);
|
||||
u32 tlv_idx = type - IWL_UCODE_TLV_DEBUG_BASE;
|
||||
u32 domain = le32_to_cpu(hdr->domain);
|
||||
|
@ -396,7 +398,7 @@ void iwl_dbg_tlv_free(struct iwl_trans *trans)
|
|||
static int iwl_dbg_tlv_parse_bin(struct iwl_trans *trans, const u8 *data,
|
||||
size_t len)
|
||||
{
|
||||
struct iwl_ucode_tlv *tlv;
|
||||
const struct iwl_ucode_tlv *tlv;
|
||||
u32 tlv_len;
|
||||
|
||||
while (len >= sizeof(*tlv)) {
|
||||
|
@ -737,12 +739,12 @@ static void iwl_dbg_tlv_set_periodic_trigs(struct iwl_fw_runtime *fwrt)
|
|||
}
|
||||
}
|
||||
|
||||
static bool is_trig_data_contained(struct iwl_ucode_tlv *new,
|
||||
struct iwl_ucode_tlv *old)
|
||||
static bool is_trig_data_contained(const struct iwl_ucode_tlv *new,
|
||||
const struct iwl_ucode_tlv *old)
|
||||
{
|
||||
struct iwl_fw_ini_trigger_tlv *new_trig = (void *)new->data;
|
||||
struct iwl_fw_ini_trigger_tlv *old_trig = (void *)old->data;
|
||||
__le32 *new_data = new_trig->data, *old_data = old_trig->data;
|
||||
const struct iwl_fw_ini_trigger_tlv *new_trig = (const void *)new->data;
|
||||
const struct iwl_fw_ini_trigger_tlv *old_trig = (const void *)old->data;
|
||||
const __le32 *new_data = new_trig->data, *old_data = old_trig->data;
|
||||
u32 new_dwords_num = iwl_tlv_array_len(new, new_trig, data);
|
||||
u32 old_dwords_num = iwl_tlv_array_len(old, old_trig, data);
|
||||
int i, j;
|
||||
|
@ -957,6 +959,7 @@ static void iwl_dbg_tlv_init_cfg(struct iwl_fw_runtime *fwrt)
|
|||
{
|
||||
enum iwl_fw_ini_buffer_location *ini_dest = &fwrt->trans->dbg.ini_dest;
|
||||
int ret, i;
|
||||
u32 failed_alloc = 0;
|
||||
|
||||
if (*ini_dest != IWL_FW_INI_LOCATION_INVALID)
|
||||
return;
|
||||
|
@ -988,10 +991,43 @@ static void iwl_dbg_tlv_init_cfg(struct iwl_fw_runtime *fwrt)
|
|||
continue;
|
||||
|
||||
ret = iwl_dbg_tlv_alloc_fragments(fwrt, i);
|
||||
if (ret)
|
||||
|
||||
if (ret) {
|
||||
IWL_WARN(fwrt,
|
||||
"WRT: Failed to allocate DRAM buffer for allocation id %d, ret=%d\n",
|
||||
i, ret);
|
||||
failed_alloc |= BIT(i);
|
||||
}
|
||||
}
|
||||
|
||||
if (!failed_alloc)
|
||||
return;
|
||||
|
||||
for (i = 0; i < ARRAY_SIZE(fwrt->trans->dbg.active_regions) && failed_alloc; i++) {
|
||||
struct iwl_fw_ini_region_tlv *reg;
|
||||
struct iwl_ucode_tlv **active_reg =
|
||||
&fwrt->trans->dbg.active_regions[i];
|
||||
u32 reg_type;
|
||||
|
||||
if (!*active_reg)
|
||||
continue;
|
||||
|
||||
reg = (void *)(*active_reg)->data;
|
||||
reg_type = le32_to_cpu(reg->type);
|
||||
|
||||
if (reg_type != IWL_FW_INI_REGION_DRAM_BUFFER ||
|
||||
!(BIT(le32_to_cpu(reg->dram_alloc_id)) & failed_alloc))
|
||||
continue;
|
||||
|
||||
IWL_DEBUG_FW(fwrt,
|
||||
"WRT: removing allocation id %d from region id %d\n",
|
||||
le32_to_cpu(reg->dram_alloc_id), i);
|
||||
|
||||
failed_alloc &= ~le32_to_cpu(reg->dram_alloc_id);
|
||||
fwrt->trans->dbg.unsupported_region_msk |= BIT(i);
|
||||
|
||||
kfree(*active_reg);
|
||||
*active_reg = NULL;
|
||||
}
|
||||
}
|
||||
|
||||
|
|
|
@ -1,12 +1,14 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */
|
||||
/*
|
||||
* Copyright (C) 2018-2019 Intel Corporation
|
||||
* Copyright (C) 2018-2020 Intel Corporation
|
||||
*/
|
||||
#ifndef __iwl_dbg_tlv_h__
|
||||
#define __iwl_dbg_tlv_h__
|
||||
|
||||
#include <linux/device.h>
|
||||
#include <linux/types.h>
|
||||
#include <fw/file.h>
|
||||
#include <fw/api/dbg-tlv.h>
|
||||
|
||||
/**
|
||||
* struct iwl_dbg_tlv_node - debug TLV node
|
||||
|
@ -43,7 +45,7 @@ struct iwl_fw_runtime;
|
|||
|
||||
void iwl_dbg_tlv_load_bin(struct device *dev, struct iwl_trans *trans);
|
||||
void iwl_dbg_tlv_free(struct iwl_trans *trans);
|
||||
void iwl_dbg_tlv_alloc(struct iwl_trans *trans, struct iwl_ucode_tlv *tlv,
|
||||
void iwl_dbg_tlv_alloc(struct iwl_trans *trans, const struct iwl_ucode_tlv *tlv,
|
||||
bool ext);
|
||||
void iwl_dbg_tlv_init(struct iwl_trans *trans);
|
||||
void iwl_dbg_tlv_time_point(struct iwl_fw_runtime *fwrt,
|
||||
|
|
|
@ -559,7 +559,7 @@ static int iwl_parse_tlv_firmware(struct iwl_drv *drv,
|
|||
bool *usniffer_images)
|
||||
{
|
||||
struct iwl_tlv_ucode_header *ucode = (void *)ucode_raw->data;
|
||||
struct iwl_ucode_tlv *tlv;
|
||||
const struct iwl_ucode_tlv *tlv;
|
||||
size_t len = ucode_raw->size;
|
||||
const u8 *data;
|
||||
u32 tlv_len;
|
||||
|
|
|
@ -715,7 +715,7 @@ void iwl_init_ht_hw_capab(struct iwl_trans *trans,
|
|||
iwlwifi_mod_params.amsdu_size >= IWL_AMSDU_8K)
|
||||
ht_info->cap |= IEEE80211_HT_CAP_MAX_AMSDU;
|
||||
|
||||
ht_info->ampdu_factor = cfg->max_ht_ampdu_exponent;
|
||||
ht_info->ampdu_factor = IEEE80211_HT_MAX_AMPDU_64K;
|
||||
ht_info->ampdu_density = IEEE80211_HT_MPDU_DENSITY_4;
|
||||
|
||||
ht_info->mcs.rx_mask[0] = 0xFF;
|
||||
|
|
|
@ -66,10 +66,10 @@ IWL_EXPORT_SYMBOL(iwl_poll_bit);
|
|||
u32 iwl_read_direct32(struct iwl_trans *trans, u32 reg)
|
||||
{
|
||||
u32 value = 0x5a5a5a5a;
|
||||
unsigned long flags;
|
||||
if (iwl_trans_grab_nic_access(trans, &flags)) {
|
||||
|
||||
if (iwl_trans_grab_nic_access(trans)) {
|
||||
value = iwl_read32(trans, reg);
|
||||
iwl_trans_release_nic_access(trans, &flags);
|
||||
iwl_trans_release_nic_access(trans);
|
||||
}
|
||||
|
||||
return value;
|
||||
|
@ -78,22 +78,18 @@ IWL_EXPORT_SYMBOL(iwl_read_direct32);
|
|||
|
||||
void iwl_write_direct32(struct iwl_trans *trans, u32 reg, u32 value)
|
||||
{
|
||||
unsigned long flags;
|
||||
|
||||
if (iwl_trans_grab_nic_access(trans, &flags)) {
|
||||
if (iwl_trans_grab_nic_access(trans)) {
|
||||
iwl_write32(trans, reg, value);
|
||||
iwl_trans_release_nic_access(trans, &flags);
|
||||
iwl_trans_release_nic_access(trans);
|
||||
}
|
||||
}
|
||||
IWL_EXPORT_SYMBOL(iwl_write_direct32);
|
||||
|
||||
void iwl_write_direct64(struct iwl_trans *trans, u64 reg, u64 value)
|
||||
{
|
||||
unsigned long flags;
|
||||
|
||||
if (iwl_trans_grab_nic_access(trans, &flags)) {
|
||||
if (iwl_trans_grab_nic_access(trans)) {
|
||||
iwl_write64(trans, reg, value);
|
||||
iwl_trans_release_nic_access(trans, &flags);
|
||||
iwl_trans_release_nic_access(trans);
|
||||
}
|
||||
}
|
||||
IWL_EXPORT_SYMBOL(iwl_write_direct64);
|
||||
|
@ -139,12 +135,11 @@ IWL_EXPORT_SYMBOL(iwl_write_prph64_no_grab);
|
|||
|
||||
u32 iwl_read_prph(struct iwl_trans *trans, u32 ofs)
|
||||
{
|
||||
unsigned long flags;
|
||||
u32 val = 0x5a5a5a5a;
|
||||
|
||||
if (iwl_trans_grab_nic_access(trans, &flags)) {
|
||||
if (iwl_trans_grab_nic_access(trans)) {
|
||||
val = iwl_read_prph_no_grab(trans, ofs);
|
||||
iwl_trans_release_nic_access(trans, &flags);
|
||||
iwl_trans_release_nic_access(trans);
|
||||
}
|
||||
return val;
|
||||
}
|
||||
|
@ -152,12 +147,10 @@ IWL_EXPORT_SYMBOL(iwl_read_prph);
|
|||
|
||||
void iwl_write_prph_delay(struct iwl_trans *trans, u32 ofs, u32 val, u32 delay_ms)
|
||||
{
|
||||
unsigned long flags;
|
||||
|
||||
if (iwl_trans_grab_nic_access(trans, &flags)) {
|
||||
if (iwl_trans_grab_nic_access(trans)) {
|
||||
mdelay(delay_ms);
|
||||
iwl_write_prph_no_grab(trans, ofs, val);
|
||||
iwl_trans_release_nic_access(trans, &flags);
|
||||
iwl_trans_release_nic_access(trans);
|
||||
}
|
||||
}
|
||||
IWL_EXPORT_SYMBOL(iwl_write_prph_delay);
|
||||
|
@ -179,13 +172,11 @@ int iwl_poll_prph_bit(struct iwl_trans *trans, u32 addr,
|
|||
|
||||
void iwl_set_bits_prph(struct iwl_trans *trans, u32 ofs, u32 mask)
|
||||
{
|
||||
unsigned long flags;
|
||||
|
||||
if (iwl_trans_grab_nic_access(trans, &flags)) {
|
||||
if (iwl_trans_grab_nic_access(trans)) {
|
||||
iwl_write_prph_no_grab(trans, ofs,
|
||||
iwl_read_prph_no_grab(trans, ofs) |
|
||||
mask);
|
||||
iwl_trans_release_nic_access(trans, &flags);
|
||||
iwl_trans_release_nic_access(trans);
|
||||
}
|
||||
}
|
||||
IWL_EXPORT_SYMBOL(iwl_set_bits_prph);
|
||||
|
@ -193,26 +184,23 @@ IWL_EXPORT_SYMBOL(iwl_set_bits_prph);
|
|||
void iwl_set_bits_mask_prph(struct iwl_trans *trans, u32 ofs,
|
||||
u32 bits, u32 mask)
|
||||
{
|
||||
unsigned long flags;
|
||||
|
||||
if (iwl_trans_grab_nic_access(trans, &flags)) {
|
||||
if (iwl_trans_grab_nic_access(trans)) {
|
||||
iwl_write_prph_no_grab(trans, ofs,
|
||||
(iwl_read_prph_no_grab(trans, ofs) &
|
||||
mask) | bits);
|
||||
iwl_trans_release_nic_access(trans, &flags);
|
||||
iwl_trans_release_nic_access(trans);
|
||||
}
|
||||
}
|
||||
IWL_EXPORT_SYMBOL(iwl_set_bits_mask_prph);
|
||||
|
||||
void iwl_clear_bits_prph(struct iwl_trans *trans, u32 ofs, u32 mask)
|
||||
{
|
||||
unsigned long flags;
|
||||
u32 val;
|
||||
|
||||
if (iwl_trans_grab_nic_access(trans, &flags)) {
|
||||
if (iwl_trans_grab_nic_access(trans)) {
|
||||
val = iwl_read_prph_no_grab(trans, ofs);
|
||||
iwl_write_prph_no_grab(trans, ofs, (val & ~mask));
|
||||
iwl_trans_release_nic_access(trans, &flags);
|
||||
iwl_trans_release_nic_access(trans);
|
||||
}
|
||||
}
|
||||
IWL_EXPORT_SYMBOL(iwl_clear_bits_prph);
|
||||
|
|
|
@ -453,8 +453,6 @@ static void iwl_init_vht_hw_capab(struct iwl_trans *trans,
|
|||
const struct iwl_cfg *cfg = trans->cfg;
|
||||
int num_rx_ants = num_of_ant(rx_chains);
|
||||
int num_tx_ants = num_of_ant(tx_chains);
|
||||
unsigned int max_ampdu_exponent = (cfg->max_vht_ampdu_exponent ?:
|
||||
IEEE80211_VHT_MAX_AMPDU_1024K);
|
||||
|
||||
vht_cap->vht_supported = true;
|
||||
|
||||
|
@ -462,7 +460,7 @@ static void iwl_init_vht_hw_capab(struct iwl_trans *trans,
|
|||
IEEE80211_VHT_CAP_RXSTBC_1 |
|
||||
IEEE80211_VHT_CAP_SU_BEAMFORMEE_CAPABLE |
|
||||
3 << IEEE80211_VHT_CAP_BEAMFORMEE_STS_SHIFT |
|
||||
max_ampdu_exponent <<
|
||||
IEEE80211_VHT_MAX_AMPDU_1024K <<
|
||||
IEEE80211_VHT_CAP_MAX_A_MPDU_LENGTH_EXPONENT_SHIFT;
|
||||
|
||||
if (data->vht160_supported)
|
||||
|
@ -585,6 +583,8 @@ static const struct ieee80211_sband_iftype_data iwl_he_capa[] = {
|
|||
IEEE80211_HE_PHY_CAP5_BEAMFORMEE_NUM_SND_DIM_UNDER_80MHZ_2 |
|
||||
IEEE80211_HE_PHY_CAP5_BEAMFORMEE_NUM_SND_DIM_ABOVE_80MHZ_2,
|
||||
.phy_cap_info[6] =
|
||||
IEEE80211_HE_PHY_CAP6_TRIG_SU_BEAMFORMER_FB |
|
||||
IEEE80211_HE_PHY_CAP6_TRIG_MU_BEAMFORMER_FB |
|
||||
IEEE80211_HE_PHY_CAP6_PPE_THRESHOLD_PRESENT,
|
||||
.phy_cap_info[7] =
|
||||
IEEE80211_HE_PHY_CAP7_POWER_BOOST_FACTOR_AR |
|
||||
|
|
|
@ -80,4 +80,5 @@ void iwl_nvm_fixups(u32 hw_id, unsigned int section, u8 *data,
|
|||
*/
|
||||
struct iwl_nvm_data *iwl_get_nvm(struct iwl_trans *trans,
|
||||
const struct iwl_fw *fw);
|
||||
|
||||
#endif /* __iwl_nvm_parse_h__ */
|
||||
|
|
|
@ -1,6 +1,6 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */
|
||||
/*
|
||||
* Copyright (C) 2005-2014, 2018-2019 Intel Corporation
|
||||
* Copyright (C) 2005-2014, 2018-2020 Intel Corporation
|
||||
* Copyright (C) 2013-2014 Intel Mobile Communications GmbH
|
||||
* Copyright (C) 2015 Intel Deutschland GmbH
|
||||
*/
|
||||
|
@ -9,6 +9,7 @@
|
|||
|
||||
#include <linux/netdevice.h>
|
||||
#include <linux/debugfs.h>
|
||||
#include "iwl-dbg-tlv.h"
|
||||
|
||||
struct iwl_op_mode;
|
||||
struct iwl_trans;
|
||||
|
@ -83,6 +84,7 @@ struct iwl_cfg;
|
|||
* @nic_config: configure NIC, called before firmware is started.
|
||||
* May sleep
|
||||
* @wimax_active: invoked when WiMax becomes active. May sleep
|
||||
* @time_point: called when transport layer wants to collect debug data
|
||||
*/
|
||||
struct iwl_op_mode_ops {
|
||||
struct iwl_op_mode *(*start)(struct iwl_trans *trans,
|
||||
|
@ -104,6 +106,9 @@ struct iwl_op_mode_ops {
|
|||
void (*cmd_queue_full)(struct iwl_op_mode *op_mode);
|
||||
void (*nic_config)(struct iwl_op_mode *op_mode);
|
||||
void (*wimax_active)(struct iwl_op_mode *op_mode);
|
||||
void (*time_point)(struct iwl_op_mode *op_mode,
|
||||
enum iwl_fw_ini_time_point tp_id,
|
||||
union iwl_dbg_tlv_tp_data *tp_data);
|
||||
};
|
||||
|
||||
int iwl_opmode_register(const char *name, const struct iwl_op_mode_ops *ops);
|
||||
|
@ -196,4 +201,11 @@ static inline void iwl_op_mode_wimax_active(struct iwl_op_mode *op_mode)
|
|||
op_mode->ops->wimax_active(op_mode);
|
||||
}
|
||||
|
||||
static inline void iwl_op_mode_time_point(struct iwl_op_mode *op_mode,
|
||||
enum iwl_fw_ini_time_point tp_id,
|
||||
union iwl_dbg_tlv_tp_data *tp_data)
|
||||
{
|
||||
op_mode->ops->time_point(op_mode, tp_id, tp_data);
|
||||
}
|
||||
|
||||
#endif /* __iwl_op_mode_h__ */
|
||||
|
|
|
@ -13,6 +13,7 @@
|
|||
#include "iwl-fh.h"
|
||||
#include "queue/tx.h"
|
||||
#include <linux/dmapool.h>
|
||||
#include "fw/api/commands.h"
|
||||
|
||||
struct iwl_trans *iwl_trans_alloc(unsigned int priv_size,
|
||||
struct device *dev,
|
||||
|
@ -161,8 +162,10 @@ int iwl_trans_send_cmd(struct iwl_trans *trans, struct iwl_host_cmd *cmd)
|
|||
if (!(cmd->flags & CMD_ASYNC))
|
||||
lock_map_acquire_read(&trans->sync_cmd_lockdep_map);
|
||||
|
||||
if (trans->wide_cmd_header && !iwl_cmd_groupid(cmd->id))
|
||||
cmd->id = DEF_ID(cmd->id);
|
||||
if (trans->wide_cmd_header && !iwl_cmd_groupid(cmd->id)) {
|
||||
if (cmd->id != REPLY_ERROR)
|
||||
cmd->id = DEF_ID(cmd->id);
|
||||
}
|
||||
|
||||
ret = iwl_trans_txq_send_hcmd(trans, cmd);
|
||||
|
||||
|
|
|
@ -579,9 +579,8 @@ struct iwl_trans_ops {
|
|||
const struct iwl_trans_config *trans_cfg);
|
||||
void (*set_pmi)(struct iwl_trans *trans, bool state);
|
||||
void (*sw_reset)(struct iwl_trans *trans);
|
||||
bool (*grab_nic_access)(struct iwl_trans *trans, unsigned long *flags);
|
||||
void (*release_nic_access)(struct iwl_trans *trans,
|
||||
unsigned long *flags);
|
||||
bool (*grab_nic_access)(struct iwl_trans *trans);
|
||||
void (*release_nic_access)(struct iwl_trans *trans);
|
||||
void (*set_bits_mask)(struct iwl_trans *trans, u32 reg, u32 mask,
|
||||
u32 value);
|
||||
|
||||
|
@ -746,6 +745,7 @@ struct iwl_trans_debug {
|
|||
bool hw_error;
|
||||
enum iwl_fw_ini_buffer_location ini_dest;
|
||||
|
||||
u64 unsupported_region_msk;
|
||||
struct iwl_ucode_tlv *active_regions[IWL_FW_INI_MAX_REGION_ID];
|
||||
struct list_head debug_info_tlv_list;
|
||||
struct iwl_dbg_tlv_time_point_data
|
||||
|
@ -1367,14 +1367,14 @@ iwl_trans_set_bits_mask(struct iwl_trans *trans, u32 reg, u32 mask, u32 value)
|
|||
trans->ops->set_bits_mask(trans, reg, mask, value);
|
||||
}
|
||||
|
||||
#define iwl_trans_grab_nic_access(trans, flags) \
|
||||
#define iwl_trans_grab_nic_access(trans) \
|
||||
__cond_lock(nic_access, \
|
||||
likely((trans)->ops->grab_nic_access(trans, flags)))
|
||||
likely((trans)->ops->grab_nic_access(trans)))
|
||||
|
||||
static inline void __releases(nic_access)
|
||||
iwl_trans_release_nic_access(struct iwl_trans *trans, unsigned long *flags)
|
||||
iwl_trans_release_nic_access(struct iwl_trans *trans)
|
||||
{
|
||||
trans->ops->release_nic_access(trans, flags);
|
||||
trans->ops->release_nic_access(trans);
|
||||
__release(nic_access);
|
||||
}
|
||||
|
||||
|
|
|
@ -6,6 +6,7 @@ iwlmvm-y += scan.o time-event.o rs.o rs-fw.o
|
|||
iwlmvm-y += power.o coex.o
|
||||
iwlmvm-y += tt.o offloading.o tdls.o
|
||||
iwlmvm-y += ftm-responder.o ftm-initiator.o
|
||||
iwlmvm-y += rfi.o
|
||||
iwlmvm-$(CONFIG_IWLWIFI_DEBUGFS) += debugfs.o debugfs-vif.o
|
||||
iwlmvm-$(CONFIG_IWLWIFI_LEDS) += led.o
|
||||
iwlmvm-$(CONFIG_PM) += d3.o
|
||||
|
|
|
@ -2043,6 +2043,7 @@ static int __iwl_mvm_resume(struct iwl_mvm *mvm, bool test)
|
|||
iwl_fw_dbg_collect_desc(&mvm->fwrt, &iwl_dump_desc_assert,
|
||||
false, 0);
|
||||
ret = 1;
|
||||
mvm->trans->system_pm_mode = IWL_PLAT_PM_MODE_DISABLED;
|
||||
goto err;
|
||||
}
|
||||
|
||||
|
@ -2164,17 +2165,12 @@ out:
|
|||
return 1;
|
||||
}
|
||||
|
||||
static int iwl_mvm_resume_d3(struct iwl_mvm *mvm)
|
||||
{
|
||||
return __iwl_mvm_resume(mvm, false);
|
||||
}
|
||||
|
||||
int iwl_mvm_resume(struct ieee80211_hw *hw)
|
||||
{
|
||||
struct iwl_mvm *mvm = IWL_MAC80211_GET_MVM(hw);
|
||||
int ret;
|
||||
|
||||
ret = iwl_mvm_resume_d3(mvm);
|
||||
ret = __iwl_mvm_resume(mvm, false);
|
||||
|
||||
iwl_mvm_resume_tcm(mvm);
|
||||
|
||||
|
|
|
@ -1776,6 +1776,69 @@ iwl_dbgfs_ltr_config_write(struct iwl_mvm *mvm,
|
|||
return ret ?: count;
|
||||
}
|
||||
|
||||
static ssize_t iwl_dbgfs_rfi_freq_table_write(struct iwl_mvm *mvm, char *buf,
|
||||
size_t count, loff_t *ppos)
|
||||
{
|
||||
int ret = 0;
|
||||
u16 op_id;
|
||||
|
||||
if (kstrtou16(buf, 10, &op_id))
|
||||
return -EINVAL;
|
||||
|
||||
/* value zero triggers re-sending the default table to the device */
|
||||
if (!op_id)
|
||||
ret = iwl_rfi_send_config_cmd(mvm, NULL);
|
||||
else
|
||||
ret = -EOPNOTSUPP; /* in the future a new table will be added */
|
||||
|
||||
return ret ?: count;
|
||||
}
|
||||
|
||||
/* The size computation is as follows:
|
||||
* each number needs at most 3 characters, number of rows is the size of
|
||||
* the table; So, need 5 chars for the "freq: " part and each tuple afterwards
|
||||
* needs 6 characters for numbers and 5 for the punctuation around.
|
||||
*/
|
||||
#define IWL_RFI_BUF_SIZE (IWL_RFI_LUT_INSTALLED_SIZE *\
|
||||
(5 + IWL_RFI_LUT_ENTRY_CHANNELS_NUM * (6 + 5)))
|
||||
|
||||
static ssize_t iwl_dbgfs_rfi_freq_table_read(struct file *file,
|
||||
char __user *user_buf,
|
||||
size_t count, loff_t *ppos)
|
||||
{
|
||||
struct iwl_mvm *mvm = file->private_data;
|
||||
struct iwl_rfi_freq_table_resp_cmd *resp;
|
||||
u32 status;
|
||||
char buf[IWL_RFI_BUF_SIZE];
|
||||
int i, j, pos = 0;
|
||||
|
||||
resp = iwl_rfi_get_freq_table(mvm);
|
||||
if (IS_ERR(resp))
|
||||
return PTR_ERR(resp);
|
||||
|
||||
status = le32_to_cpu(resp->status);
|
||||
if (status != RFI_FREQ_TABLE_OK) {
|
||||
scnprintf(buf, IWL_RFI_BUF_SIZE, "status = %d\n", status);
|
||||
goto out;
|
||||
}
|
||||
|
||||
for (i = 0; i < ARRAY_SIZE(resp->table); i++) {
|
||||
pos += scnprintf(buf + pos, IWL_RFI_BUF_SIZE - pos, "%d: ",
|
||||
resp->table[i].freq);
|
||||
|
||||
for (j = 0; j < ARRAY_SIZE(resp->table[i].channels); j++)
|
||||
pos += scnprintf(buf + pos, IWL_RFI_BUF_SIZE - pos,
|
||||
"(%d, %d) ",
|
||||
resp->table[i].channels[j],
|
||||
resp->table[i].bands[j]);
|
||||
pos += scnprintf(buf + pos, IWL_RFI_BUF_SIZE - pos, "\n");
|
||||
}
|
||||
|
||||
out:
|
||||
kfree(resp);
|
||||
return simple_read_from_buffer(user_buf, count, ppos, buf, pos);
|
||||
}
|
||||
|
||||
MVM_DEBUGFS_READ_WRITE_FILE_OPS(prph_reg, 64);
|
||||
|
||||
/* Device wide debugfs entries */
|
||||
|
@ -1827,6 +1890,7 @@ MVM_DEBUGFS_READ_WRITE_STA_FILE_OPS(amsdu_len, 16);
|
|||
MVM_DEBUGFS_READ_WRITE_FILE_OPS(he_sniffer_params, 32);
|
||||
|
||||
MVM_DEBUGFS_WRITE_FILE_OPS(ltr_config, 512);
|
||||
MVM_DEBUGFS_READ_WRITE_FILE_OPS(rfi_freq_table, 16);
|
||||
|
||||
static ssize_t iwl_dbgfs_mem_read(struct file *file, char __user *user_buf,
|
||||
size_t count, loff_t *ppos)
|
||||
|
@ -1973,26 +2037,24 @@ void iwl_mvm_sta_add_debugfs(struct ieee80211_hw *hw,
|
|||
MVM_DEBUGFS_ADD_STA_FILE(amsdu_len, dir, 0600);
|
||||
}
|
||||
|
||||
void iwl_mvm_dbgfs_register(struct iwl_mvm *mvm, struct dentry *dbgfs_dir)
|
||||
void iwl_mvm_dbgfs_register(struct iwl_mvm *mvm)
|
||||
{
|
||||
struct dentry *bcast_dir __maybe_unused;
|
||||
char buf[100];
|
||||
|
||||
spin_lock_init(&mvm->drv_stats_lock);
|
||||
|
||||
mvm->debugfs_dir = dbgfs_dir;
|
||||
|
||||
MVM_DEBUGFS_ADD_FILE(tx_flush, mvm->debugfs_dir, 0200);
|
||||
MVM_DEBUGFS_ADD_FILE(sta_drain, mvm->debugfs_dir, 0200);
|
||||
MVM_DEBUGFS_ADD_FILE(sram, mvm->debugfs_dir, 0600);
|
||||
MVM_DEBUGFS_ADD_FILE(set_nic_temperature, mvm->debugfs_dir, 0600);
|
||||
MVM_DEBUGFS_ADD_FILE(nic_temp, dbgfs_dir, 0400);
|
||||
MVM_DEBUGFS_ADD_FILE(ctdp_budget, dbgfs_dir, 0400);
|
||||
MVM_DEBUGFS_ADD_FILE(stop_ctdp, dbgfs_dir, 0200);
|
||||
MVM_DEBUGFS_ADD_FILE(force_ctkill, dbgfs_dir, 0200);
|
||||
MVM_DEBUGFS_ADD_FILE(stations, dbgfs_dir, 0400);
|
||||
MVM_DEBUGFS_ADD_FILE(bt_notif, dbgfs_dir, 0400);
|
||||
MVM_DEBUGFS_ADD_FILE(bt_cmd, dbgfs_dir, 0400);
|
||||
MVM_DEBUGFS_ADD_FILE(nic_temp, mvm->debugfs_dir, 0400);
|
||||
MVM_DEBUGFS_ADD_FILE(ctdp_budget, mvm->debugfs_dir, 0400);
|
||||
MVM_DEBUGFS_ADD_FILE(stop_ctdp, mvm->debugfs_dir, 0200);
|
||||
MVM_DEBUGFS_ADD_FILE(force_ctkill, mvm->debugfs_dir, 0200);
|
||||
MVM_DEBUGFS_ADD_FILE(stations, mvm->debugfs_dir, 0400);
|
||||
MVM_DEBUGFS_ADD_FILE(bt_notif, mvm->debugfs_dir, 0400);
|
||||
MVM_DEBUGFS_ADD_FILE(bt_cmd, mvm->debugfs_dir, 0400);
|
||||
MVM_DEBUGFS_ADD_FILE(disable_power_off, mvm->debugfs_dir, 0600);
|
||||
MVM_DEBUGFS_ADD_FILE(fw_ver, mvm->debugfs_dir, 0400);
|
||||
MVM_DEBUGFS_ADD_FILE(fw_rx_stats, mvm->debugfs_dir, 0400);
|
||||
|
@ -2010,11 +2072,12 @@ void iwl_mvm_dbgfs_register(struct iwl_mvm *mvm, struct dentry *dbgfs_dir)
|
|||
MVM_DEBUGFS_ADD_FILE(inject_packet, mvm->debugfs_dir, 0200);
|
||||
MVM_DEBUGFS_ADD_FILE(inject_beacon_ie, mvm->debugfs_dir, 0200);
|
||||
MVM_DEBUGFS_ADD_FILE(inject_beacon_ie_restore, mvm->debugfs_dir, 0200);
|
||||
MVM_DEBUGFS_ADD_FILE(rfi_freq_table, mvm->debugfs_dir, 0600);
|
||||
|
||||
if (mvm->fw->phy_integration_ver)
|
||||
MVM_DEBUGFS_ADD_FILE(phy_integration_ver, mvm->debugfs_dir, 0400);
|
||||
#ifdef CONFIG_ACPI
|
||||
MVM_DEBUGFS_ADD_FILE(sar_geo_profile, dbgfs_dir, 0400);
|
||||
MVM_DEBUGFS_ADD_FILE(sar_geo_profile, mvm->debugfs_dir, 0400);
|
||||
#endif
|
||||
MVM_DEBUGFS_ADD_FILE(he_sniffer_params, mvm->debugfs_dir, 0600);
|
||||
|
||||
|
@ -2066,12 +2129,13 @@ void iwl_mvm_dbgfs_register(struct iwl_mvm *mvm, struct dentry *dbgfs_dir)
|
|||
debugfs_create_blob("nvm_reg", S_IRUSR,
|
||||
mvm->debugfs_dir, &mvm->nvm_reg_blob);
|
||||
|
||||
debugfs_create_file("mem", 0600, dbgfs_dir, mvm, &iwl_dbgfs_mem_ops);
|
||||
debugfs_create_file("mem", 0600, mvm->debugfs_dir, mvm,
|
||||
&iwl_dbgfs_mem_ops);
|
||||
|
||||
/*
|
||||
* Create a symlink with mac80211. It will be removed when mac80211
|
||||
* exists (before the opmode exists which removes the target.)
|
||||
*/
|
||||
snprintf(buf, 100, "../../%pd2", dbgfs_dir->d_parent);
|
||||
snprintf(buf, 100, "../../%pd2", mvm->debugfs_dir->d_parent);
|
||||
debugfs_create_symlink("iwlwifi", mvm->hw->wiphy->debugfsdir, buf);
|
||||
}
|
||||
|
|
|
@ -1,6 +1,6 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */
|
||||
/*
|
||||
* Copyright (C) 2012-2014, 2018 Intel Corporation
|
||||
* Copyright (C) 2012-2014, 2018, 2020 Intel Corporation
|
||||
* Copyright (C) 2013-2015 Intel Mobile Communications GmbH
|
||||
* Copyright (C) 2016-2017 Intel Deutschland GmbH
|
||||
*/
|
||||
|
@ -36,5 +36,6 @@
|
|||
#include "fw/api/stats.h"
|
||||
#include "fw/api/location.h"
|
||||
#include "fw/api/tx.h"
|
||||
#include "fw/api/rfi.h"
|
||||
|
||||
#endif /* __fw_api_h__ */
|
||||
|
|
|
@ -476,9 +476,13 @@ static int iwl_run_unified_mvm_ucode(struct iwl_mvm *mvm)
|
|||
|
||||
/* Load NVM to NIC if needed */
|
||||
if (mvm->nvm_file_name) {
|
||||
iwl_read_external_nvm(mvm->trans, mvm->nvm_file_name,
|
||||
mvm->nvm_sections);
|
||||
iwl_mvm_load_nvm_to_nic(mvm);
|
||||
ret = iwl_read_external_nvm(mvm->trans, mvm->nvm_file_name,
|
||||
mvm->nvm_sections);
|
||||
if (ret)
|
||||
goto error;
|
||||
ret = iwl_mvm_load_nvm_to_nic(mvm);
|
||||
if (ret)
|
||||
goto error;
|
||||
}
|
||||
|
||||
if (IWL_MVM_PARSE_NVM && !mvm->nvm_data) {
|
||||
|
@ -659,8 +663,11 @@ int iwl_run_init_mvm_ucode(struct iwl_mvm *mvm)
|
|||
}
|
||||
|
||||
/* In case we read the NVM from external file, load it to the NIC */
|
||||
if (mvm->nvm_file_name)
|
||||
iwl_mvm_load_nvm_to_nic(mvm);
|
||||
if (mvm->nvm_file_name) {
|
||||
ret = iwl_mvm_load_nvm_to_nic(mvm);
|
||||
if (ret)
|
||||
goto remove_notif;
|
||||
}
|
||||
|
||||
WARN_ONCE(mvm->nvm_data->nvm_version < mvm->trans->cfg->nvm_ver,
|
||||
"Too old NVM version (0x%0x, required = 0x%0x)",
|
||||
|
@ -862,12 +869,10 @@ static int iwl_mvm_sar_geo_init(struct iwl_mvm *mvm)
|
|||
if (cmd_ver == 3) {
|
||||
len = sizeof(cmd.v3);
|
||||
n_bands = ARRAY_SIZE(cmd.v3.table[0]);
|
||||
cmd.v3.table_revision = cpu_to_le32(mvm->fwrt.geo_rev);
|
||||
} else if (fw_has_api(&mvm->fwrt.fw->ucode_capa,
|
||||
IWL_UCODE_TLV_API_SAR_TABLE_VER)) {
|
||||
len = sizeof(cmd.v2);
|
||||
n_bands = ARRAY_SIZE(cmd.v2.table[0]);
|
||||
cmd.v2.table_revision = cpu_to_le32(mvm->fwrt.geo_rev);
|
||||
} else {
|
||||
len = sizeof(cmd.v1);
|
||||
n_bands = ARRAY_SIZE(cmd.v1.table[0]);
|
||||
|
@ -887,6 +892,16 @@ static int iwl_mvm_sar_geo_init(struct iwl_mvm *mvm)
|
|||
if (ret)
|
||||
return 0;
|
||||
|
||||
/*
|
||||
* Set the revision on versions that contain it.
|
||||
* This must be done after calling iwl_sar_geo_init().
|
||||
*/
|
||||
if (cmd_ver == 3)
|
||||
cmd.v3.table_revision = cpu_to_le32(mvm->fwrt.geo_rev);
|
||||
else if (fw_has_api(&mvm->fwrt.fw->ucode_capa,
|
||||
IWL_UCODE_TLV_API_SAR_TABLE_VER))
|
||||
cmd.v2.table_revision = cpu_to_le32(mvm->fwrt.geo_rev);
|
||||
|
||||
return iwl_mvm_send_cmd_pdu(mvm,
|
||||
WIDE_ID(PHY_OPS_GROUP, GEO_TX_POWER_LIMIT),
|
||||
0, len, &cmd);
|
||||
|
@ -895,7 +910,6 @@ static int iwl_mvm_sar_geo_init(struct iwl_mvm *mvm)
|
|||
static int iwl_mvm_get_ppag_table(struct iwl_mvm *mvm)
|
||||
{
|
||||
union acpi_object *wifi_pkg, *data, *enabled;
|
||||
union iwl_ppag_table_cmd ppag_table;
|
||||
int i, j, ret, tbl_rev, num_sub_bands;
|
||||
int idx = 2;
|
||||
s8 *gain;
|
||||
|
@ -949,8 +963,8 @@ read_table:
|
|||
goto out_free;
|
||||
}
|
||||
|
||||
ppag_table.v1.enabled = cpu_to_le32(enabled->integer.value);
|
||||
if (!ppag_table.v1.enabled) {
|
||||
mvm->fwrt.ppag_table.v1.enabled = cpu_to_le32(enabled->integer.value);
|
||||
if (!mvm->fwrt.ppag_table.v1.enabled) {
|
||||
ret = 0;
|
||||
goto out_free;
|
||||
}
|
||||
|
@ -965,16 +979,23 @@ read_table:
|
|||
union acpi_object *ent;
|
||||
|
||||
ent = &wifi_pkg->package.elements[idx++];
|
||||
if (ent->type != ACPI_TYPE_INTEGER ||
|
||||
(j == 0 && ent->integer.value > ACPI_PPAG_MAX_LB) ||
|
||||
(j == 0 && ent->integer.value < ACPI_PPAG_MIN_LB) ||
|
||||
(j != 0 && ent->integer.value > ACPI_PPAG_MAX_HB) ||
|
||||
(j != 0 && ent->integer.value < ACPI_PPAG_MIN_HB)) {
|
||||
ppag_table.v1.enabled = cpu_to_le32(0);
|
||||
if (ent->type != ACPI_TYPE_INTEGER) {
|
||||
ret = -EINVAL;
|
||||
goto out_free;
|
||||
}
|
||||
|
||||
gain[i * num_sub_bands + j] = ent->integer.value;
|
||||
|
||||
if ((j == 0 &&
|
||||
(gain[i * num_sub_bands + j] > ACPI_PPAG_MAX_LB ||
|
||||
gain[i * num_sub_bands + j] < ACPI_PPAG_MIN_LB)) ||
|
||||
(j != 0 &&
|
||||
(gain[i * num_sub_bands + j] > ACPI_PPAG_MAX_HB ||
|
||||
gain[i * num_sub_bands + j] < ACPI_PPAG_MIN_HB))) {
|
||||
mvm->fwrt.ppag_table.v1.enabled = cpu_to_le32(0);
|
||||
ret = -EINVAL;
|
||||
goto out_free;
|
||||
}
|
||||
}
|
||||
}
|
||||
ret = 0;
|
||||
|
@ -987,7 +1008,6 @@ int iwl_mvm_ppag_send_cmd(struct iwl_mvm *mvm)
|
|||
{
|
||||
u8 cmd_ver;
|
||||
int i, j, ret, num_sub_bands, cmd_size;
|
||||
union iwl_ppag_table_cmd ppag_table;
|
||||
s8 *gain;
|
||||
|
||||
if (!fw_has_capa(&mvm->fw->ucode_capa, IWL_UCODE_TLV_CAPA_SET_PPAG)) {
|
||||
|
@ -1000,15 +1020,13 @@ int iwl_mvm_ppag_send_cmd(struct iwl_mvm *mvm)
|
|||
return 0;
|
||||
}
|
||||
|
||||
ppag_table.v1.enabled = mvm->fwrt.ppag_table.v1.enabled;
|
||||
|
||||
cmd_ver = iwl_fw_lookup_cmd_ver(mvm->fw, PHY_OPS_GROUP,
|
||||
PER_PLATFORM_ANT_GAIN_CMD,
|
||||
IWL_FW_CMD_VER_UNKNOWN);
|
||||
if (cmd_ver == 1) {
|
||||
num_sub_bands = IWL_NUM_SUB_BANDS;
|
||||
gain = mvm->fwrt.ppag_table.v1.gain[0];
|
||||
cmd_size = sizeof(ppag_table.v1);
|
||||
cmd_size = sizeof(mvm->fwrt.ppag_table.v1);
|
||||
if (mvm->fwrt.ppag_ver == 2) {
|
||||
IWL_DEBUG_RADIO(mvm,
|
||||
"PPAG table is v2 but FW supports v1, sending truncated table\n");
|
||||
|
@ -1016,7 +1034,7 @@ int iwl_mvm_ppag_send_cmd(struct iwl_mvm *mvm)
|
|||
} else if (cmd_ver == 2) {
|
||||
num_sub_bands = IWL_NUM_SUB_BANDS_V2;
|
||||
gain = mvm->fwrt.ppag_table.v2.gain[0];
|
||||
cmd_size = sizeof(ppag_table.v2);
|
||||
cmd_size = sizeof(mvm->fwrt.ppag_table.v2);
|
||||
if (mvm->fwrt.ppag_ver == 1) {
|
||||
IWL_DEBUG_RADIO(mvm,
|
||||
"PPAG table is v1 but FW supports v2, sending padded table\n");
|
||||
|
@ -1036,7 +1054,7 @@ int iwl_mvm_ppag_send_cmd(struct iwl_mvm *mvm)
|
|||
IWL_DEBUG_RADIO(mvm, "Sending PER_PLATFORM_ANT_GAIN_CMD\n");
|
||||
ret = iwl_mvm_send_cmd_pdu(mvm, WIDE_ID(PHY_OPS_GROUP,
|
||||
PER_PLATFORM_ANT_GAIN_CMD),
|
||||
0, cmd_size, &ppag_table);
|
||||
0, cmd_size, &mvm->fwrt.ppag_table);
|
||||
if (ret < 0)
|
||||
IWL_ERR(mvm, "failed to send PER_PLATFORM_ANT_GAIN_CMD (%d)\n",
|
||||
ret);
|
||||
|
@ -1130,7 +1148,8 @@ static u8 iwl_mvm_eval_dsm_indonesia_5g2(struct iwl_mvm *mvm)
|
|||
u8 value;
|
||||
|
||||
int ret = iwl_acpi_get_dsm_u8((&mvm->fwrt)->dev, 0,
|
||||
DSM_FUNC_ENABLE_INDONESIA_5G2, &value);
|
||||
DSM_FUNC_ENABLE_INDONESIA_5G2,
|
||||
&iwl_guid, &value);
|
||||
|
||||
if (ret < 0)
|
||||
IWL_DEBUG_RADIO(mvm,
|
||||
|
@ -1151,11 +1170,36 @@ static u8 iwl_mvm_eval_dsm_indonesia_5g2(struct iwl_mvm *mvm)
|
|||
return DSM_VALUE_INDONESIA_DISABLE;
|
||||
}
|
||||
|
||||
static u8 iwl_mvm_eval_dsm_rfi(struct iwl_mvm *mvm)
|
||||
{
|
||||
u8 value;
|
||||
int ret = iwl_acpi_get_dsm_u8((&mvm->fwrt)->dev, 0, DSM_RFI_FUNC_ENABLE,
|
||||
&iwl_rfi_guid, &value);
|
||||
|
||||
if (ret < 0) {
|
||||
IWL_DEBUG_RADIO(mvm, "Failed to get DSM RFI, ret=%d\n", ret);
|
||||
|
||||
} else if (value >= DSM_VALUE_RFI_MAX) {
|
||||
IWL_DEBUG_RADIO(mvm, "DSM RFI got invalid value, ret=%d\n",
|
||||
value);
|
||||
|
||||
} else if (value == DSM_VALUE_RFI_ENABLE) {
|
||||
IWL_DEBUG_RADIO(mvm, "DSM RFI is evaluated to enable\n");
|
||||
return DSM_VALUE_RFI_ENABLE;
|
||||
}
|
||||
|
||||
IWL_DEBUG_RADIO(mvm, "DSM RFI is disabled\n");
|
||||
|
||||
/* default behaviour is disabled */
|
||||
return DSM_VALUE_RFI_DISABLE;
|
||||
}
|
||||
|
||||
static u8 iwl_mvm_eval_dsm_disable_srd(struct iwl_mvm *mvm)
|
||||
{
|
||||
u8 value;
|
||||
int ret = iwl_acpi_get_dsm_u8((&mvm->fwrt)->dev, 0,
|
||||
DSM_FUNC_DISABLE_SRD, &value);
|
||||
DSM_FUNC_DISABLE_SRD,
|
||||
&iwl_guid, &value);
|
||||
|
||||
if (ret < 0)
|
||||
IWL_DEBUG_RADIO(mvm,
|
||||
|
@ -1185,7 +1229,7 @@ static void iwl_mvm_lari_cfg(struct iwl_mvm *mvm)
|
|||
{
|
||||
u8 ret;
|
||||
int cmd_ret;
|
||||
struct iwl_lari_config_change_cmd cmd = {};
|
||||
struct iwl_lari_config_change_cmd_v2 cmd = {};
|
||||
|
||||
if (iwl_mvm_eval_dsm_indonesia_5g2(mvm) == DSM_VALUE_INDONESIA_ENABLE)
|
||||
cmd.config_bitmap |=
|
||||
|
@ -1203,11 +1247,18 @@ static void iwl_mvm_lari_cfg(struct iwl_mvm *mvm)
|
|||
/* apply more config masks here */
|
||||
|
||||
if (cmd.config_bitmap) {
|
||||
IWL_DEBUG_RADIO(mvm, "sending LARI_CONFIG_CHANGE\n");
|
||||
size_t cmd_size = iwl_fw_lookup_cmd_ver(mvm->fw,
|
||||
REGULATORY_AND_NVM_GROUP,
|
||||
LARI_CONFIG_CHANGE, 1) == 2 ?
|
||||
sizeof(struct iwl_lari_config_change_cmd_v2) :
|
||||
sizeof(struct iwl_lari_config_change_cmd_v1);
|
||||
IWL_DEBUG_RADIO(mvm,
|
||||
"sending LARI_CONFIG_CHANGE, config_bitmap=0x%x\n",
|
||||
le32_to_cpu(cmd.config_bitmap));
|
||||
cmd_ret = iwl_mvm_send_cmd_pdu(mvm,
|
||||
WIDE_ID(REGULATORY_AND_NVM_GROUP,
|
||||
LARI_CONFIG_CHANGE),
|
||||
0, sizeof(cmd), &cmd);
|
||||
0, cmd_size, &cmd);
|
||||
if (cmd_ret < 0)
|
||||
IWL_DEBUG_RADIO(mvm,
|
||||
"Failed to send LARI_CONFIG_CHANGE (%d)\n",
|
||||
|
@ -1249,6 +1300,11 @@ static void iwl_mvm_tas_init(struct iwl_mvm *mvm)
|
|||
static void iwl_mvm_lari_cfg(struct iwl_mvm *mvm)
|
||||
{
|
||||
}
|
||||
|
||||
static u8 iwl_mvm_eval_dsm_rfi(struct iwl_mvm *mvm)
|
||||
{
|
||||
return DSM_VALUE_RFI_DISABLE;
|
||||
}
|
||||
#endif /* CONFIG_ACPI */
|
||||
|
||||
void iwl_mvm_send_recovery_cmd(struct iwl_mvm *mvm, u32 flags)
|
||||
|
@ -1585,6 +1641,12 @@ int iwl_mvm_up(struct iwl_mvm *mvm)
|
|||
|
||||
iwl_mvm_ftm_initiator_smooth_config(mvm);
|
||||
|
||||
if (fw_has_capa(&mvm->fw->ucode_capa,
|
||||
IWL_UCODE_TLV_CAPA_RFIM_SUPPORT)) {
|
||||
if (iwl_mvm_eval_dsm_rfi(mvm) == DSM_VALUE_RFI_ENABLE)
|
||||
iwl_rfi_send_config_cmd(mvm, NULL);
|
||||
}
|
||||
|
||||
IWL_DEBUG_INFO(mvm, "RT uCode started.\n");
|
||||
return 0;
|
||||
error:
|
||||
|
|
|
@ -2007,9 +2007,21 @@ static void iwl_mvm_cfg_he_sta(struct iwl_mvm *mvm,
|
|||
struct ieee80211_sta *sta;
|
||||
u32 flags;
|
||||
int i;
|
||||
const struct ieee80211_sta_he_cap *own_he_cap = NULL;
|
||||
struct ieee80211_chanctx_conf *chanctx_conf;
|
||||
const struct ieee80211_supported_band *sband;
|
||||
|
||||
rcu_read_lock();
|
||||
|
||||
chanctx_conf = rcu_dereference(vif->chanctx_conf);
|
||||
if (WARN_ON(!chanctx_conf)) {
|
||||
rcu_read_unlock();
|
||||
return;
|
||||
}
|
||||
|
||||
sband = mvm->hw->wiphy->bands[chanctx_conf->def.chan->band];
|
||||
own_he_cap = ieee80211_get_he_iftype_cap(sband, vif->type);
|
||||
|
||||
sta = rcu_dereference(mvm->fw_id_to_mac_id[sta_ctxt_cmd.sta_id]);
|
||||
if (IS_ERR_OR_NULL(sta)) {
|
||||
rcu_read_unlock();
|
||||
|
@ -2196,6 +2208,10 @@ static void iwl_mvm_cfg_he_sta(struct iwl_mvm *mvm,
|
|||
(vif->bss_conf.uora_ocw_range >> 3) & 0x7;
|
||||
}
|
||||
|
||||
if (own_he_cap && !(own_he_cap->he_cap_elem.mac_cap_info[2] &
|
||||
IEEE80211_HE_MAC_CAP2_ACK_EN))
|
||||
flags |= STA_CTXT_HE_NIC_NOT_ACK_ENABLED;
|
||||
|
||||
if (vif->bss_conf.nontransmitted) {
|
||||
flags |= STA_CTXT_HE_REF_BSSID_VALID;
|
||||
ether_addr_copy(sta_ctxt_cmd.ref_bssid_addr,
|
||||
|
@ -4674,7 +4690,8 @@ static void iwl_mvm_channel_switch_rx_beacon(struct ieee80211_hw *hw,
|
|||
if (mvmvif->csa_failed)
|
||||
goto out_unlock;
|
||||
|
||||
IWL_DEBUG_MAC80211(mvm, "Modify CSA on mac %d\n", mvmvif->id);
|
||||
IWL_DEBUG_MAC80211(mvm, "Modify CSA on mac %d count = %d mode = %d\n",
|
||||
mvmvif->id, chsw->count, chsw->block_tx);
|
||||
WARN_ON(iwl_mvm_send_cmd_pdu(mvm,
|
||||
WIDE_ID(MAC_CONF_GROUP,
|
||||
CHANNEL_SWITCH_TIME_EVENT_CMD),
|
||||
|
|
|
@ -893,8 +893,12 @@ struct iwl_mvm {
|
|||
/* last smart fifo state that was successfully sent to firmware */
|
||||
enum iwl_sf_state sf_state;
|
||||
|
||||
#ifdef CONFIG_IWLWIFI_DEBUGFS
|
||||
/*
|
||||
* Leave this pointer outside the ifdef below so that it can be
|
||||
* assigned without ifdef in the source code.
|
||||
*/
|
||||
struct dentry *debugfs_dir;
|
||||
#ifdef CONFIG_IWLWIFI_DEBUGFS
|
||||
u32 dbgfs_sram_offset, dbgfs_sram_len;
|
||||
u32 dbgfs_prph_reg_addr;
|
||||
bool disable_power_off;
|
||||
|
@ -1700,12 +1704,11 @@ void iwl_mvm_rx_umac_scan_iter_complete_notif(struct iwl_mvm *mvm,
|
|||
|
||||
/* MVM debugfs */
|
||||
#ifdef CONFIG_IWLWIFI_DEBUGFS
|
||||
void iwl_mvm_dbgfs_register(struct iwl_mvm *mvm, struct dentry *dbgfs_dir);
|
||||
void iwl_mvm_dbgfs_register(struct iwl_mvm *mvm);
|
||||
void iwl_mvm_vif_dbgfs_register(struct iwl_mvm *mvm, struct ieee80211_vif *vif);
|
||||
void iwl_mvm_vif_dbgfs_clean(struct iwl_mvm *mvm, struct ieee80211_vif *vif);
|
||||
#else
|
||||
static inline void iwl_mvm_dbgfs_register(struct iwl_mvm *mvm,
|
||||
struct dentry *dbgfs_dir)
|
||||
static inline void iwl_mvm_dbgfs_register(struct iwl_mvm *mvm)
|
||||
{
|
||||
}
|
||||
static inline void
|
||||
|
@ -2037,6 +2040,10 @@ void iwl_mvm_sta_add_debugfs(struct ieee80211_hw *hw,
|
|||
struct dentry *dir);
|
||||
#endif
|
||||
|
||||
int iwl_rfi_send_config_cmd(struct iwl_mvm *mvm,
|
||||
struct iwl_rfi_lut_entry *rfi_table);
|
||||
struct iwl_rfi_freq_table_resp_cmd *iwl_rfi_get_freq_table(struct iwl_mvm *mvm);
|
||||
|
||||
static inline u8 iwl_mvm_phy_band_from_nl80211(enum nl80211_band band)
|
||||
{
|
||||
switch (band) {
|
||||
|
|
|
@ -645,6 +645,44 @@ static const struct iwl_fw_runtime_ops iwl_mvm_fwrt_ops = {
|
|||
.d3_debug_enable = iwl_mvm_d3_debug_enable,
|
||||
};
|
||||
|
||||
static int iwl_mvm_start_get_nvm(struct iwl_mvm *mvm)
|
||||
{
|
||||
int ret;
|
||||
|
||||
mutex_lock(&mvm->mutex);
|
||||
|
||||
ret = iwl_run_init_mvm_ucode(mvm);
|
||||
|
||||
if (ret && ret != -ERFKILL)
|
||||
iwl_fw_dbg_error_collect(&mvm->fwrt, FW_DBG_TRIGGER_DRIVER);
|
||||
|
||||
if (!iwlmvm_mod_params.init_dbg || !ret)
|
||||
iwl_mvm_stop_device(mvm);
|
||||
|
||||
mutex_unlock(&mvm->mutex);
|
||||
|
||||
if (ret < 0)
|
||||
IWL_ERR(mvm, "Failed to run INIT ucode: %d\n", ret);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
static int iwl_mvm_start_post_nvm(struct iwl_mvm *mvm)
|
||||
{
|
||||
int ret;
|
||||
|
||||
iwl_mvm_toggle_tx_ant(mvm, &mvm->mgmt_last_antenna_idx);
|
||||
|
||||
ret = iwl_mvm_mac_setup_register(mvm);
|
||||
if (ret)
|
||||
return ret;
|
||||
mvm->hw_registered = true;
|
||||
|
||||
iwl_mvm_dbgfs_register(mvm);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static struct iwl_op_mode *
|
||||
iwl_op_mode_mvm_start(struct iwl_trans *trans, const struct iwl_cfg *cfg,
|
||||
const struct iwl_fw *fw, struct dentry *dbgfs_dir)
|
||||
|
@ -866,18 +904,6 @@ iwl_op_mode_mvm_start(struct iwl_trans *trans, const struct iwl_cfg *cfg,
|
|||
if (err)
|
||||
goto out_free;
|
||||
|
||||
mutex_lock(&mvm->mutex);
|
||||
err = iwl_run_init_mvm_ucode(mvm);
|
||||
if (err && err != -ERFKILL)
|
||||
iwl_fw_dbg_error_collect(&mvm->fwrt, FW_DBG_TRIGGER_DRIVER);
|
||||
if (!iwlmvm_mod_params.init_dbg || !err)
|
||||
iwl_mvm_stop_device(mvm);
|
||||
mutex_unlock(&mvm->mutex);
|
||||
if (err < 0) {
|
||||
IWL_ERR(mvm, "Failed to run INIT ucode: %d\n", err);
|
||||
goto out_free;
|
||||
}
|
||||
|
||||
scan_size = iwl_mvm_scan_size(mvm);
|
||||
|
||||
mvm->scan_cmd = kmalloc(scan_size, GFP_KERNEL);
|
||||
|
@ -891,26 +917,27 @@ iwl_op_mode_mvm_start(struct iwl_trans *trans, const struct iwl_cfg *cfg,
|
|||
/* Set EBS as successful as long as not stated otherwise by the FW. */
|
||||
mvm->last_ebs_successful = true;
|
||||
|
||||
err = iwl_mvm_mac_setup_register(mvm);
|
||||
if (err)
|
||||
goto out_free;
|
||||
mvm->hw_registered = true;
|
||||
|
||||
min_backoff = iwl_mvm_min_backoff(mvm);
|
||||
iwl_mvm_thermal_initialize(mvm, min_backoff);
|
||||
|
||||
iwl_mvm_dbgfs_register(mvm, dbgfs_dir);
|
||||
|
||||
if (!iwl_mvm_has_new_rx_stats_api(mvm))
|
||||
memset(&mvm->rx_stats_v3, 0,
|
||||
sizeof(struct mvm_statistics_rx_v3));
|
||||
else
|
||||
memset(&mvm->rx_stats, 0, sizeof(struct mvm_statistics_rx));
|
||||
|
||||
iwl_mvm_toggle_tx_ant(mvm, &mvm->mgmt_last_antenna_idx);
|
||||
mvm->debugfs_dir = dbgfs_dir;
|
||||
|
||||
if (iwl_mvm_start_get_nvm(mvm))
|
||||
goto out_thermal_exit;
|
||||
|
||||
if (iwl_mvm_start_post_nvm(mvm))
|
||||
goto out_thermal_exit;
|
||||
|
||||
return op_mode;
|
||||
|
||||
out_thermal_exit:
|
||||
iwl_mvm_thermal_exit(mvm);
|
||||
out_free:
|
||||
iwl_fw_flush_dumps(&mvm->fwrt);
|
||||
iwl_fw_runtime_free(&mvm->fwrt);
|
||||
|
@ -1412,6 +1439,15 @@ static void iwl_mvm_cmd_queue_full(struct iwl_op_mode *op_mode)
|
|||
iwl_mvm_nic_restart(mvm, true);
|
||||
}
|
||||
|
||||
static void iwl_op_mode_mvm_time_point(struct iwl_op_mode *op_mode,
|
||||
enum iwl_fw_ini_time_point tp_id,
|
||||
union iwl_dbg_tlv_tp_data *tp_data)
|
||||
{
|
||||
struct iwl_mvm *mvm = IWL_OP_MODE_GET_MVM(op_mode);
|
||||
|
||||
iwl_dbg_tlv_time_point(&mvm->fwrt, tp_id, tp_data);
|
||||
}
|
||||
|
||||
#define IWL_MVM_COMMON_OPS \
|
||||
/* these could be differentiated */ \
|
||||
.async_cb = iwl_mvm_async_cb, \
|
||||
|
@ -1424,7 +1460,8 @@ static void iwl_mvm_cmd_queue_full(struct iwl_op_mode *op_mode)
|
|||
.nic_config = iwl_mvm_nic_config, \
|
||||
/* as we only register one, these MUST be common! */ \
|
||||
.start = iwl_op_mode_mvm_start, \
|
||||
.stop = iwl_op_mode_mvm_stop
|
||||
.stop = iwl_op_mode_mvm_stop, \
|
||||
.time_point = iwl_op_mode_mvm_time_point
|
||||
|
||||
static const struct iwl_op_mode_ops iwl_mvm_ops = {
|
||||
IWL_MVM_COMMON_OPS,
|
||||
|
|
|
@ -0,0 +1,118 @@
|
|||
// SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
|
||||
/*
|
||||
* Copyright (C) 2020 Intel Corporation
|
||||
*/
|
||||
|
||||
#include "mvm.h"
|
||||
#include "fw/api/commands.h"
|
||||
#include "fw/api/phy-ctxt.h"
|
||||
|
||||
/**
|
||||
* DDR needs frequency in units of 16.666MHz, so provide FW with the
|
||||
* frequency values in the adjusted format.
|
||||
*/
|
||||
const static struct iwl_rfi_lut_entry iwl_rfi_table[IWL_RFI_LUT_SIZE] = {
|
||||
/* LPDDR4 */
|
||||
|
||||
/* frequency 3733MHz */
|
||||
{cpu_to_le16(223), {114, 116, 118, 120, 122,},
|
||||
{PHY_BAND_5, PHY_BAND_5, PHY_BAND_5, PHY_BAND_5, PHY_BAND_5,}},
|
||||
|
||||
/* frequency 4267MHz */
|
||||
{cpu_to_le16(256), {79, 83, 85, 87, 89, 91, 93,},
|
||||
{PHY_BAND_6, PHY_BAND_6, PHY_BAND_6, PHY_BAND_6, PHY_BAND_6,
|
||||
PHY_BAND_6, PHY_BAND_6,}},
|
||||
|
||||
/* DDR5ePOR */
|
||||
|
||||
/* frequency 4000MHz */
|
||||
{cpu_to_le16(240), {3, 5, 7, 9, 11, 13, 15,},
|
||||
{PHY_BAND_6, PHY_BAND_6, PHY_BAND_6, PHY_BAND_6, PHY_BAND_6,
|
||||
PHY_BAND_6, PHY_BAND_6,}},
|
||||
|
||||
/* frequency 4400MHz */
|
||||
{cpu_to_le16(264), {111, 119, 123, 125, 129, 131, 133, 135, 143,},
|
||||
{PHY_BAND_6, PHY_BAND_6, PHY_BAND_6, PHY_BAND_6, PHY_BAND_6,
|
||||
PHY_BAND_6, PHY_BAND_6, PHY_BAND_6, PHY_BAND_6,}},
|
||||
|
||||
/* LPDDR5iPOR */
|
||||
|
||||
/* frequency 5200MHz */
|
||||
{cpu_to_le16(312), {36, 38, 40, 42, 50,},
|
||||
{PHY_BAND_5, PHY_BAND_5, PHY_BAND_5, PHY_BAND_5, PHY_BAND_5,}},
|
||||
|
||||
/* frequency 6000MHz */
|
||||
{cpu_to_le16(360), {3, 5, 7, 9, 11, 13, 15,},
|
||||
{PHY_BAND_6, PHY_BAND_6, PHY_BAND_6, PHY_BAND_6, PHY_BAND_6,
|
||||
PHY_BAND_6, PHY_BAND_6,}},
|
||||
|
||||
/* frequency 6400MHz */
|
||||
{cpu_to_le16(384), {79, 83, 85, 87, 89, 91, 93,},
|
||||
{PHY_BAND_6, PHY_BAND_6, PHY_BAND_6, PHY_BAND_6, PHY_BAND_6,
|
||||
PHY_BAND_6, PHY_BAND_6,}},
|
||||
};
|
||||
|
||||
int iwl_rfi_send_config_cmd(struct iwl_mvm *mvm, struct iwl_rfi_lut_entry *rfi_table)
|
||||
{
|
||||
int ret;
|
||||
struct iwl_rfi_config_cmd cmd;
|
||||
struct iwl_host_cmd hcmd = {
|
||||
.id = WIDE_ID(SYSTEM_GROUP, RFI_CONFIG_CMD),
|
||||
.dataflags[0] = IWL_HCMD_DFL_DUP,
|
||||
.data[0] = &cmd,
|
||||
.len[0] = sizeof(cmd),
|
||||
};
|
||||
|
||||
if (!fw_has_capa(&mvm->fw->ucode_capa, IWL_UCODE_TLV_CAPA_RFIM_SUPPORT))
|
||||
return -EOPNOTSUPP;
|
||||
|
||||
/* in case no table is passed, use the default one */
|
||||
if (!rfi_table) {
|
||||
memcpy(cmd.table, iwl_rfi_table, sizeof(cmd.table));
|
||||
} else {
|
||||
memcpy(cmd.table, rfi_table, sizeof(cmd.table));
|
||||
/* notify FW the table is not the default one */
|
||||
cmd.oem = 1;
|
||||
}
|
||||
|
||||
mutex_lock(&mvm->mutex);
|
||||
ret = iwl_mvm_send_cmd(mvm, &hcmd);
|
||||
mutex_unlock(&mvm->mutex);
|
||||
|
||||
if (ret)
|
||||
IWL_ERR(mvm, "Failed to send RFI config cmd %d\n", ret);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
struct iwl_rfi_freq_table_resp_cmd *iwl_rfi_get_freq_table(struct iwl_mvm *mvm)
|
||||
{
|
||||
struct iwl_rfi_freq_table_resp_cmd *resp;
|
||||
int resp_size = sizeof(*resp);
|
||||
int ret;
|
||||
struct iwl_host_cmd cmd = {
|
||||
.id = WIDE_ID(SYSTEM_GROUP, RFI_GET_FREQ_TABLE_CMD),
|
||||
.flags = CMD_WANT_SKB,
|
||||
};
|
||||
|
||||
if (!fw_has_capa(&mvm->fw->ucode_capa, IWL_UCODE_TLV_CAPA_RFIM_SUPPORT))
|
||||
return ERR_PTR(-EOPNOTSUPP);
|
||||
|
||||
mutex_lock(&mvm->mutex);
|
||||
ret = iwl_mvm_send_cmd(mvm, &cmd);
|
||||
mutex_unlock(&mvm->mutex);
|
||||
if (ret)
|
||||
return ERR_PTR(ret);
|
||||
|
||||
if (WARN_ON_ONCE(iwl_rx_packet_payload_len(cmd.resp_pkt) != resp_size))
|
||||
return ERR_PTR(-EIO);
|
||||
|
||||
resp = kzalloc(resp_size, GFP_KERNEL);
|
||||
if (!resp)
|
||||
return ERR_PTR(-ENOMEM);
|
||||
|
||||
memcpy(resp, cmd.resp_pkt->data, resp_size);
|
||||
|
||||
iwl_free_resp(&cmd);
|
||||
return resp;
|
||||
}
|
|
@ -1253,14 +1253,16 @@ int iwl_mvm_config_scan(struct iwl_mvm *mvm)
|
|||
memset(&cfg, 0, sizeof(cfg));
|
||||
|
||||
if (iwl_fw_lookup_cmd_ver(mvm->fw, LONG_GROUP,
|
||||
ADD_STA, 0) < 12)
|
||||
ADD_STA, 0) < 12) {
|
||||
cfg.bcast_sta_id = mvm->aux_sta.sta_id;
|
||||
/*
|
||||
* Fw doesn't use this sta anymore, pending deprecation via HOST API
|
||||
* change.
|
||||
*/
|
||||
else
|
||||
} else if (iwl_fw_lookup_cmd_ver(mvm->fw, LONG_GROUP,
|
||||
SCAN_CFG_CMD, 0) < 5) {
|
||||
/*
|
||||
* Fw doesn't use this sta anymore. Deprecated on SCAN_CFG_CMD
|
||||
* version 5.
|
||||
*/
|
||||
cfg.bcast_sta_id = 0xff;
|
||||
}
|
||||
|
||||
cfg.tx_chains = cpu_to_le32(iwl_mvm_get_valid_tx_ant(mvm));
|
||||
cfg.rx_chains = cpu_to_le32(iwl_mvm_scan_rx_ant(mvm));
|
||||
|
|
|
@ -999,9 +999,6 @@ void iwl_mvm_remove_csa_period(struct iwl_mvm *mvm,
|
|||
|
||||
lockdep_assert_held(&mvm->mutex);
|
||||
|
||||
if (!te_data->running)
|
||||
return;
|
||||
|
||||
spin_lock_bh(&mvm->time_event_lock);
|
||||
id = te_data->id;
|
||||
spin_unlock_bh(&mvm->time_event_lock);
|
||||
|
|
|
@ -261,7 +261,7 @@ int iwl_mvm_get_temp(struct iwl_mvm *mvm, s32 *temp)
|
|||
ret = iwl_wait_notification(&mvm->notif_wait, &wait_temp_notif,
|
||||
IWL_MVM_TEMP_NOTIF_WAIT_TIMEOUT);
|
||||
if (ret)
|
||||
IWL_ERR(mvm, "Getting the temperature timed out\n");
|
||||
IWL_WARN(mvm, "Getting the temperature timed out\n");
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
|
|
@ -265,20 +265,24 @@ static u32 iwl_mvm_get_tx_rate(struct iwl_mvm *mvm,
|
|||
struct ieee80211_tx_info *info,
|
||||
struct ieee80211_sta *sta, __le16 fc)
|
||||
{
|
||||
int rate_idx;
|
||||
int rate_idx = -1;
|
||||
u8 rate_plcp;
|
||||
u32 rate_flags = 0;
|
||||
struct iwl_mvm_sta *mvmsta = iwl_mvm_sta_from_mac80211(sta);
|
||||
|
||||
/* HT rate doesn't make sense for a non data frame */
|
||||
WARN_ONCE(info->control.rates[0].flags & IEEE80211_TX_RC_MCS &&
|
||||
!ieee80211_is_data(fc),
|
||||
"Got a HT rate (flags:0x%x/mcs:%d/fc:0x%x/state:%d) for a non data frame\n",
|
||||
info->control.rates[0].flags,
|
||||
info->control.rates[0].idx,
|
||||
le16_to_cpu(fc), mvmsta->sta_state);
|
||||
/* info->control is only relevant for non HW rate control */
|
||||
if (!ieee80211_hw_check(mvm->hw, HAS_RATE_CONTROL)) {
|
||||
/* HT rate doesn't make sense for a non data frame */
|
||||
WARN_ONCE(info->control.rates[0].flags & IEEE80211_TX_RC_MCS &&
|
||||
!ieee80211_is_data(fc),
|
||||
"Got a HT rate (flags:0x%x/mcs:%d/fc:0x%x/state:%d) for a non data frame\n",
|
||||
info->control.rates[0].flags,
|
||||
info->control.rates[0].idx,
|
||||
le16_to_cpu(fc), mvmsta->sta_state);
|
||||
|
||||
rate_idx = info->control.rates[0].idx;
|
||||
}
|
||||
|
||||
rate_idx = info->control.rates[0].idx;
|
||||
/* if the rate isn't a well known legacy rate, take the lowest one */
|
||||
if (rate_idx < 0 || rate_idx >= IWL_RATE_COUNT_LEGACY)
|
||||
rate_idx = rate_lowest_index(
|
||||
|
|
|
@ -298,16 +298,19 @@ int iwl_trans_pcie_ctx_info_gen3_set_pnvm(struct iwl_trans *trans,
|
|||
if (trans->trans_cfg->device_family < IWL_DEVICE_FAMILY_AX210)
|
||||
return 0;
|
||||
|
||||
ret = iwl_pcie_ctxt_info_alloc_dma(trans, data, len,
|
||||
&trans_pcie->pnvm_dram);
|
||||
if (ret < 0) {
|
||||
IWL_DEBUG_FW(trans, "Failed to allocate PNVM DMA %d.\n",
|
||||
ret);
|
||||
return ret;
|
||||
}
|
||||
/* only allocate the DRAM if not allocated yet */
|
||||
if (!trans->pnvm_loaded) {
|
||||
if (WARN_ON(prph_sc_ctrl->pnvm_cfg.pnvm_size))
|
||||
return -EBUSY;
|
||||
|
||||
if (WARN_ON(prph_sc_ctrl->pnvm_cfg.pnvm_size))
|
||||
return -EBUSY;
|
||||
ret = iwl_pcie_ctxt_info_alloc_dma(trans, data, len,
|
||||
&trans_pcie->pnvm_dram);
|
||||
if (ret < 0) {
|
||||
IWL_DEBUG_FW(trans, "Failed to allocate PNVM DMA %d.\n",
|
||||
ret);
|
||||
return ret;
|
||||
}
|
||||
}
|
||||
|
||||
prph_sc_ctrl->pnvm_cfg.pnvm_base_addr =
|
||||
cpu_to_le64(trans_pcie->pnvm_dram.physical);
|
||||
|
|
|
@ -488,7 +488,7 @@ static const struct pci_device_id iwl_hw_card_ids[] = {
|
|||
|
||||
/* Ma devices */
|
||||
{IWL_PCI_DEVICE(0x2729, PCI_ANY_ID, iwl_ma_trans_cfg)},
|
||||
{IWL_PCI_DEVICE(0x7E80, PCI_ANY_ID, iwl_ma_trans_cfg)},
|
||||
{IWL_PCI_DEVICE(0x7E40, PCI_ANY_ID, iwl_ma_trans_cfg)},
|
||||
|
||||
#endif /* CONFIG_IWLMVM */
|
||||
|
||||
|
@ -497,16 +497,16 @@ static const struct pci_device_id iwl_hw_card_ids[] = {
|
|||
MODULE_DEVICE_TABLE(pci, iwl_hw_card_ids);
|
||||
|
||||
#define _IWL_DEV_INFO(_device, _subdevice, _mac_type, _mac_step, _rf_type, \
|
||||
_rf_id, _no_160, _cores, _cfg, _name) \
|
||||
_rf_id, _no_160, _cores, _cdb, _cfg, _name) \
|
||||
{ .device = (_device), .subdevice = (_subdevice), .cfg = &(_cfg), \
|
||||
.name = _name, .mac_type = _mac_type, .rf_type = _rf_type, \
|
||||
.no_160 = _no_160, .cores = _cores, .rf_id = _rf_id, \
|
||||
.mac_step = _mac_step }
|
||||
.mac_step = _mac_step, .cdb = _cdb }
|
||||
|
||||
#define IWL_DEV_INFO(_device, _subdevice, _cfg, _name) \
|
||||
_IWL_DEV_INFO(_device, _subdevice, IWL_CFG_ANY, IWL_CFG_ANY, \
|
||||
IWL_CFG_ANY, IWL_CFG_ANY, IWL_CFG_ANY, IWL_CFG_ANY, \
|
||||
_cfg, _name)
|
||||
IWL_CFG_NO_CDB, _cfg, _name)
|
||||
|
||||
static const struct iwl_dev_info iwl_dev_info_table[] = {
|
||||
#if IS_ENABLED(CONFIG_IWLMVM)
|
||||
|
@ -596,9 +596,16 @@ static const struct iwl_dev_info iwl_dev_info_table[] = {
|
|||
/* So with HR */
|
||||
IWL_DEV_INFO(0x2725, 0x0090, iwlax211_2ax_cfg_so_gf_a0, NULL),
|
||||
IWL_DEV_INFO(0x2725, 0x0020, iwlax210_2ax_cfg_ty_gf_a0, NULL),
|
||||
IWL_DEV_INFO(0x2725, 0x2020, iwlax210_2ax_cfg_ty_gf_a0, NULL),
|
||||
IWL_DEV_INFO(0x2725, 0x0024, iwlax210_2ax_cfg_ty_gf_a0, NULL),
|
||||
IWL_DEV_INFO(0x2725, 0x0310, iwlax210_2ax_cfg_ty_gf_a0, NULL),
|
||||
IWL_DEV_INFO(0x2725, 0x0510, iwlax210_2ax_cfg_ty_gf_a0, NULL),
|
||||
IWL_DEV_INFO(0x2725, 0x0A10, iwlax210_2ax_cfg_ty_gf_a0, NULL),
|
||||
IWL_DEV_INFO(0x2725, 0xE020, iwlax210_2ax_cfg_ty_gf_a0, NULL),
|
||||
IWL_DEV_INFO(0x2725, 0xE024, iwlax210_2ax_cfg_ty_gf_a0, NULL),
|
||||
IWL_DEV_INFO(0x2725, 0x4020, iwlax210_2ax_cfg_ty_gf_a0, NULL),
|
||||
IWL_DEV_INFO(0x2725, 0x6020, iwlax210_2ax_cfg_ty_gf_a0, NULL),
|
||||
IWL_DEV_INFO(0x2725, 0x6024, iwlax210_2ax_cfg_ty_gf_a0, NULL),
|
||||
IWL_DEV_INFO(0x7A70, 0x0090, iwlax211_2ax_cfg_so_gf_a0_long, NULL),
|
||||
IWL_DEV_INFO(0x7A70, 0x0098, iwlax211_2ax_cfg_so_gf_a0_long, NULL),
|
||||
IWL_DEV_INFO(0x7A70, 0x00B0, iwlax411_2ax_cfg_so_gf4_a0_long, NULL),
|
||||
|
@ -617,6 +624,7 @@ static const struct iwl_dev_info iwl_dev_info_table[] = {
|
|||
IWL_DEV_INFO(0x2726, 0x0090, iwlax211_cfg_snj_gf_a0, NULL),
|
||||
IWL_DEV_INFO(0x2726, 0x0098, iwlax211_cfg_snj_gf_a0, NULL),
|
||||
IWL_DEV_INFO(0x2726, 0x00B0, iwlax411_2ax_cfg_sosnj_gf4_a0, NULL),
|
||||
IWL_DEV_INFO(0x2726, 0x00B4, iwlax411_2ax_cfg_sosnj_gf4_a0, NULL),
|
||||
IWL_DEV_INFO(0x2726, 0x0510, iwlax211_cfg_snj_gf_a0, NULL),
|
||||
IWL_DEV_INFO(0x2726, 0x1651, iwl_cfg_snj_hr_b0, iwl_ax201_killer_1650s_name),
|
||||
IWL_DEV_INFO(0x2726, 0x1652, iwl_cfg_snj_hr_b0, iwl_ax201_killer_1650i_name),
|
||||
|
@ -624,98 +632,98 @@ static const struct iwl_dev_info iwl_dev_info_table[] = {
|
|||
_IWL_DEV_INFO(IWL_CFG_ANY, IWL_CFG_ANY,
|
||||
IWL_CFG_MAC_TYPE_PU, IWL_CFG_ANY,
|
||||
IWL_CFG_RF_TYPE_JF1, IWL_CFG_RF_ID_JF1,
|
||||
IWL_CFG_160, IWL_CFG_CORES_BT,
|
||||
IWL_CFG_160, IWL_CFG_CORES_BT, IWL_CFG_NO_CDB,
|
||||
iwl9560_2ac_cfg_soc, iwl9461_160_name),
|
||||
_IWL_DEV_INFO(IWL_CFG_ANY, IWL_CFG_ANY,
|
||||
IWL_CFG_MAC_TYPE_PU, IWL_CFG_ANY,
|
||||
IWL_CFG_RF_TYPE_JF1, IWL_CFG_RF_ID_JF1,
|
||||
IWL_CFG_NO_160, IWL_CFG_CORES_BT,
|
||||
IWL_CFG_NO_160, IWL_CFG_CORES_BT, IWL_CFG_NO_CDB,
|
||||
iwl9560_2ac_cfg_soc, iwl9461_name),
|
||||
_IWL_DEV_INFO(IWL_CFG_ANY, IWL_CFG_ANY,
|
||||
IWL_CFG_MAC_TYPE_PU, IWL_CFG_ANY,
|
||||
IWL_CFG_RF_TYPE_JF1, IWL_CFG_RF_ID_JF1_DIV,
|
||||
IWL_CFG_160, IWL_CFG_CORES_BT,
|
||||
IWL_CFG_160, IWL_CFG_CORES_BT, IWL_CFG_NO_CDB,
|
||||
iwl9560_2ac_cfg_soc, iwl9462_160_name),
|
||||
_IWL_DEV_INFO(IWL_CFG_ANY, IWL_CFG_ANY,
|
||||
IWL_CFG_MAC_TYPE_PU, IWL_CFG_ANY,
|
||||
IWL_CFG_RF_TYPE_JF1, IWL_CFG_RF_ID_JF1_DIV,
|
||||
IWL_CFG_NO_160, IWL_CFG_CORES_BT,
|
||||
IWL_CFG_NO_160, IWL_CFG_CORES_BT, IWL_CFG_NO_CDB,
|
||||
iwl9560_2ac_cfg_soc, iwl9462_name),
|
||||
|
||||
_IWL_DEV_INFO(IWL_CFG_ANY, IWL_CFG_ANY,
|
||||
IWL_CFG_MAC_TYPE_PU, IWL_CFG_ANY,
|
||||
IWL_CFG_RF_TYPE_JF2, IWL_CFG_RF_ID_JF,
|
||||
IWL_CFG_160, IWL_CFG_CORES_BT,
|
||||
IWL_CFG_160, IWL_CFG_CORES_BT, IWL_CFG_NO_CDB,
|
||||
iwl9560_2ac_cfg_soc, iwl9560_160_name),
|
||||
_IWL_DEV_INFO(IWL_CFG_ANY, IWL_CFG_ANY,
|
||||
IWL_CFG_MAC_TYPE_PU, IWL_CFG_ANY,
|
||||
IWL_CFG_RF_TYPE_JF2, IWL_CFG_RF_ID_JF,
|
||||
IWL_CFG_NO_160, IWL_CFG_CORES_BT,
|
||||
IWL_CFG_NO_160, IWL_CFG_CORES_BT, IWL_CFG_NO_CDB,
|
||||
iwl9560_2ac_cfg_soc, iwl9560_name),
|
||||
|
||||
_IWL_DEV_INFO(0x2526, IWL_CFG_ANY,
|
||||
IWL_CFG_MAC_TYPE_PNJ, IWL_CFG_ANY,
|
||||
IWL_CFG_RF_TYPE_JF1, IWL_CFG_RF_ID_JF1,
|
||||
IWL_CFG_160, IWL_CFG_CORES_BT,
|
||||
IWL_CFG_160, IWL_CFG_CORES_BT, IWL_CFG_NO_CDB,
|
||||
iwl9260_2ac_cfg, iwl9461_160_name),
|
||||
_IWL_DEV_INFO(0x2526, IWL_CFG_ANY,
|
||||
IWL_CFG_MAC_TYPE_PNJ, IWL_CFG_ANY,
|
||||
IWL_CFG_RF_TYPE_JF1, IWL_CFG_RF_ID_JF1,
|
||||
IWL_CFG_NO_160, IWL_CFG_CORES_BT,
|
||||
IWL_CFG_NO_160, IWL_CFG_CORES_BT, IWL_CFG_NO_CDB,
|
||||
iwl9260_2ac_cfg, iwl9461_name),
|
||||
_IWL_DEV_INFO(0x2526, IWL_CFG_ANY,
|
||||
IWL_CFG_MAC_TYPE_PNJ, IWL_CFG_ANY,
|
||||
IWL_CFG_RF_TYPE_JF1, IWL_CFG_RF_ID_JF1_DIV,
|
||||
IWL_CFG_160, IWL_CFG_CORES_BT,
|
||||
IWL_CFG_160, IWL_CFG_CORES_BT, IWL_CFG_NO_CDB,
|
||||
iwl9260_2ac_cfg, iwl9462_160_name),
|
||||
_IWL_DEV_INFO(0x2526, IWL_CFG_ANY,
|
||||
IWL_CFG_MAC_TYPE_PNJ, IWL_CFG_ANY,
|
||||
IWL_CFG_RF_TYPE_JF1, IWL_CFG_RF_ID_JF1_DIV,
|
||||
IWL_CFG_NO_160, IWL_CFG_CORES_BT,
|
||||
IWL_CFG_NO_160, IWL_CFG_CORES_BT, IWL_CFG_NO_CDB,
|
||||
iwl9260_2ac_cfg, iwl9462_name),
|
||||
|
||||
_IWL_DEV_INFO(0x2526, IWL_CFG_ANY,
|
||||
IWL_CFG_MAC_TYPE_PNJ, IWL_CFG_ANY,
|
||||
IWL_CFG_RF_TYPE_JF2, IWL_CFG_RF_ID_JF,
|
||||
IWL_CFG_160, IWL_CFG_CORES_BT,
|
||||
IWL_CFG_160, IWL_CFG_CORES_BT, IWL_CFG_NO_CDB,
|
||||
iwl9260_2ac_cfg, iwl9560_160_name),
|
||||
_IWL_DEV_INFO(0x2526, IWL_CFG_ANY,
|
||||
IWL_CFG_MAC_TYPE_PNJ, IWL_CFG_ANY,
|
||||
IWL_CFG_RF_TYPE_JF2, IWL_CFG_RF_ID_JF,
|
||||
IWL_CFG_NO_160, IWL_CFG_CORES_BT,
|
||||
IWL_CFG_NO_160, IWL_CFG_CORES_BT, IWL_CFG_NO_CDB,
|
||||
iwl9260_2ac_cfg, iwl9560_name),
|
||||
|
||||
_IWL_DEV_INFO(0x2526, IWL_CFG_ANY,
|
||||
IWL_CFG_MAC_TYPE_TH, IWL_CFG_ANY,
|
||||
IWL_CFG_RF_TYPE_TH, IWL_CFG_ANY,
|
||||
IWL_CFG_160, IWL_CFG_CORES_BT_GNSS,
|
||||
IWL_CFG_160, IWL_CFG_CORES_BT_GNSS, IWL_CFG_NO_CDB,
|
||||
iwl9260_2ac_cfg, iwl9270_160_name),
|
||||
_IWL_DEV_INFO(0x2526, IWL_CFG_ANY,
|
||||
IWL_CFG_MAC_TYPE_TH, IWL_CFG_ANY,
|
||||
IWL_CFG_RF_TYPE_TH, IWL_CFG_ANY,
|
||||
IWL_CFG_NO_160, IWL_CFG_CORES_BT_GNSS,
|
||||
IWL_CFG_NO_160, IWL_CFG_CORES_BT_GNSS, IWL_CFG_NO_CDB,
|
||||
iwl9260_2ac_cfg, iwl9270_name),
|
||||
|
||||
_IWL_DEV_INFO(0x271B, IWL_CFG_ANY,
|
||||
IWL_CFG_MAC_TYPE_TH, IWL_CFG_ANY,
|
||||
IWL_CFG_RF_TYPE_TH1, IWL_CFG_ANY,
|
||||
IWL_CFG_160, IWL_CFG_CORES_BT,
|
||||
IWL_CFG_160, IWL_CFG_CORES_BT, IWL_CFG_NO_CDB,
|
||||
iwl9260_2ac_cfg, iwl9162_160_name),
|
||||
_IWL_DEV_INFO(0x271B, IWL_CFG_ANY,
|
||||
IWL_CFG_MAC_TYPE_TH, IWL_CFG_ANY,
|
||||
IWL_CFG_RF_TYPE_TH1, IWL_CFG_ANY,
|
||||
IWL_CFG_NO_160, IWL_CFG_CORES_BT,
|
||||
IWL_CFG_NO_160, IWL_CFG_CORES_BT, IWL_CFG_NO_CDB,
|
||||
iwl9260_2ac_cfg, iwl9162_name),
|
||||
|
||||
_IWL_DEV_INFO(0x2526, IWL_CFG_ANY,
|
||||
IWL_CFG_MAC_TYPE_TH, IWL_CFG_ANY,
|
||||
IWL_CFG_RF_TYPE_TH, IWL_CFG_ANY,
|
||||
IWL_CFG_160, IWL_CFG_CORES_BT,
|
||||
IWL_CFG_160, IWL_CFG_CORES_BT, IWL_CFG_NO_CDB,
|
||||
iwl9260_2ac_cfg, iwl9260_160_name),
|
||||
_IWL_DEV_INFO(0x2526, IWL_CFG_ANY,
|
||||
IWL_CFG_MAC_TYPE_TH, IWL_CFG_ANY,
|
||||
IWL_CFG_RF_TYPE_TH, IWL_CFG_ANY,
|
||||
IWL_CFG_NO_160, IWL_CFG_CORES_BT,
|
||||
IWL_CFG_NO_160, IWL_CFG_CORES_BT, IWL_CFG_NO_CDB,
|
||||
iwl9260_2ac_cfg, iwl9260_name),
|
||||
|
||||
/* Qu with Jf */
|
||||
|
@ -723,176 +731,176 @@ static const struct iwl_dev_info iwl_dev_info_table[] = {
|
|||
_IWL_DEV_INFO(IWL_CFG_ANY, IWL_CFG_ANY,
|
||||
IWL_CFG_MAC_TYPE_QU, SILICON_B_STEP,
|
||||
IWL_CFG_RF_TYPE_JF1, IWL_CFG_RF_ID_JF1,
|
||||
IWL_CFG_160, IWL_CFG_CORES_BT,
|
||||
IWL_CFG_160, IWL_CFG_CORES_BT, IWL_CFG_NO_CDB,
|
||||
iwl9560_qu_b0_jf_b0_cfg, iwl9461_160_name),
|
||||
_IWL_DEV_INFO(IWL_CFG_ANY, IWL_CFG_ANY,
|
||||
IWL_CFG_MAC_TYPE_QU, SILICON_B_STEP,
|
||||
IWL_CFG_RF_TYPE_JF1, IWL_CFG_RF_ID_JF1,
|
||||
IWL_CFG_NO_160, IWL_CFG_CORES_BT,
|
||||
IWL_CFG_NO_160, IWL_CFG_CORES_BT, IWL_CFG_NO_CDB,
|
||||
iwl9560_qu_b0_jf_b0_cfg, iwl9461_name),
|
||||
_IWL_DEV_INFO(IWL_CFG_ANY, IWL_CFG_ANY,
|
||||
IWL_CFG_MAC_TYPE_QU, SILICON_B_STEP,
|
||||
IWL_CFG_RF_TYPE_JF1, IWL_CFG_RF_ID_JF1_DIV,
|
||||
IWL_CFG_160, IWL_CFG_CORES_BT,
|
||||
IWL_CFG_160, IWL_CFG_CORES_BT, IWL_CFG_NO_CDB,
|
||||
iwl9560_qu_b0_jf_b0_cfg, iwl9462_160_name),
|
||||
_IWL_DEV_INFO(IWL_CFG_ANY, IWL_CFG_ANY,
|
||||
IWL_CFG_MAC_TYPE_QU, SILICON_B_STEP,
|
||||
IWL_CFG_RF_TYPE_JF1, IWL_CFG_RF_ID_JF1_DIV,
|
||||
IWL_CFG_NO_160, IWL_CFG_CORES_BT,
|
||||
IWL_CFG_NO_160, IWL_CFG_CORES_BT, IWL_CFG_NO_CDB,
|
||||
iwl9560_qu_b0_jf_b0_cfg, iwl9462_name),
|
||||
|
||||
_IWL_DEV_INFO(IWL_CFG_ANY, IWL_CFG_ANY,
|
||||
IWL_CFG_MAC_TYPE_QU, SILICON_B_STEP,
|
||||
IWL_CFG_RF_TYPE_JF2, IWL_CFG_RF_ID_JF,
|
||||
IWL_CFG_160, IWL_CFG_CORES_BT,
|
||||
IWL_CFG_160, IWL_CFG_CORES_BT, IWL_CFG_NO_CDB,
|
||||
iwl9560_qu_b0_jf_b0_cfg, iwl9560_160_name),
|
||||
_IWL_DEV_INFO(IWL_CFG_ANY, IWL_CFG_ANY,
|
||||
IWL_CFG_MAC_TYPE_QU, SILICON_B_STEP,
|
||||
IWL_CFG_RF_TYPE_JF2, IWL_CFG_RF_ID_JF,
|
||||
IWL_CFG_NO_160, IWL_CFG_CORES_BT,
|
||||
IWL_CFG_NO_160, IWL_CFG_CORES_BT, IWL_CFG_NO_CDB,
|
||||
iwl9560_qu_b0_jf_b0_cfg, iwl9560_name),
|
||||
|
||||
_IWL_DEV_INFO(IWL_CFG_ANY, 0x1551,
|
||||
IWL_CFG_MAC_TYPE_QU, SILICON_B_STEP,
|
||||
IWL_CFG_RF_TYPE_JF2, IWL_CFG_RF_ID_JF,
|
||||
IWL_CFG_NO_160, IWL_CFG_CORES_BT,
|
||||
IWL_CFG_NO_160, IWL_CFG_CORES_BT, IWL_CFG_NO_CDB,
|
||||
iwl9560_qu_b0_jf_b0_cfg, iwl9560_killer_1550s_name),
|
||||
_IWL_DEV_INFO(IWL_CFG_ANY, 0x1552,
|
||||
IWL_CFG_MAC_TYPE_QU, SILICON_B_STEP,
|
||||
IWL_CFG_RF_TYPE_JF2, IWL_CFG_RF_ID_JF,
|
||||
IWL_CFG_NO_160, IWL_CFG_CORES_BT,
|
||||
IWL_CFG_NO_160, IWL_CFG_CORES_BT, IWL_CFG_NO_CDB,
|
||||
iwl9560_qu_b0_jf_b0_cfg, iwl9560_killer_1550i_name),
|
||||
|
||||
/* Qu C step */
|
||||
_IWL_DEV_INFO(IWL_CFG_ANY, IWL_CFG_ANY,
|
||||
IWL_CFG_MAC_TYPE_QU, SILICON_C_STEP,
|
||||
IWL_CFG_RF_TYPE_JF1, IWL_CFG_RF_ID_JF1,
|
||||
IWL_CFG_160, IWL_CFG_CORES_BT,
|
||||
IWL_CFG_160, IWL_CFG_CORES_BT, IWL_CFG_NO_CDB,
|
||||
iwl9560_qu_c0_jf_b0_cfg, iwl9461_160_name),
|
||||
_IWL_DEV_INFO(IWL_CFG_ANY, IWL_CFG_ANY,
|
||||
IWL_CFG_MAC_TYPE_QU, SILICON_C_STEP,
|
||||
IWL_CFG_RF_TYPE_JF1, IWL_CFG_RF_ID_JF1,
|
||||
IWL_CFG_NO_160, IWL_CFG_CORES_BT,
|
||||
IWL_CFG_NO_160, IWL_CFG_CORES_BT, IWL_CFG_NO_CDB,
|
||||
iwl9560_qu_c0_jf_b0_cfg, iwl9461_name),
|
||||
_IWL_DEV_INFO(IWL_CFG_ANY, IWL_CFG_ANY,
|
||||
IWL_CFG_MAC_TYPE_QU, SILICON_C_STEP,
|
||||
IWL_CFG_RF_TYPE_JF1, IWL_CFG_RF_ID_JF1_DIV,
|
||||
IWL_CFG_160, IWL_CFG_CORES_BT,
|
||||
IWL_CFG_160, IWL_CFG_CORES_BT, IWL_CFG_NO_CDB,
|
||||
iwl9560_qu_c0_jf_b0_cfg, iwl9462_160_name),
|
||||
_IWL_DEV_INFO(IWL_CFG_ANY, IWL_CFG_ANY,
|
||||
IWL_CFG_MAC_TYPE_QU, SILICON_C_STEP,
|
||||
IWL_CFG_RF_TYPE_JF1, IWL_CFG_RF_ID_JF1_DIV,
|
||||
IWL_CFG_NO_160, IWL_CFG_CORES_BT,
|
||||
IWL_CFG_NO_160, IWL_CFG_CORES_BT, IWL_CFG_NO_CDB,
|
||||
iwl9560_qu_c0_jf_b0_cfg, iwl9462_name),
|
||||
|
||||
_IWL_DEV_INFO(IWL_CFG_ANY, IWL_CFG_ANY,
|
||||
IWL_CFG_MAC_TYPE_QU, SILICON_C_STEP,
|
||||
IWL_CFG_RF_TYPE_JF2, IWL_CFG_RF_ID_JF,
|
||||
IWL_CFG_160, IWL_CFG_CORES_BT,
|
||||
IWL_CFG_160, IWL_CFG_CORES_BT, IWL_CFG_NO_CDB,
|
||||
iwl9560_qu_c0_jf_b0_cfg, iwl9560_160_name),
|
||||
_IWL_DEV_INFO(IWL_CFG_ANY, IWL_CFG_ANY,
|
||||
IWL_CFG_MAC_TYPE_QU, SILICON_C_STEP,
|
||||
IWL_CFG_RF_TYPE_JF2, IWL_CFG_RF_ID_JF,
|
||||
IWL_CFG_NO_160, IWL_CFG_CORES_BT,
|
||||
IWL_CFG_NO_160, IWL_CFG_CORES_BT, IWL_CFG_NO_CDB,
|
||||
iwl9560_qu_c0_jf_b0_cfg, iwl9560_name),
|
||||
|
||||
_IWL_DEV_INFO(IWL_CFG_ANY, 0x1551,
|
||||
IWL_CFG_MAC_TYPE_QU, SILICON_C_STEP,
|
||||
IWL_CFG_RF_TYPE_JF2, IWL_CFG_RF_ID_JF,
|
||||
IWL_CFG_160, IWL_CFG_CORES_BT,
|
||||
IWL_CFG_160, IWL_CFG_CORES_BT, IWL_CFG_NO_CDB,
|
||||
iwl9560_qu_c0_jf_b0_cfg, iwl9560_killer_1550s_name),
|
||||
_IWL_DEV_INFO(IWL_CFG_ANY, 0x1552,
|
||||
IWL_CFG_MAC_TYPE_QU, SILICON_C_STEP,
|
||||
IWL_CFG_RF_TYPE_JF2, IWL_CFG_RF_ID_JF,
|
||||
IWL_CFG_NO_160, IWL_CFG_CORES_BT,
|
||||
IWL_CFG_NO_160, IWL_CFG_CORES_BT, IWL_CFG_NO_CDB,
|
||||
iwl9560_qu_c0_jf_b0_cfg, iwl9560_killer_1550i_name),
|
||||
|
||||
/* QuZ */
|
||||
_IWL_DEV_INFO(IWL_CFG_ANY, IWL_CFG_ANY,
|
||||
IWL_CFG_MAC_TYPE_QUZ, IWL_CFG_ANY,
|
||||
IWL_CFG_RF_TYPE_JF1, IWL_CFG_RF_ID_JF1,
|
||||
IWL_CFG_160, IWL_CFG_CORES_BT,
|
||||
IWL_CFG_160, IWL_CFG_CORES_BT, IWL_CFG_NO_CDB,
|
||||
iwl9560_quz_a0_jf_b0_cfg, iwl9461_160_name),
|
||||
_IWL_DEV_INFO(IWL_CFG_ANY, IWL_CFG_ANY,
|
||||
IWL_CFG_MAC_TYPE_QUZ, IWL_CFG_ANY,
|
||||
IWL_CFG_RF_TYPE_JF1, IWL_CFG_RF_ID_JF1,
|
||||
IWL_CFG_NO_160, IWL_CFG_CORES_BT,
|
||||
IWL_CFG_NO_160, IWL_CFG_CORES_BT, IWL_CFG_NO_CDB,
|
||||
iwl9560_quz_a0_jf_b0_cfg, iwl9461_name),
|
||||
_IWL_DEV_INFO(IWL_CFG_ANY, IWL_CFG_ANY,
|
||||
IWL_CFG_MAC_TYPE_QUZ, IWL_CFG_ANY,
|
||||
IWL_CFG_RF_TYPE_JF1, IWL_CFG_RF_ID_JF1_DIV,
|
||||
IWL_CFG_160, IWL_CFG_CORES_BT,
|
||||
IWL_CFG_160, IWL_CFG_CORES_BT, IWL_CFG_NO_CDB,
|
||||
iwl9560_quz_a0_jf_b0_cfg, iwl9462_160_name),
|
||||
_IWL_DEV_INFO(IWL_CFG_ANY, IWL_CFG_ANY,
|
||||
IWL_CFG_MAC_TYPE_QUZ, IWL_CFG_ANY,
|
||||
IWL_CFG_RF_TYPE_JF1, IWL_CFG_RF_ID_JF1_DIV,
|
||||
IWL_CFG_NO_160, IWL_CFG_CORES_BT,
|
||||
IWL_CFG_NO_160, IWL_CFG_CORES_BT, IWL_CFG_NO_CDB,
|
||||
iwl9560_quz_a0_jf_b0_cfg, iwl9462_name),
|
||||
|
||||
_IWL_DEV_INFO(IWL_CFG_ANY, IWL_CFG_ANY,
|
||||
IWL_CFG_MAC_TYPE_QUZ, IWL_CFG_ANY,
|
||||
IWL_CFG_RF_TYPE_JF2, IWL_CFG_RF_ID_JF,
|
||||
IWL_CFG_160, IWL_CFG_CORES_BT,
|
||||
IWL_CFG_160, IWL_CFG_CORES_BT, IWL_CFG_NO_CDB,
|
||||
iwl9560_quz_a0_jf_b0_cfg, iwl9560_160_name),
|
||||
_IWL_DEV_INFO(IWL_CFG_ANY, IWL_CFG_ANY,
|
||||
IWL_CFG_MAC_TYPE_QUZ, IWL_CFG_ANY,
|
||||
IWL_CFG_RF_TYPE_JF2, IWL_CFG_RF_ID_JF,
|
||||
IWL_CFG_NO_160, IWL_CFG_CORES_BT,
|
||||
IWL_CFG_NO_160, IWL_CFG_CORES_BT, IWL_CFG_NO_CDB,
|
||||
iwl9560_quz_a0_jf_b0_cfg, iwl9560_name),
|
||||
|
||||
_IWL_DEV_INFO(IWL_CFG_ANY, 0x1551,
|
||||
IWL_CFG_MAC_TYPE_QUZ, IWL_CFG_ANY,
|
||||
IWL_CFG_RF_TYPE_JF2, IWL_CFG_RF_ID_JF,
|
||||
IWL_CFG_160, IWL_CFG_CORES_BT,
|
||||
IWL_CFG_160, IWL_CFG_CORES_BT, IWL_CFG_NO_CDB,
|
||||
iwl9560_quz_a0_jf_b0_cfg, iwl9560_killer_1550s_name),
|
||||
_IWL_DEV_INFO(IWL_CFG_ANY, 0x1552,
|
||||
IWL_CFG_MAC_TYPE_QUZ, IWL_CFG_ANY,
|
||||
IWL_CFG_RF_TYPE_JF2, IWL_CFG_RF_ID_JF,
|
||||
IWL_CFG_NO_160, IWL_CFG_CORES_BT,
|
||||
IWL_CFG_NO_160, IWL_CFG_CORES_BT, IWL_CFG_NO_CDB,
|
||||
iwl9560_quz_a0_jf_b0_cfg, iwl9560_killer_1550i_name),
|
||||
|
||||
/* QnJ */
|
||||
_IWL_DEV_INFO(IWL_CFG_ANY, IWL_CFG_ANY,
|
||||
IWL_CFG_MAC_TYPE_QNJ, IWL_CFG_ANY,
|
||||
IWL_CFG_RF_TYPE_JF1, IWL_CFG_RF_ID_JF1,
|
||||
IWL_CFG_160, IWL_CFG_CORES_BT,
|
||||
IWL_CFG_160, IWL_CFG_CORES_BT, IWL_CFG_NO_CDB,
|
||||
iwl9560_qnj_b0_jf_b0_cfg, iwl9461_160_name),
|
||||
_IWL_DEV_INFO(IWL_CFG_ANY, IWL_CFG_ANY,
|
||||
IWL_CFG_MAC_TYPE_QNJ, IWL_CFG_ANY,
|
||||
IWL_CFG_RF_TYPE_JF1, IWL_CFG_RF_ID_JF1,
|
||||
IWL_CFG_NO_160, IWL_CFG_CORES_BT,
|
||||
IWL_CFG_NO_160, IWL_CFG_CORES_BT, IWL_CFG_NO_CDB,
|
||||
iwl9560_qnj_b0_jf_b0_cfg, iwl9461_name),
|
||||
_IWL_DEV_INFO(IWL_CFG_ANY, IWL_CFG_ANY,
|
||||
IWL_CFG_MAC_TYPE_QNJ, IWL_CFG_ANY,
|
||||
IWL_CFG_RF_TYPE_JF1, IWL_CFG_RF_ID_JF1_DIV,
|
||||
IWL_CFG_160, IWL_CFG_CORES_BT,
|
||||
IWL_CFG_160, IWL_CFG_CORES_BT, IWL_CFG_NO_CDB,
|
||||
iwl9560_qnj_b0_jf_b0_cfg, iwl9462_160_name),
|
||||
_IWL_DEV_INFO(IWL_CFG_ANY, IWL_CFG_ANY,
|
||||
IWL_CFG_MAC_TYPE_QNJ, IWL_CFG_ANY,
|
||||
IWL_CFG_RF_TYPE_JF1, IWL_CFG_RF_ID_JF1_DIV,
|
||||
IWL_CFG_NO_160, IWL_CFG_CORES_BT,
|
||||
IWL_CFG_NO_160, IWL_CFG_CORES_BT, IWL_CFG_NO_CDB,
|
||||
iwl9560_qnj_b0_jf_b0_cfg, iwl9462_name),
|
||||
|
||||
_IWL_DEV_INFO(IWL_CFG_ANY, IWL_CFG_ANY,
|
||||
IWL_CFG_MAC_TYPE_QNJ, IWL_CFG_ANY,
|
||||
IWL_CFG_RF_TYPE_JF2, IWL_CFG_RF_ID_JF,
|
||||
IWL_CFG_160, IWL_CFG_CORES_BT,
|
||||
IWL_CFG_160, IWL_CFG_CORES_BT, IWL_CFG_NO_CDB,
|
||||
iwl9560_qnj_b0_jf_b0_cfg, iwl9560_160_name),
|
||||
_IWL_DEV_INFO(IWL_CFG_ANY, IWL_CFG_ANY,
|
||||
IWL_CFG_MAC_TYPE_QNJ, IWL_CFG_ANY,
|
||||
IWL_CFG_RF_TYPE_JF2, IWL_CFG_RF_ID_JF,
|
||||
IWL_CFG_NO_160, IWL_CFG_CORES_BT,
|
||||
IWL_CFG_NO_160, IWL_CFG_CORES_BT, IWL_CFG_NO_CDB,
|
||||
iwl9560_qnj_b0_jf_b0_cfg, iwl9560_name),
|
||||
|
||||
_IWL_DEV_INFO(IWL_CFG_ANY, 0x1551,
|
||||
IWL_CFG_MAC_TYPE_QNJ, IWL_CFG_ANY,
|
||||
IWL_CFG_RF_TYPE_JF2, IWL_CFG_RF_ID_JF,
|
||||
IWL_CFG_160, IWL_CFG_CORES_BT,
|
||||
IWL_CFG_160, IWL_CFG_CORES_BT, IWL_CFG_NO_CDB,
|
||||
iwl9560_qnj_b0_jf_b0_cfg, iwl9560_killer_1550s_name),
|
||||
_IWL_DEV_INFO(IWL_CFG_ANY, 0x1552,
|
||||
IWL_CFG_MAC_TYPE_QNJ, IWL_CFG_ANY,
|
||||
IWL_CFG_RF_TYPE_JF2, IWL_CFG_RF_ID_JF,
|
||||
IWL_CFG_NO_160, IWL_CFG_CORES_BT,
|
||||
IWL_CFG_NO_160, IWL_CFG_CORES_BT, IWL_CFG_NO_CDB,
|
||||
iwl9560_qnj_b0_jf_b0_cfg, iwl9560_killer_1550i_name),
|
||||
|
||||
/* Qu with Hr */
|
||||
|
@ -900,103 +908,139 @@ static const struct iwl_dev_info iwl_dev_info_table[] = {
|
|||
_IWL_DEV_INFO(IWL_CFG_ANY, IWL_CFG_ANY,
|
||||
IWL_CFG_MAC_TYPE_QU, SILICON_B_STEP,
|
||||
IWL_CFG_RF_TYPE_HR1, IWL_CFG_ANY,
|
||||
IWL_CFG_ANY, IWL_CFG_ANY,
|
||||
IWL_CFG_ANY, IWL_CFG_ANY, IWL_CFG_NO_CDB,
|
||||
iwl_qu_b0_hr1_b0, iwl_ax101_name),
|
||||
_IWL_DEV_INFO(IWL_CFG_ANY, IWL_CFG_ANY,
|
||||
IWL_CFG_MAC_TYPE_QU, SILICON_C_STEP,
|
||||
IWL_CFG_RF_TYPE_HR2, IWL_CFG_ANY,
|
||||
IWL_CFG_ANY, IWL_CFG_ANY,
|
||||
IWL_CFG_ANY, IWL_CFG_ANY, IWL_CFG_NO_CDB,
|
||||
iwl_qu_b0_hr_b0, iwl_ax203_name),
|
||||
|
||||
/* Qu C step */
|
||||
_IWL_DEV_INFO(IWL_CFG_ANY, IWL_CFG_ANY,
|
||||
IWL_CFG_MAC_TYPE_QU, SILICON_C_STEP,
|
||||
IWL_CFG_RF_TYPE_HR1, IWL_CFG_ANY,
|
||||
IWL_CFG_ANY, IWL_CFG_ANY,
|
||||
IWL_CFG_ANY, IWL_CFG_ANY, IWL_CFG_NO_CDB,
|
||||
iwl_qu_c0_hr1_b0, iwl_ax101_name),
|
||||
_IWL_DEV_INFO(IWL_CFG_ANY, IWL_CFG_ANY,
|
||||
IWL_CFG_MAC_TYPE_QU, SILICON_C_STEP,
|
||||
IWL_CFG_RF_TYPE_HR2, IWL_CFG_ANY,
|
||||
IWL_CFG_ANY, IWL_CFG_ANY,
|
||||
IWL_CFG_ANY, IWL_CFG_ANY, IWL_CFG_NO_CDB,
|
||||
iwl_qu_c0_hr_b0, iwl_ax203_name),
|
||||
|
||||
/* QuZ */
|
||||
_IWL_DEV_INFO(IWL_CFG_ANY, IWL_CFG_ANY,
|
||||
IWL_CFG_MAC_TYPE_QUZ, IWL_CFG_ANY,
|
||||
IWL_CFG_RF_TYPE_HR1, IWL_CFG_ANY,
|
||||
IWL_CFG_ANY, IWL_CFG_ANY,
|
||||
IWL_CFG_ANY, IWL_CFG_ANY, IWL_CFG_NO_CDB,
|
||||
iwl_quz_a0_hr1_b0, iwl_ax101_name),
|
||||
_IWL_DEV_INFO(IWL_CFG_ANY, IWL_CFG_ANY,
|
||||
IWL_CFG_MAC_TYPE_QUZ, SILICON_B_STEP,
|
||||
IWL_CFG_RF_TYPE_HR2, IWL_CFG_ANY,
|
||||
IWL_CFG_NO_160, IWL_CFG_ANY, IWL_CFG_NO_CDB,
|
||||
iwl_cfg_quz_a0_hr_b0, iwl_ax203_name),
|
||||
|
||||
/* QnJ with Hr */
|
||||
_IWL_DEV_INFO(IWL_CFG_ANY, IWL_CFG_ANY,
|
||||
IWL_CFG_MAC_TYPE_QNJ, IWL_CFG_ANY,
|
||||
IWL_CFG_RF_TYPE_HR2, IWL_CFG_ANY,
|
||||
IWL_CFG_ANY, IWL_CFG_ANY,
|
||||
IWL_CFG_ANY, IWL_CFG_ANY, IWL_CFG_NO_CDB,
|
||||
iwl_qnj_b0_hr_b0_cfg, iwl_ax201_name),
|
||||
|
||||
/* SnJ with Jf */
|
||||
_IWL_DEV_INFO(IWL_CFG_ANY, IWL_CFG_ANY,
|
||||
IWL_CFG_MAC_TYPE_SNJ, IWL_CFG_ANY,
|
||||
IWL_CFG_RF_TYPE_JF1, IWL_CFG_RF_ID_JF1,
|
||||
IWL_CFG_160, IWL_CFG_CORES_BT,
|
||||
IWL_CFG_160, IWL_CFG_CORES_BT, IWL_CFG_NO_CDB,
|
||||
iwl_cfg_snj_a0_jf_b0, iwl9461_160_name),
|
||||
_IWL_DEV_INFO(IWL_CFG_ANY, IWL_CFG_ANY,
|
||||
IWL_CFG_MAC_TYPE_SNJ, IWL_CFG_ANY,
|
||||
IWL_CFG_RF_TYPE_JF1, IWL_CFG_RF_ID_JF1,
|
||||
IWL_CFG_NO_160, IWL_CFG_CORES_BT,
|
||||
IWL_CFG_NO_160, IWL_CFG_CORES_BT, IWL_CFG_NO_CDB,
|
||||
iwl_cfg_snj_a0_jf_b0, iwl9461_name),
|
||||
_IWL_DEV_INFO(IWL_CFG_ANY, IWL_CFG_ANY,
|
||||
IWL_CFG_MAC_TYPE_SNJ, IWL_CFG_ANY,
|
||||
IWL_CFG_RF_TYPE_JF1, IWL_CFG_RF_ID_JF1_DIV,
|
||||
IWL_CFG_160, IWL_CFG_CORES_BT,
|
||||
IWL_CFG_160, IWL_CFG_CORES_BT, IWL_CFG_NO_CDB,
|
||||
iwl_cfg_snj_a0_jf_b0, iwl9462_160_name),
|
||||
_IWL_DEV_INFO(IWL_CFG_ANY, IWL_CFG_ANY,
|
||||
IWL_CFG_MAC_TYPE_SNJ, IWL_CFG_ANY,
|
||||
IWL_CFG_RF_TYPE_JF1, IWL_CFG_RF_ID_JF1_DIV,
|
||||
IWL_CFG_NO_160, IWL_CFG_CORES_BT,
|
||||
IWL_CFG_NO_160, IWL_CFG_CORES_BT, IWL_CFG_NO_CDB,
|
||||
iwl_cfg_snj_a0_jf_b0, iwl9462_name),
|
||||
|
||||
_IWL_DEV_INFO(IWL_CFG_ANY, IWL_CFG_ANY,
|
||||
IWL_CFG_MAC_TYPE_SNJ, IWL_CFG_ANY,
|
||||
IWL_CFG_RF_TYPE_JF2, IWL_CFG_RF_ID_JF,
|
||||
IWL_CFG_160, IWL_CFG_CORES_BT,
|
||||
IWL_CFG_160, IWL_CFG_CORES_BT, IWL_CFG_NO_CDB,
|
||||
iwl_cfg_snj_a0_jf_b0, iwl9560_160_name),
|
||||
_IWL_DEV_INFO(IWL_CFG_ANY, IWL_CFG_ANY,
|
||||
IWL_CFG_MAC_TYPE_SNJ, IWL_CFG_ANY,
|
||||
IWL_CFG_RF_TYPE_JF2, IWL_CFG_RF_ID_JF,
|
||||
IWL_CFG_NO_160, IWL_CFG_CORES_BT,
|
||||
IWL_CFG_NO_160, IWL_CFG_CORES_BT, IWL_CFG_NO_CDB,
|
||||
iwl_cfg_snj_a0_jf_b0, iwl9560_name),
|
||||
|
||||
/* SnJ with Hr */
|
||||
_IWL_DEV_INFO(IWL_CFG_ANY, IWL_CFG_ANY,
|
||||
IWL_CFG_MAC_TYPE_SNJ, IWL_CFG_ANY,
|
||||
IWL_CFG_RF_TYPE_HR1, IWL_CFG_ANY,
|
||||
IWL_CFG_ANY, IWL_CFG_ANY,
|
||||
IWL_CFG_ANY, IWL_CFG_ANY, IWL_CFG_NO_CDB,
|
||||
iwl_cfg_snj_hr_b0, iwl_ax101_name),
|
||||
|
||||
_IWL_DEV_INFO(IWL_CFG_ANY, IWL_CFG_ANY,
|
||||
IWL_CFG_MAC_TYPE_SNJ, IWL_CFG_ANY,
|
||||
IWL_CFG_RF_TYPE_HR2, IWL_CFG_ANY,
|
||||
IWL_CFG_ANY, IWL_CFG_ANY,
|
||||
IWL_CFG_ANY, IWL_CFG_ANY, IWL_CFG_NO_CDB,
|
||||
iwl_cfg_snj_hr_b0, iwl_ax201_name),
|
||||
|
||||
/* Ma */
|
||||
_IWL_DEV_INFO(IWL_CFG_ANY, IWL_CFG_ANY,
|
||||
IWL_CFG_MAC_TYPE_MA, IWL_CFG_ANY,
|
||||
IWL_CFG_RF_TYPE_HR2, IWL_CFG_ANY,
|
||||
IWL_CFG_ANY, IWL_CFG_ANY, IWL_CFG_NO_CDB,
|
||||
iwl_cfg_ma_a0_hr_b0, iwl_ax201_name),
|
||||
_IWL_DEV_INFO(IWL_CFG_ANY, IWL_CFG_ANY,
|
||||
IWL_CFG_MAC_TYPE_MA, IWL_CFG_ANY,
|
||||
IWL_CFG_RF_TYPE_GF, IWL_CFG_ANY,
|
||||
IWL_CFG_ANY, IWL_CFG_ANY,
|
||||
IWL_CFG_ANY, IWL_CFG_ANY, IWL_CFG_NO_CDB,
|
||||
iwl_cfg_ma_a0_gf_a0, iwl_ax211_name),
|
||||
_IWL_DEV_INFO(IWL_CFG_ANY, IWL_CFG_ANY,
|
||||
IWL_CFG_MAC_TYPE_MA, IWL_CFG_ANY,
|
||||
IWL_CFG_RF_TYPE_GF, IWL_CFG_ANY,
|
||||
IWL_CFG_ANY, IWL_CFG_ANY, IWL_CFG_CDB,
|
||||
iwl_cfg_ma_a0_gf4_a0, iwl_ax211_name),
|
||||
_IWL_DEV_INFO(IWL_CFG_ANY, IWL_CFG_ANY,
|
||||
IWL_CFG_MAC_TYPE_MA, IWL_CFG_ANY,
|
||||
IWL_CFG_RF_TYPE_MR, IWL_CFG_ANY,
|
||||
IWL_CFG_ANY, IWL_CFG_ANY,
|
||||
IWL_CFG_ANY, IWL_CFG_ANY, IWL_CFG_NO_CDB,
|
||||
iwl_cfg_ma_a0_mr_a0, iwl_ma_name),
|
||||
_IWL_DEV_INFO(IWL_CFG_ANY, IWL_CFG_ANY,
|
||||
IWL_CFG_MAC_TYPE_SNJ, IWL_CFG_ANY,
|
||||
IWL_CFG_RF_TYPE_MR, IWL_CFG_ANY,
|
||||
IWL_CFG_ANY, IWL_CFG_ANY,
|
||||
IWL_CFG_ANY, IWL_CFG_ANY, IWL_CFG_NO_CDB,
|
||||
iwl_cfg_snj_a0_mr_a0, iwl_ma_name),
|
||||
|
||||
/* So with Hr */
|
||||
_IWL_DEV_INFO(IWL_CFG_ANY, IWL_CFG_ANY,
|
||||
IWL_CFG_MAC_TYPE_SO, IWL_CFG_ANY,
|
||||
IWL_CFG_RF_TYPE_HR2, IWL_CFG_ANY,
|
||||
IWL_CFG_NO_160, IWL_CFG_ANY, IWL_CFG_NO_CDB,
|
||||
iwl_cfg_so_a0_hr_a0, iwl_ax203_name),
|
||||
_IWL_DEV_INFO(IWL_CFG_ANY, IWL_CFG_ANY,
|
||||
IWL_CFG_MAC_TYPE_SO, IWL_CFG_ANY,
|
||||
IWL_CFG_RF_TYPE_HR2, IWL_CFG_ANY,
|
||||
IWL_CFG_NO_160, IWL_CFG_ANY, IWL_CFG_NO_CDB,
|
||||
iwl_cfg_so_a0_hr_a0, iwl_ax203_name),
|
||||
_IWL_DEV_INFO(IWL_CFG_ANY, IWL_CFG_ANY,
|
||||
IWL_CFG_MAC_TYPE_SO, IWL_CFG_ANY,
|
||||
IWL_CFG_RF_TYPE_HR1, IWL_CFG_ANY,
|
||||
IWL_CFG_160, IWL_CFG_ANY, IWL_CFG_NO_CDB,
|
||||
iwl_cfg_so_a0_hr_a0, iwl_ax101_name),
|
||||
_IWL_DEV_INFO(IWL_CFG_ANY, IWL_CFG_ANY,
|
||||
IWL_CFG_MAC_TYPE_SO, IWL_CFG_ANY,
|
||||
IWL_CFG_RF_TYPE_HR2, IWL_CFG_ANY,
|
||||
IWL_CFG_160, IWL_CFG_ANY, IWL_CFG_NO_CDB,
|
||||
iwl_cfg_so_a0_hr_a0, iwl_ax201_name)
|
||||
|
||||
#endif /* CONFIG_IWLMVM */
|
||||
};
|
||||
|
@ -1046,6 +1090,8 @@ static int iwl_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
|
|||
(dev_info->rf_type == (u16)IWL_CFG_ANY ||
|
||||
dev_info->rf_type ==
|
||||
CSR_HW_RFID_TYPE(iwl_trans->hw_rf_id)) &&
|
||||
(dev_info->cdb == IWL_CFG_NO_CDB ||
|
||||
CSR_HW_RFID_IS_CDB(iwl_trans->hw_rf_id)) &&
|
||||
(dev_info->rf_id == (u8)IWL_CFG_ANY ||
|
||||
dev_info->rf_id ==
|
||||
IWL_SUBDEVICE_RF_ID(pdev->subsystem_device)) &&
|
||||
|
|
|
@ -834,8 +834,11 @@ err:
|
|||
trans_pcie->base_rb_stts_dma = 0;
|
||||
}
|
||||
kfree(trans_pcie->rx_pool);
|
||||
trans_pcie->rx_pool = NULL;
|
||||
kfree(trans_pcie->global_table);
|
||||
trans_pcie->global_table = NULL;
|
||||
kfree(trans_pcie->rxq);
|
||||
trans_pcie->rxq = NULL;
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
@ -844,7 +847,6 @@ static void iwl_pcie_rx_hw_init(struct iwl_trans *trans, struct iwl_rxq *rxq)
|
|||
{
|
||||
struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
|
||||
u32 rb_size;
|
||||
unsigned long flags;
|
||||
const u32 rfdnlog = RX_QUEUE_SIZE_LOG; /* 256 RBDs */
|
||||
|
||||
switch (trans_pcie->rx_buf_size) {
|
||||
|
@ -862,7 +864,7 @@ static void iwl_pcie_rx_hw_init(struct iwl_trans *trans, struct iwl_rxq *rxq)
|
|||
rb_size = FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_4K;
|
||||
}
|
||||
|
||||
if (!iwl_trans_grab_nic_access(trans, &flags))
|
||||
if (!iwl_trans_grab_nic_access(trans))
|
||||
return;
|
||||
|
||||
/* Stop Rx DMA */
|
||||
|
@ -899,7 +901,7 @@ static void iwl_pcie_rx_hw_init(struct iwl_trans *trans, struct iwl_rxq *rxq)
|
|||
(RX_RB_TIMEOUT << FH_RCSR_RX_CONFIG_REG_IRQ_RBTH_POS) |
|
||||
(rfdnlog << FH_RCSR_RX_CONFIG_RBDCB_SIZE_POS));
|
||||
|
||||
iwl_trans_release_nic_access(trans, &flags);
|
||||
iwl_trans_release_nic_access(trans);
|
||||
|
||||
/* Set interrupt coalescing timer to default (2048 usecs) */
|
||||
iwl_write8(trans, CSR_INT_COALESCING, IWL_HOST_INT_TIMEOUT_DEF);
|
||||
|
@ -913,7 +915,6 @@ static void iwl_pcie_rx_mq_hw_init(struct iwl_trans *trans)
|
|||
{
|
||||
struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
|
||||
u32 rb_size, enabled = 0;
|
||||
unsigned long flags;
|
||||
int i;
|
||||
|
||||
switch (trans_pcie->rx_buf_size) {
|
||||
|
@ -934,7 +935,7 @@ static void iwl_pcie_rx_mq_hw_init(struct iwl_trans *trans)
|
|||
rb_size = RFH_RXF_DMA_RB_SIZE_4K;
|
||||
}
|
||||
|
||||
if (!iwl_trans_grab_nic_access(trans, &flags))
|
||||
if (!iwl_trans_grab_nic_access(trans))
|
||||
return;
|
||||
|
||||
/* Stop Rx DMA */
|
||||
|
@ -992,7 +993,7 @@ static void iwl_pcie_rx_mq_hw_init(struct iwl_trans *trans)
|
|||
/* Enable the relevant rx queues */
|
||||
iwl_write_prph_no_grab(trans, RFH_RXF_RXQ_ACTIVE, enabled);
|
||||
|
||||
iwl_trans_release_nic_access(trans, &flags);
|
||||
iwl_trans_release_nic_access(trans);
|
||||
|
||||
/* Set interrupt coalescing timer to default (2048 usecs) */
|
||||
iwl_write8(trans, CSR_INT_COALESCING, IWL_HOST_INT_TIMEOUT_DEF);
|
||||
|
@ -1657,6 +1658,9 @@ irqreturn_t iwl_pcie_irq_rx_msix_handler(int irq, void *dev_id)
|
|||
if (WARN_ON(entry->entry >= trans->num_rx_queues))
|
||||
return IRQ_NONE;
|
||||
|
||||
if (WARN_ONCE(!rxq, "Got MSI-X interrupt before we have Rx queues"))
|
||||
return IRQ_NONE;
|
||||
|
||||
lock_map_acquire(&trans->sync_cmd_lockdep_map);
|
||||
|
||||
local_bh_disable();
|
||||
|
|
|
@ -10,6 +10,8 @@
|
|||
#include "internal.h"
|
||||
#include "fw/dbg.h"
|
||||
|
||||
#define FW_RESET_TIMEOUT (HZ / 5)
|
||||
|
||||
/*
|
||||
* Start up NIC's basic functionality after it has been reset
|
||||
* (e.g. after platform boot, or shutdown via iwl_pcie_apm_stop())
|
||||
|
@ -104,7 +106,7 @@ static void iwl_trans_pcie_fw_reset_handshake(struct iwl_trans *trans)
|
|||
|
||||
/* wait 200ms */
|
||||
ret = wait_event_timeout(trans_pcie->fw_reset_waitq,
|
||||
trans_pcie->fw_reset_done, HZ / 5);
|
||||
trans_pcie->fw_reset_done, FW_RESET_TIMEOUT);
|
||||
if (!ret)
|
||||
IWL_ERR(trans,
|
||||
"firmware didn't ACK the reset - continue anyway\n");
|
||||
|
@ -198,6 +200,10 @@ void iwl_trans_pcie_gen2_stop_device(struct iwl_trans *trans)
|
|||
struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
|
||||
bool was_in_rfkill;
|
||||
|
||||
iwl_op_mode_time_point(trans->op_mode,
|
||||
IWL_FW_INI_TIME_POINT_HOST_DEVICE_DISABLE,
|
||||
NULL);
|
||||
|
||||
mutex_lock(&trans_pcie->mutex);
|
||||
trans_pcie->opmode_down = true;
|
||||
was_in_rfkill = test_bit(STATUS_RFKILL_OPMODE, &trans->status);
|
||||
|
|
|
@ -523,11 +523,15 @@ static int iwl_pcie_nic_init(struct iwl_trans *trans)
|
|||
iwl_op_mode_nic_config(trans->op_mode);
|
||||
|
||||
/* Allocate the RX queue, or reset if it is already allocated */
|
||||
iwl_pcie_rx_init(trans);
|
||||
ret = iwl_pcie_rx_init(trans);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
/* Allocate or reset and init all Tx and Command queues */
|
||||
if (iwl_pcie_tx_init(trans))
|
||||
if (iwl_pcie_tx_init(trans)) {
|
||||
iwl_pcie_rx_free(trans);
|
||||
return -ENOMEM;
|
||||
}
|
||||
|
||||
if (trans->trans_cfg->base_params->shadow_reg_enable) {
|
||||
/* enable shadow regs in HW */
|
||||
|
@ -636,17 +640,16 @@ static int iwl_pcie_load_firmware_chunk(struct iwl_trans *trans,
|
|||
u32 byte_cnt)
|
||||
{
|
||||
struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
|
||||
unsigned long flags;
|
||||
int ret;
|
||||
|
||||
trans_pcie->ucode_write_complete = false;
|
||||
|
||||
if (!iwl_trans_grab_nic_access(trans, &flags))
|
||||
if (!iwl_trans_grab_nic_access(trans))
|
||||
return -EIO;
|
||||
|
||||
iwl_pcie_load_firmware_chunk_fh(trans, dst_addr, phy_addr,
|
||||
byte_cnt);
|
||||
iwl_trans_release_nic_access(trans, &flags);
|
||||
iwl_trans_release_nic_access(trans);
|
||||
|
||||
ret = wait_event_timeout(trans_pcie->ucode_write_waitq,
|
||||
trans_pcie->ucode_write_complete, 5 * HZ);
|
||||
|
@ -1376,6 +1379,10 @@ static void iwl_trans_pcie_stop_device(struct iwl_trans *trans)
|
|||
struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
|
||||
bool was_in_rfkill;
|
||||
|
||||
iwl_op_mode_time_point(trans->op_mode,
|
||||
IWL_FW_INI_TIME_POINT_HOST_DEVICE_DISABLE,
|
||||
NULL);
|
||||
|
||||
mutex_lock(&trans_pcie->mutex);
|
||||
trans_pcie->opmode_down = true;
|
||||
was_in_rfkill = test_bit(STATUS_RFKILL_OPMODE, &trans->status);
|
||||
|
@ -1966,13 +1973,12 @@ static void iwl_trans_pcie_removal_wk(struct work_struct *wk)
|
|||
module_put(THIS_MODULE);
|
||||
}
|
||||
|
||||
static bool iwl_trans_pcie_grab_nic_access(struct iwl_trans *trans,
|
||||
unsigned long *flags)
|
||||
static bool iwl_trans_pcie_grab_nic_access(struct iwl_trans *trans)
|
||||
{
|
||||
int ret;
|
||||
struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
|
||||
|
||||
spin_lock_irqsave(&trans_pcie->reg_lock, *flags);
|
||||
spin_lock_bh(&trans_pcie->reg_lock);
|
||||
|
||||
if (trans_pcie->cmd_hold_nic_awake)
|
||||
goto out;
|
||||
|
@ -2057,7 +2063,7 @@ static bool iwl_trans_pcie_grab_nic_access(struct iwl_trans *trans,
|
|||
}
|
||||
|
||||
err:
|
||||
spin_unlock_irqrestore(&trans_pcie->reg_lock, *flags);
|
||||
spin_unlock_bh(&trans_pcie->reg_lock);
|
||||
return false;
|
||||
}
|
||||
|
||||
|
@ -2070,8 +2076,7 @@ out:
|
|||
return true;
|
||||
}
|
||||
|
||||
static void iwl_trans_pcie_release_nic_access(struct iwl_trans *trans,
|
||||
unsigned long *flags)
|
||||
static void iwl_trans_pcie_release_nic_access(struct iwl_trans *trans)
|
||||
{
|
||||
struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
|
||||
|
||||
|
@ -2095,13 +2100,12 @@ static void iwl_trans_pcie_release_nic_access(struct iwl_trans *trans,
|
|||
* scheduled on different CPUs (after we drop reg_lock).
|
||||
*/
|
||||
out:
|
||||
spin_unlock_irqrestore(&trans_pcie->reg_lock, *flags);
|
||||
spin_unlock_bh(&trans_pcie->reg_lock);
|
||||
}
|
||||
|
||||
static int iwl_trans_pcie_read_mem(struct iwl_trans *trans, u32 addr,
|
||||
void *buf, int dwords)
|
||||
{
|
||||
unsigned long flags;
|
||||
int offs = 0;
|
||||
u32 *vals = buf;
|
||||
|
||||
|
@ -2110,7 +2114,7 @@ static int iwl_trans_pcie_read_mem(struct iwl_trans *trans, u32 addr,
|
|||
unsigned long end = jiffies + HZ / 2;
|
||||
bool resched = false;
|
||||
|
||||
if (iwl_trans_grab_nic_access(trans, &flags)) {
|
||||
if (iwl_trans_grab_nic_access(trans)) {
|
||||
iwl_write32(trans, HBUS_TARG_MEM_RADDR,
|
||||
addr + 4 * offs);
|
||||
|
||||
|
@ -2124,7 +2128,7 @@ static int iwl_trans_pcie_read_mem(struct iwl_trans *trans, u32 addr,
|
|||
break;
|
||||
}
|
||||
}
|
||||
iwl_trans_release_nic_access(trans, &flags);
|
||||
iwl_trans_release_nic_access(trans);
|
||||
|
||||
if (resched)
|
||||
cond_resched();
|
||||
|
@ -2139,16 +2143,15 @@ static int iwl_trans_pcie_read_mem(struct iwl_trans *trans, u32 addr,
|
|||
static int iwl_trans_pcie_write_mem(struct iwl_trans *trans, u32 addr,
|
||||
const void *buf, int dwords)
|
||||
{
|
||||
unsigned long flags;
|
||||
int offs, ret = 0;
|
||||
const u32 *vals = buf;
|
||||
|
||||
if (iwl_trans_grab_nic_access(trans, &flags)) {
|
||||
if (iwl_trans_grab_nic_access(trans)) {
|
||||
iwl_write32(trans, HBUS_TARG_MEM_WADDR, addr);
|
||||
for (offs = 0; offs < dwords; offs++)
|
||||
iwl_write32(trans, HBUS_TARG_MEM_WDAT,
|
||||
vals ? vals[offs] : 0);
|
||||
iwl_trans_release_nic_access(trans, &flags);
|
||||
iwl_trans_release_nic_access(trans);
|
||||
} else {
|
||||
ret = -EBUSY;
|
||||
}
|
||||
|
@ -2296,11 +2299,10 @@ static void iwl_trans_pcie_set_bits_mask(struct iwl_trans *trans, u32 reg,
|
|||
u32 mask, u32 value)
|
||||
{
|
||||
struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
|
||||
unsigned long flags;
|
||||
|
||||
spin_lock_irqsave(&trans_pcie->reg_lock, flags);
|
||||
spin_lock_bh(&trans_pcie->reg_lock);
|
||||
__iwl_trans_pcie_set_bits_mask(trans, reg, mask, value);
|
||||
spin_unlock_irqrestore(&trans_pcie->reg_lock, flags);
|
||||
spin_unlock_bh(&trans_pcie->reg_lock);
|
||||
}
|
||||
|
||||
static const char *get_csr_string(int cmd)
|
||||
|
@ -2945,11 +2947,10 @@ static u32 iwl_trans_pcie_fh_regs_dump(struct iwl_trans *trans,
|
|||
struct iwl_fw_error_dump_data **data)
|
||||
{
|
||||
u32 fh_regs_len = FH_MEM_UPPER_BOUND - FH_MEM_LOWER_BOUND;
|
||||
unsigned long flags;
|
||||
__le32 *val;
|
||||
int i;
|
||||
|
||||
if (!iwl_trans_grab_nic_access(trans, &flags))
|
||||
if (!iwl_trans_grab_nic_access(trans))
|
||||
return 0;
|
||||
|
||||
(*data)->type = cpu_to_le32(IWL_FW_ERROR_DUMP_FH_REGS);
|
||||
|
@ -2967,7 +2968,7 @@ static u32 iwl_trans_pcie_fh_regs_dump(struct iwl_trans *trans,
|
|||
*val++ = cpu_to_le32(iwl_trans_pcie_read_prph(trans,
|
||||
i));
|
||||
|
||||
iwl_trans_release_nic_access(trans, &flags);
|
||||
iwl_trans_release_nic_access(trans);
|
||||
|
||||
*data = iwl_fw_error_next_data(*data);
|
||||
|
||||
|
@ -2981,10 +2982,9 @@ iwl_trans_pci_dump_marbh_monitor(struct iwl_trans *trans,
|
|||
{
|
||||
u32 buf_size_in_dwords = (monitor_len >> 2);
|
||||
u32 *buffer = (u32 *)fw_mon_data->data;
|
||||
unsigned long flags;
|
||||
u32 i;
|
||||
|
||||
if (!iwl_trans_grab_nic_access(trans, &flags))
|
||||
if (!iwl_trans_grab_nic_access(trans))
|
||||
return 0;
|
||||
|
||||
iwl_write_umac_prph_no_grab(trans, MON_DMARB_RD_CTL_ADDR, 0x1);
|
||||
|
@ -2993,7 +2993,7 @@ iwl_trans_pci_dump_marbh_monitor(struct iwl_trans *trans,
|
|||
MON_DMARB_RD_DATA_ADDR);
|
||||
iwl_write_umac_prph_no_grab(trans, MON_DMARB_RD_CTL_ADDR, 0x0);
|
||||
|
||||
iwl_trans_release_nic_access(trans, &flags);
|
||||
iwl_trans_release_nic_access(trans);
|
||||
|
||||
return monitor_len;
|
||||
}
|
||||
|
|
|
@ -31,7 +31,6 @@ int iwl_pcie_gen2_enqueue_hcmd(struct iwl_trans *trans,
|
|||
struct iwl_txq *txq = trans->txqs.txq[trans->txqs.cmd.q_id];
|
||||
struct iwl_device_cmd *out_cmd;
|
||||
struct iwl_cmd_meta *out_meta;
|
||||
unsigned long flags;
|
||||
void *dup_buf = NULL;
|
||||
dma_addr_t phys_addr;
|
||||
int i, cmd_pos, idx;
|
||||
|
@ -244,11 +243,11 @@ int iwl_pcie_gen2_enqueue_hcmd(struct iwl_trans *trans,
|
|||
if (txq->read_ptr == txq->write_ptr && txq->wd_timeout)
|
||||
mod_timer(&txq->stuck_timer, jiffies + txq->wd_timeout);
|
||||
|
||||
spin_lock_irqsave(&trans_pcie->reg_lock, flags);
|
||||
spin_lock(&trans_pcie->reg_lock);
|
||||
/* Increment and update queue's write index */
|
||||
txq->write_ptr = iwl_txq_inc_wrap(trans, txq->write_ptr);
|
||||
iwl_txq_inc_wr_ptr(trans, txq);
|
||||
spin_unlock_irqrestore(&trans_pcie->reg_lock, flags);
|
||||
spin_unlock(&trans_pcie->reg_lock);
|
||||
|
||||
out:
|
||||
spin_unlock_bh(&txq->lock);
|
||||
|
|
|
@ -223,12 +223,10 @@ static void iwl_pcie_txq_unmap(struct iwl_trans *trans, int txq_id)
|
|||
txq->read_ptr = iwl_txq_inc_wrap(trans, txq->read_ptr);
|
||||
|
||||
if (txq->read_ptr == txq->write_ptr) {
|
||||
unsigned long flags;
|
||||
|
||||
spin_lock_irqsave(&trans_pcie->reg_lock, flags);
|
||||
spin_lock(&trans_pcie->reg_lock);
|
||||
if (txq_id == trans->txqs.cmd.q_id)
|
||||
iwl_pcie_clear_cmd_in_flight(trans);
|
||||
spin_unlock_irqrestore(&trans_pcie->reg_lock, flags);
|
||||
spin_unlock(&trans_pcie->reg_lock);
|
||||
}
|
||||
}
|
||||
|
||||
|
@ -394,13 +392,12 @@ void iwl_trans_pcie_tx_reset(struct iwl_trans *trans)
|
|||
static void iwl_pcie_tx_stop_fh(struct iwl_trans *trans)
|
||||
{
|
||||
struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
|
||||
unsigned long flags;
|
||||
int ch, ret;
|
||||
u32 mask = 0;
|
||||
|
||||
spin_lock_bh(&trans_pcie->irq_lock);
|
||||
|
||||
if (!iwl_trans_grab_nic_access(trans, &flags))
|
||||
if (!iwl_trans_grab_nic_access(trans))
|
||||
goto out;
|
||||
|
||||
/* Stop each Tx DMA channel */
|
||||
|
@ -416,7 +413,7 @@ static void iwl_pcie_tx_stop_fh(struct iwl_trans *trans)
|
|||
"Failing on timeout while stopping DMA channel %d [0x%08x]\n",
|
||||
ch, iwl_read32(trans, FH_TSSR_TX_STATUS_REG));
|
||||
|
||||
iwl_trans_release_nic_access(trans, &flags);
|
||||
iwl_trans_release_nic_access(trans);
|
||||
|
||||
out:
|
||||
spin_unlock_bh(&trans_pcie->irq_lock);
|
||||
|
@ -679,7 +676,6 @@ static void iwl_pcie_cmdq_reclaim(struct iwl_trans *trans, int txq_id, int idx)
|
|||
{
|
||||
struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
|
||||
struct iwl_txq *txq = trans->txqs.txq[txq_id];
|
||||
unsigned long flags;
|
||||
int nfreed = 0;
|
||||
u16 r;
|
||||
|
||||
|
@ -710,9 +706,10 @@ static void iwl_pcie_cmdq_reclaim(struct iwl_trans *trans, int txq_id, int idx)
|
|||
}
|
||||
|
||||
if (txq->read_ptr == txq->write_ptr) {
|
||||
spin_lock_irqsave(&trans_pcie->reg_lock, flags);
|
||||
/* BHs are also disabled due to txq->lock */
|
||||
spin_lock(&trans_pcie->reg_lock);
|
||||
iwl_pcie_clear_cmd_in_flight(trans);
|
||||
spin_unlock_irqrestore(&trans_pcie->reg_lock, flags);
|
||||
spin_unlock(&trans_pcie->reg_lock);
|
||||
}
|
||||
|
||||
iwl_txq_progress(txq);
|
||||
|
@ -921,7 +918,6 @@ int iwl_pcie_enqueue_hcmd(struct iwl_trans *trans,
|
|||
struct iwl_txq *txq = trans->txqs.txq[trans->txqs.cmd.q_id];
|
||||
struct iwl_device_cmd *out_cmd;
|
||||
struct iwl_cmd_meta *out_meta;
|
||||
unsigned long flags;
|
||||
void *dup_buf = NULL;
|
||||
dma_addr_t phys_addr;
|
||||
int idx;
|
||||
|
@ -1164,20 +1160,19 @@ int iwl_pcie_enqueue_hcmd(struct iwl_trans *trans,
|
|||
if (txq->read_ptr == txq->write_ptr && txq->wd_timeout)
|
||||
mod_timer(&txq->stuck_timer, jiffies + txq->wd_timeout);
|
||||
|
||||
spin_lock_irqsave(&trans_pcie->reg_lock, flags);
|
||||
spin_lock(&trans_pcie->reg_lock);
|
||||
ret = iwl_pcie_set_cmd_in_flight(trans, cmd);
|
||||
if (ret < 0) {
|
||||
idx = ret;
|
||||
spin_unlock_irqrestore(&trans_pcie->reg_lock, flags);
|
||||
goto out;
|
||||
goto unlock_reg;
|
||||
}
|
||||
|
||||
/* Increment and update queue's write index */
|
||||
txq->write_ptr = iwl_txq_inc_wrap(trans, txq->write_ptr);
|
||||
iwl_pcie_txq_inc_wr_ptr(trans, txq);
|
||||
|
||||
spin_unlock_irqrestore(&trans_pcie->reg_lock, flags);
|
||||
|
||||
unlock_reg:
|
||||
spin_unlock(&trans_pcie->reg_lock);
|
||||
out:
|
||||
spin_unlock_bh(&txq->lock);
|
||||
free_dup_buf:
|
||||
|
|
|
@ -1577,6 +1577,10 @@ void iwl_txq_reclaim(struct iwl_trans *trans, int txq_id, int ssn,
|
|||
__func__, txq_id, last_to_free,
|
||||
trans->trans_cfg->base_params->max_tfd_queue_size,
|
||||
txq->write_ptr, txq->read_ptr);
|
||||
|
||||
iwl_op_mode_time_point(trans->op_mode,
|
||||
IWL_FW_INI_TIME_POINT_FAKE_TX,
|
||||
NULL);
|
||||
goto out;
|
||||
}
|
||||
|
||||
|
|
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