phy: mediatek: hdmi: mt8173: use FIELD_PREP to prepare bits field
Use FIELD_PREP() macro to prepare bits field value, then no need define macros of bits offset. Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Link: https://lore.kernel.org/r/20220920090038.15133-11-chunfeng.yun@mediatek.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
This commit is contained in:
Chunfeng Yun
Vinod Koul
Родитель
a8a78274c6
Коммит
309b4fec53
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@ -9,27 +9,17 @@
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#define HDMI_CON0 0x00
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#define RG_HDMITX_PLL_EN BIT(31)
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#define RG_HDMITX_PLL_FBKDIV GENMASK(30, 24)
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#define PLL_FBKDIV_SHIFT 24
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#define RG_HDMITX_PLL_FBKSEL GENMASK(23, 22)
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#define PLL_FBKSEL_SHIFT 22
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#define RG_HDMITX_PLL_PREDIV GENMASK(21, 20)
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#define PREDIV_SHIFT 20
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#define RG_HDMITX_PLL_POSDIV GENMASK(19, 18)
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#define POSDIV_SHIFT 18
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#define RG_HDMITX_PLL_RST_DLY GENMASK(17, 16)
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#define RG_HDMITX_PLL_IR GENMASK(15, 12)
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#define PLL_IR_SHIFT 12
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#define RG_HDMITX_PLL_IC GENMASK(11, 8)
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#define PLL_IC_SHIFT 8
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#define RG_HDMITX_PLL_BP GENMASK(7, 4)
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#define PLL_BP_SHIFT 4
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#define RG_HDMITX_PLL_BR GENMASK(3, 2)
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#define PLL_BR_SHIFT 2
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#define RG_HDMITX_PLL_BC GENMASK(1, 0)
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#define PLL_BC_SHIFT 0
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#define HDMI_CON1 0x04
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#define RG_HDMITX_PLL_DIVEN GENMASK(31, 29)
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#define PLL_DIVEN_SHIFT 29
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#define RG_HDMITX_PLL_AUTOK_EN BIT(28)
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#define RG_HDMITX_PLL_AUTOK_KF GENMASK(27, 26)
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#define RG_HDMITX_PLL_AUTOK_KS GENMASK(25, 24)
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@ -40,7 +30,6 @@
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#define RG_HDMITX_PLL_BIAS_LPF_EN BIT(13)
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#define RG_HDMITX_PLL_TXDIV_EN BIT(12)
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#define RG_HDMITX_PLL_TXDIV GENMASK(11, 10)
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#define PLL_TXDIV_SHIFT 10
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#define RG_HDMITX_PLL_LVROD_EN BIT(9)
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#define RG_HDMITX_PLL_MONVC_EN BIT(8)
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#define RG_HDMITX_PLL_MONCK_EN BIT(7)
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@ -58,7 +47,6 @@
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#define RG_HDMITX_PRD_IMP_EN GENMASK(23, 20)
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#define RG_HDMITX_DRV_EN GENMASK(19, 16)
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#define RG_HDMITX_DRV_IMP_EN GENMASK(15, 12)
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#define DRV_IMP_EN_SHIFT 12
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#define RG_HDMITX_MHLCK_FORCE BIT(10)
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#define RG_HDMITX_MHLCK_PPIX_EN BIT(9)
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#define RG_HDMITX_MHLCK_EN BIT(8)
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@ -72,28 +60,16 @@
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#define RG_HDMITX_PRD_IBIAS_D2 GENMASK(19, 16)
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#define RG_HDMITX_PRD_IBIAS_D1 GENMASK(11, 8)
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#define RG_HDMITX_PRD_IBIAS_D0 GENMASK(3, 0)
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#define PRD_IBIAS_CLK_SHIFT 24
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#define PRD_IBIAS_D2_SHIFT 16
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#define PRD_IBIAS_D1_SHIFT 8
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#define PRD_IBIAS_D0_SHIFT 0
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#define HDMI_CON5 0x14
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#define RG_HDMITX_DRV_IBIAS_CLK GENMASK(29, 24)
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#define RG_HDMITX_DRV_IBIAS_D2 GENMASK(21, 16)
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#define RG_HDMITX_DRV_IBIAS_D1 GENMASK(13, 8)
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#define RG_HDMITX_DRV_IBIAS_D0 GENMASK(5, 0)
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#define DRV_IBIAS_CLK_SHIFT 24
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#define DRV_IBIAS_D2_SHIFT 16
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#define DRV_IBIAS_D1_SHIFT 8
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#define DRV_IBIAS_D0_SHIFT 0
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#define HDMI_CON6 0x18
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#define RG_HDMITX_DRV_IMP_CLK GENMASK(29, 24)
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#define RG_HDMITX_DRV_IMP_D2 GENMASK(21, 16)
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#define RG_HDMITX_DRV_IMP_D1 GENMASK(13, 8)
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#define RG_HDMITX_DRV_IMP_D0 GENMASK(5, 0)
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#define DRV_IMP_CLK_SHIFT 24
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#define DRV_IMP_D2_SHIFT 16
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#define DRV_IMP_D1_SHIFT 8
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#define DRV_IMP_D0_SHIFT 0
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#define HDMI_CON7 0x1c
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#define RG_HDMITX_MHLCK_DRV_IBIAS GENMASK(31, 27)
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#define RG_HDMITX_SER_DIN GENMASK(25, 16)
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@ -178,21 +154,27 @@ static int mtk_hdmi_pll_set_rate(struct clk_hw *hw, unsigned long rate,
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}
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mtk_hdmi_phy_mask(hdmi_phy, HDMI_CON0,
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(pre_div << PREDIV_SHIFT), RG_HDMITX_PLL_PREDIV);
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FIELD_PREP(RG_HDMITX_PLL_PREDIV, pre_div),
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RG_HDMITX_PLL_PREDIV);
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mtk_hdmi_phy_set_bits(hdmi_phy, HDMI_CON0, RG_HDMITX_PLL_POSDIV);
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mtk_hdmi_phy_mask(hdmi_phy, HDMI_CON0,
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(0x1 << PLL_IC_SHIFT) | (0x1 << PLL_IR_SHIFT),
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FIELD_PREP(RG_HDMITX_PLL_IC, 0x1) |
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FIELD_PREP(RG_HDMITX_PLL_IR, 0x1),
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RG_HDMITX_PLL_IC | RG_HDMITX_PLL_IR);
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mtk_hdmi_phy_mask(hdmi_phy, HDMI_CON1,
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(div << PLL_TXDIV_SHIFT), RG_HDMITX_PLL_TXDIV);
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FIELD_PREP(RG_HDMITX_PLL_TXDIV, div),
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RG_HDMITX_PLL_TXDIV);
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mtk_hdmi_phy_mask(hdmi_phy, HDMI_CON0,
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(0x1 << PLL_FBKSEL_SHIFT) | (19 << PLL_FBKDIV_SHIFT),
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FIELD_PREP(RG_HDMITX_PLL_FBKSEL, 0x1) |
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FIELD_PREP(RG_HDMITX_PLL_FBKDIV, 19),
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RG_HDMITX_PLL_FBKSEL | RG_HDMITX_PLL_FBKDIV);
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mtk_hdmi_phy_mask(hdmi_phy, HDMI_CON1,
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(0x2 << PLL_DIVEN_SHIFT), RG_HDMITX_PLL_DIVEN);
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FIELD_PREP(RG_HDMITX_PLL_DIVEN, 0x2),
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RG_HDMITX_PLL_DIVEN);
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mtk_hdmi_phy_mask(hdmi_phy, HDMI_CON0,
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(0xc << PLL_BP_SHIFT) | (0x2 << PLL_BC_SHIFT) |
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(0x1 << PLL_BR_SHIFT),
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FIELD_PREP(RG_HDMITX_PLL_BP, 0xc) |
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FIELD_PREP(RG_HDMITX_PLL_BC, 0x2) |
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FIELD_PREP(RG_HDMITX_PLL_BR, 0x1),
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RG_HDMITX_PLL_BP | RG_HDMITX_PLL_BC |
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RG_HDMITX_PLL_BR);
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if (rate < 165000000) {
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@ -209,29 +191,29 @@ static int mtk_hdmi_pll_set_rate(struct clk_hw *hw, unsigned long rate,
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hdmi_ibias = hdmi_phy->ibias_up;
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}
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mtk_hdmi_phy_mask(hdmi_phy, HDMI_CON4,
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(pre_ibias << PRD_IBIAS_CLK_SHIFT) |
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(pre_ibias << PRD_IBIAS_D2_SHIFT) |
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(pre_ibias << PRD_IBIAS_D1_SHIFT) |
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(pre_ibias << PRD_IBIAS_D0_SHIFT),
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FIELD_PREP(RG_HDMITX_PRD_IBIAS_CLK, pre_ibias) |
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FIELD_PREP(RG_HDMITX_PRD_IBIAS_D2, pre_ibias) |
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FIELD_PREP(RG_HDMITX_PRD_IBIAS_D1, pre_ibias) |
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FIELD_PREP(RG_HDMITX_PRD_IBIAS_D0, pre_ibias),
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RG_HDMITX_PRD_IBIAS_CLK |
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RG_HDMITX_PRD_IBIAS_D2 |
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RG_HDMITX_PRD_IBIAS_D1 |
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RG_HDMITX_PRD_IBIAS_D0);
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mtk_hdmi_phy_mask(hdmi_phy, HDMI_CON3,
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(imp_en << DRV_IMP_EN_SHIFT),
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FIELD_PREP(RG_HDMITX_DRV_IMP_EN, imp_en),
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RG_HDMITX_DRV_IMP_EN);
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mtk_hdmi_phy_mask(hdmi_phy, HDMI_CON6,
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(hdmi_phy->drv_imp_clk << DRV_IMP_CLK_SHIFT) |
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(hdmi_phy->drv_imp_d2 << DRV_IMP_D2_SHIFT) |
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(hdmi_phy->drv_imp_d1 << DRV_IMP_D1_SHIFT) |
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(hdmi_phy->drv_imp_d0 << DRV_IMP_D0_SHIFT),
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FIELD_PREP(RG_HDMITX_DRV_IMP_CLK, hdmi_phy->drv_imp_clk) |
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FIELD_PREP(RG_HDMITX_DRV_IMP_D2, hdmi_phy->drv_imp_d2) |
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FIELD_PREP(RG_HDMITX_DRV_IMP_D1, hdmi_phy->drv_imp_d1) |
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FIELD_PREP(RG_HDMITX_DRV_IMP_D0, hdmi_phy->drv_imp_d0),
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RG_HDMITX_DRV_IMP_CLK | RG_HDMITX_DRV_IMP_D2 |
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RG_HDMITX_DRV_IMP_D1 | RG_HDMITX_DRV_IMP_D0);
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mtk_hdmi_phy_mask(hdmi_phy, HDMI_CON5,
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(hdmi_ibias << DRV_IBIAS_CLK_SHIFT) |
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(hdmi_ibias << DRV_IBIAS_D2_SHIFT) |
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(hdmi_ibias << DRV_IBIAS_D1_SHIFT) |
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(hdmi_ibias << DRV_IBIAS_D0_SHIFT),
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FIELD_PREP(RG_HDMITX_DRV_IBIAS_CLK, hdmi_ibias) |
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FIELD_PREP(RG_HDMITX_DRV_IBIAS_D2, hdmi_ibias) |
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FIELD_PREP(RG_HDMITX_DRV_IBIAS_D1, hdmi_ibias) |
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FIELD_PREP(RG_HDMITX_DRV_IBIAS_D0, hdmi_ibias),
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RG_HDMITX_DRV_IBIAS_CLK |
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RG_HDMITX_DRV_IBIAS_D2 |
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RG_HDMITX_DRV_IBIAS_D1 |
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