rt2x00: Fix Descriptor DMA initialization
As Adam Baker reported the DMA address for the descriptor base was incorrectly initialized in the PCI drivers. Instead of the DMA base for the descriptor, the DMA base for the data was passed resulting in a broken TX/RX state for PCI drivers. Signed-off-by: Ivo van Doorn <IvDoorn@gmail.com> Signed-off-by: John W. Linville <linville@tuxdriver.com>
This commit is contained in:
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e542239f63
Коммит
30b3a23c25
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@ -597,11 +597,12 @@ static void rt2400pci_init_rxentry(struct rt2x00_dev *rt2x00dev,
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u32 word;
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rt2x00_desc_read(priv_rx->desc, 2, &word);
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rt2x00_set_field32(&word, RXD_W2_BUFFER_LENGTH, entry->queue->data_size);
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rt2x00_set_field32(&word, RXD_W2_BUFFER_LENGTH,
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entry->queue->data_size);
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rt2x00_desc_write(priv_rx->desc, 2, word);
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rt2x00_desc_read(priv_rx->desc, 1, &word);
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rt2x00_set_field32(&word, RXD_W1_BUFFER_ADDRESS, priv_rx->dma);
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rt2x00_set_field32(&word, RXD_W1_BUFFER_ADDRESS, priv_rx->data_dma);
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rt2x00_desc_write(priv_rx->desc, 1, word);
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rt2x00_desc_read(priv_rx->desc, 0, &word);
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@ -616,7 +617,7 @@ static void rt2400pci_init_txentry(struct rt2x00_dev *rt2x00dev,
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u32 word;
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rt2x00_desc_read(priv_tx->desc, 1, &word);
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rt2x00_set_field32(&word, TXD_W1_BUFFER_ADDRESS, priv_tx->dma);
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rt2x00_set_field32(&word, TXD_W1_BUFFER_ADDRESS, priv_tx->data_dma);
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rt2x00_desc_write(priv_tx->desc, 1, word);
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rt2x00_desc_read(priv_tx->desc, 2, &word);
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@ -648,22 +649,26 @@ static int rt2400pci_init_queues(struct rt2x00_dev *rt2x00dev)
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priv_tx = rt2x00dev->tx[1].entries[0].priv_data;
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rt2x00pci_register_read(rt2x00dev, TXCSR3, ®);
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rt2x00_set_field32(®, TXCSR3_TX_RING_REGISTER, priv_tx->dma);
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rt2x00_set_field32(®, TXCSR3_TX_RING_REGISTER,
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priv_tx->desc_dma);
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rt2x00pci_register_write(rt2x00dev, TXCSR3, reg);
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priv_tx = rt2x00dev->tx[0].entries[0].priv_data;
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rt2x00pci_register_read(rt2x00dev, TXCSR5, ®);
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rt2x00_set_field32(®, TXCSR5_PRIO_RING_REGISTER, priv_tx->dma);
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rt2x00_set_field32(®, TXCSR5_PRIO_RING_REGISTER,
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priv_tx->desc_dma);
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rt2x00pci_register_write(rt2x00dev, TXCSR5, reg);
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priv_tx = rt2x00dev->bcn[1].entries[0].priv_data;
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rt2x00pci_register_read(rt2x00dev, TXCSR4, ®);
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rt2x00_set_field32(®, TXCSR4_ATIM_RING_REGISTER, priv_tx->dma);
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rt2x00_set_field32(®, TXCSR4_ATIM_RING_REGISTER,
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priv_tx->desc_dma);
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rt2x00pci_register_write(rt2x00dev, TXCSR4, reg);
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priv_tx = rt2x00dev->bcn[0].entries[0].priv_data;
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rt2x00pci_register_read(rt2x00dev, TXCSR6, ®);
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rt2x00_set_field32(®, TXCSR6_BEACON_RING_REGISTER, priv_tx->dma);
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rt2x00_set_field32(®, TXCSR6_BEACON_RING_REGISTER,
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priv_tx->desc_dma);
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rt2x00pci_register_write(rt2x00dev, TXCSR6, reg);
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rt2x00pci_register_read(rt2x00dev, RXCSR1, ®);
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@ -673,7 +678,7 @@ static int rt2400pci_init_queues(struct rt2x00_dev *rt2x00dev)
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priv_rx = rt2x00dev->rx->entries[0].priv_data;
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rt2x00pci_register_read(rt2x00dev, RXCSR2, ®);
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rt2x00_set_field32(®, RXCSR2_RX_RING_REGISTER, priv_tx->dma);
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rt2x00_set_field32(®, RXCSR2_RX_RING_REGISTER, priv_tx->desc_dma);
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rt2x00pci_register_write(rt2x00dev, RXCSR2, reg);
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return 0;
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@ -691,7 +691,7 @@ static void rt2500pci_init_rxentry(struct rt2x00_dev *rt2x00dev,
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u32 word;
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rt2x00_desc_read(priv_rx->desc, 1, &word);
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rt2x00_set_field32(&word, RXD_W1_BUFFER_ADDRESS, priv_rx->dma);
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rt2x00_set_field32(&word, RXD_W1_BUFFER_ADDRESS, priv_rx->data_dma);
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rt2x00_desc_write(priv_rx->desc, 1, word);
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rt2x00_desc_read(priv_rx->desc, 0, &word);
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@ -706,7 +706,7 @@ static void rt2500pci_init_txentry(struct rt2x00_dev *rt2x00dev,
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u32 word;
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rt2x00_desc_read(priv_tx->desc, 1, &word);
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rt2x00_set_field32(&word, TXD_W1_BUFFER_ADDRESS, priv_tx->dma);
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rt2x00_set_field32(&word, TXD_W1_BUFFER_ADDRESS, priv_tx->data_dma);
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rt2x00_desc_write(priv_tx->desc, 1, word);
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rt2x00_desc_read(priv_tx->desc, 0, &word);
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@ -733,22 +733,26 @@ static int rt2500pci_init_queues(struct rt2x00_dev *rt2x00dev)
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priv_tx = rt2x00dev->tx[1].entries[0].priv_data;
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rt2x00pci_register_read(rt2x00dev, TXCSR3, ®);
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rt2x00_set_field32(®, TXCSR3_TX_RING_REGISTER, priv_tx->dma);
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rt2x00_set_field32(®, TXCSR3_TX_RING_REGISTER,
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priv_tx->desc_dma);
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rt2x00pci_register_write(rt2x00dev, TXCSR3, reg);
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priv_tx = rt2x00dev->tx[0].entries[0].priv_data;
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rt2x00pci_register_read(rt2x00dev, TXCSR5, ®);
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rt2x00_set_field32(®, TXCSR5_PRIO_RING_REGISTER, priv_tx->dma);
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rt2x00_set_field32(®, TXCSR5_PRIO_RING_REGISTER,
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priv_tx->desc_dma);
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rt2x00pci_register_write(rt2x00dev, TXCSR5, reg);
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priv_tx = rt2x00dev->bcn[1].entries[0].priv_data;
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rt2x00pci_register_read(rt2x00dev, TXCSR4, ®);
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rt2x00_set_field32(®, TXCSR4_ATIM_RING_REGISTER, priv_tx->dma);
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rt2x00_set_field32(®, TXCSR4_ATIM_RING_REGISTER,
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priv_tx->desc_dma);
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rt2x00pci_register_write(rt2x00dev, TXCSR4, reg);
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priv_tx = rt2x00dev->bcn[0].entries[0].priv_data;
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rt2x00pci_register_read(rt2x00dev, TXCSR6, ®);
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rt2x00_set_field32(®, TXCSR6_BEACON_RING_REGISTER, priv_tx->dma);
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rt2x00_set_field32(®, TXCSR6_BEACON_RING_REGISTER,
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priv_tx->desc_dma);
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rt2x00pci_register_write(rt2x00dev, TXCSR6, reg);
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rt2x00pci_register_read(rt2x00dev, RXCSR1, ®);
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@ -758,7 +762,7 @@ static int rt2500pci_init_queues(struct rt2x00_dev *rt2x00dev)
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priv_rx = rt2x00dev->rx->entries[0].priv_data;
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rt2x00pci_register_read(rt2x00dev, RXCSR2, ®);
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rt2x00_set_field32(®, RXCSR2_RX_RING_REGISTER, priv_tx->dma);
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rt2x00_set_field32(®, RXCSR2_RX_RING_REGISTER, priv_tx->desc_dma);
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rt2x00pci_register_write(rt2x00dev, RXCSR2, reg);
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return 0;
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@ -218,40 +218,44 @@ static int rt2x00pci_alloc_queue_dma(struct rt2x00_dev *rt2x00dev,
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struct pci_dev *pci_dev = rt2x00dev_pci(rt2x00dev);
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struct queue_entry_priv_pci_rx *priv_rx;
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struct queue_entry_priv_pci_tx *priv_tx;
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void *desc;
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void *data_addr;
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void *data;
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dma_addr_t data_dma;
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void *addr;
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dma_addr_t dma;
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void *desc_addr;
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dma_addr_t desc_dma;
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void *data_addr;
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dma_addr_t data_dma;
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unsigned int i;
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/*
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* Allocate DMA memory for descriptor and buffer.
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*/
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data_addr = pci_alloc_consistent(pci_dev, dma_size(queue), &data_dma);
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if (!data_addr)
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addr = pci_alloc_consistent(pci_dev, dma_size(queue), &dma);
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if (!addr)
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return -ENOMEM;
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memset(data_addr, 0, dma_size(queue));
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memset(addr, 0, dma_size(queue));
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/*
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* Initialize all queue entries to contain valid addresses.
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*/
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for (i = 0; i < queue->limit; i++) {
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desc = desc_offset(queue, data_addr, i);
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data = data_offset(queue, data_addr, i);
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dma = data_offset(queue, data_dma, i);
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desc_addr = desc_offset(queue, addr, i);
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desc_dma = desc_offset(queue, dma, i);
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data_addr = data_offset(queue, addr, i);
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data_dma = data_offset(queue, dma, i);
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if (queue->qid == QID_RX) {
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priv_rx = queue->entries[i].priv_data;
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priv_rx->desc = desc;
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priv_rx->data = data;
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priv_rx->dma = dma;
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priv_rx->desc = desc_addr;
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priv_rx->desc_dma = desc_dma;
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priv_rx->data = data_addr;
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priv_rx->data_dma = data_dma;
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} else {
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priv_tx = queue->entries[i].priv_data;
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priv_tx->desc = desc;
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priv_tx->data = data;
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priv_tx->dma = dma;
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priv_tx->desc = desc_addr;
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priv_tx->desc_dma = desc_dma;
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priv_tx->data = data_addr;
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priv_tx->data_dma = data_dma;
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}
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}
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@ -270,13 +274,13 @@ static void rt2x00pci_free_queue_dma(struct rt2x00_dev *rt2x00dev,
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if (queue->qid == QID_RX) {
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priv_rx = queue->entries[0].priv_data;
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data_addr = priv_rx->data;
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data_dma = priv_rx->dma;
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data_dma = priv_rx->data_dma;
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priv_rx->data = NULL;
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} else {
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priv_tx = queue->entries[0].priv_data;
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data_addr = priv_tx->data;
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data_dma = priv_tx->dma;
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data_dma = priv_tx->data_dma;
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priv_tx->data = NULL;
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}
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@ -103,9 +103,10 @@ int rt2x00pci_write_tx_data(struct rt2x00_dev *rt2x00dev,
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*/
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struct queue_entry_priv_pci_rx {
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__le32 *desc;
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dma_addr_t desc_dma;
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void *data;
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dma_addr_t dma;
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dma_addr_t data_dma;
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};
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/**
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@ -118,9 +119,10 @@ struct queue_entry_priv_pci_rx {
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*/
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struct queue_entry_priv_pci_tx {
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__le32 *desc;
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dma_addr_t desc_dma;
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void *data;
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dma_addr_t dma;
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dma_addr_t data_dma;
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struct ieee80211_tx_control control;
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};
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@ -975,7 +975,8 @@ static void rt61pci_init_rxentry(struct rt2x00_dev *rt2x00dev,
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u32 word;
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rt2x00_desc_read(priv_rx->desc, 5, &word);
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rt2x00_set_field32(&word, RXD_W5_BUFFER_PHYSICAL_ADDRESS, priv_rx->dma);
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rt2x00_set_field32(&word, RXD_W5_BUFFER_PHYSICAL_ADDRESS,
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priv_rx->data_dma);
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rt2x00_desc_write(priv_rx->desc, 5, word);
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rt2x00_desc_read(priv_rx->desc, 0, &word);
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@ -999,7 +1000,8 @@ static void rt61pci_init_txentry(struct rt2x00_dev *rt2x00dev,
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rt2x00_desc_write(priv_tx->desc, 5, word);
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rt2x00_desc_read(priv_tx->desc, 6, &word);
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rt2x00_set_field32(&word, TXD_W6_BUFFER_PHYSICAL_ADDRESS, priv_tx->dma);
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rt2x00_set_field32(&word, TXD_W6_BUFFER_PHYSICAL_ADDRESS,
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priv_tx->data_dma);
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rt2x00_desc_write(priv_tx->desc, 6, word);
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rt2x00_desc_read(priv_tx->desc, 0, &word);
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@ -1035,22 +1037,26 @@ static int rt61pci_init_queues(struct rt2x00_dev *rt2x00dev)
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priv_tx = rt2x00dev->tx[0].entries[0].priv_data;
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rt2x00pci_register_read(rt2x00dev, AC0_BASE_CSR, ®);
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rt2x00_set_field32(®, AC0_BASE_CSR_RING_REGISTER, priv_tx->dma);
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rt2x00_set_field32(®, AC0_BASE_CSR_RING_REGISTER,
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priv_tx->desc_dma);
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rt2x00pci_register_write(rt2x00dev, AC0_BASE_CSR, reg);
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priv_tx = rt2x00dev->tx[1].entries[0].priv_data;
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rt2x00pci_register_read(rt2x00dev, AC1_BASE_CSR, ®);
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rt2x00_set_field32(®, AC1_BASE_CSR_RING_REGISTER, priv_tx->dma);
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rt2x00_set_field32(®, AC1_BASE_CSR_RING_REGISTER,
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priv_tx->desc_dma);
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rt2x00pci_register_write(rt2x00dev, AC1_BASE_CSR, reg);
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priv_tx = rt2x00dev->tx[2].entries[0].priv_data;
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rt2x00pci_register_read(rt2x00dev, AC2_BASE_CSR, ®);
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rt2x00_set_field32(®, AC2_BASE_CSR_RING_REGISTER, priv_tx->dma);
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rt2x00_set_field32(®, AC2_BASE_CSR_RING_REGISTER,
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priv_tx->desc_dma);
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rt2x00pci_register_write(rt2x00dev, AC2_BASE_CSR, reg);
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priv_tx = rt2x00dev->tx[3].entries[0].priv_data;
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rt2x00pci_register_read(rt2x00dev, AC3_BASE_CSR, ®);
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rt2x00_set_field32(®, AC3_BASE_CSR_RING_REGISTER, priv_tx->dma);
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rt2x00_set_field32(®, AC3_BASE_CSR_RING_REGISTER,
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priv_tx->desc_dma);
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rt2x00pci_register_write(rt2x00dev, AC3_BASE_CSR, reg);
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rt2x00pci_register_read(rt2x00dev, RX_RING_CSR, ®);
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@ -1062,7 +1068,8 @@ static int rt61pci_init_queues(struct rt2x00_dev *rt2x00dev)
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priv_rx = rt2x00dev->rx->entries[0].priv_data;
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rt2x00pci_register_read(rt2x00dev, RX_BASE_CSR, ®);
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rt2x00_set_field32(®, RX_BASE_CSR_RING_REGISTER, priv_rx->dma);
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rt2x00_set_field32(®, RX_BASE_CSR_RING_REGISTER,
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priv_rx->desc_dma);
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rt2x00pci_register_write(rt2x00dev, RX_BASE_CSR, reg);
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rt2x00pci_register_read(rt2x00dev, TX_DMA_DST_CSR, ®);
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