Merge remote-tracking branches 'spi/topic/sirf', 'spi/topic/spidev', 'spi/topic/st-ssc' and 'spi/topic/ti-qspi' into spi-next
This commit is contained in:
Коммит
30b9278bf5
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@ -0,0 +1,41 @@
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* CSR SiRFprimaII Serial Peripheral Interface
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Required properties:
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- compatible : Should be "sirf,prima2-spi"
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- reg : Offset and length of the register set for the device
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- interrupts : Should contain SPI interrupt
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- resets: phandle to the reset controller asserting this device in
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reset
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See ../reset/reset.txt for details.
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- dmas : Must contain an entry for each entry in clock-names.
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See ../dma/dma.txt for details.
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- dma-names : Must include the following entries:
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- rx
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- tx
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- clocks : Must contain an entry for each entry in clock-names.
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See ../clocks/clock-bindings.txt for details.
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- #address-cells: Number of cells required to define a chip select
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address on the SPI bus. Should be set to 1.
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- #size-cells: Should be zero.
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Optional properties:
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- spi-max-frequency: Specifies maximum SPI clock frequency,
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Units - Hz. Definition as per
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Documentation/devicetree/bindings/spi/spi-bus.txt
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- cs-gpios: should specify GPIOs used for chipselects.
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Example:
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spi0: spi@b00d0000 {
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compatible = "sirf,prima2-spi";
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reg = <0xb00d0000 0x10000>;
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interrupts = <15>;
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dmas = <&dmac1 9>,
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<&dmac1 4>;
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dma-names = "rx", "tx";
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#address-cells = <1>;
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#size-cells = <0>;
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clocks = <&clks 19>;
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resets = <&rstc 26>;
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};
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@ -0,0 +1,40 @@
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STMicroelectronics SSC (SPI) Controller
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---------------------------------------
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Required properties:
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- compatible : "st,comms-ssc4-spi"
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- reg : Offset and length of the device's register set
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- interrupts : The interrupt specifier
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- clock-names : Must contain "ssc"
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- clocks : Must contain an entry for each name in clock-names
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See ../clk/*
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- pinctrl-names : Uses "default", can use "sleep" if provided
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See ../pinctrl/pinctrl-binding.txt
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Optional properties:
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- cs-gpios : List of GPIO chip selects
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See ../spi/spi-bus.txt
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Child nodes represent devices on the SPI bus
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See ../spi/spi-bus.txt
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Example:
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spi@9840000 {
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compatible = "st,comms-ssc4-spi";
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reg = <0x9840000 0x110>;
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interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>;
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clock-names = "ssc";
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pinctrl-0 = <&pinctrl_spi0_default>;
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pinctrl-names = "default";
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cs-gpios = <&pio17 5 0>;
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#address-cells = <1>;
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#size-cells = <0>;
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st95hf@0{
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compatible = "st,st95hf";
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reg = <0>;
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spi-max-frequency = <1000000>;
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interrupts = <2 IRQ_TYPE_EDGE_FALLING>;
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};
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};
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@ -511,6 +511,13 @@ config SPI_SIRF
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help
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help
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SPI driver for CSR SiRFprimaII SoCs
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SPI driver for CSR SiRFprimaII SoCs
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config SPI_ST_SSC4
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tristate "STMicroelectronics SPI SSC-based driver"
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depends on ARCH_STI
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help
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STMicroelectronics SoCs support for SPI. If you say yes to
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this option, support will be included for the SSC driven SPI.
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config SPI_SUN4I
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config SPI_SUN4I
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tristate "Allwinner A10 SoCs SPI controller"
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tristate "Allwinner A10 SoCs SPI controller"
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depends on ARCH_SUNXI || COMPILE_TEST
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depends on ARCH_SUNXI || COMPILE_TEST
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@ -77,6 +77,7 @@ obj-$(CONFIG_SPI_SH_HSPI) += spi-sh-hspi.o
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obj-$(CONFIG_SPI_SH_MSIOF) += spi-sh-msiof.o
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obj-$(CONFIG_SPI_SH_MSIOF) += spi-sh-msiof.o
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obj-$(CONFIG_SPI_SH_SCI) += spi-sh-sci.o
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obj-$(CONFIG_SPI_SH_SCI) += spi-sh-sci.o
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obj-$(CONFIG_SPI_SIRF) += spi-sirf.o
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obj-$(CONFIG_SPI_SIRF) += spi-sirf.o
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obj-$(CONFIG_SPI_ST_SSC4) += spi-st-ssc4.o
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obj-$(CONFIG_SPI_SUN4I) += spi-sun4i.o
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obj-$(CONFIG_SPI_SUN4I) += spi-sun4i.o
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obj-$(CONFIG_SPI_SUN6I) += spi-sun6i.o
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obj-$(CONFIG_SPI_SUN6I) += spi-sun6i.o
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obj-$(CONFIG_SPI_TEGRA114) += spi-tegra114.o
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obj-$(CONFIG_SPI_TEGRA114) += spi-tegra114.o
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@ -818,7 +818,6 @@ static SIMPLE_DEV_PM_OPS(spi_sirfsoc_pm_ops, spi_sirfsoc_suspend,
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static const struct of_device_id spi_sirfsoc_of_match[] = {
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static const struct of_device_id spi_sirfsoc_of_match[] = {
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{ .compatible = "sirf,prima2-spi", },
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{ .compatible = "sirf,prima2-spi", },
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{ .compatible = "sirf,marco-spi", },
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{}
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{}
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};
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};
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MODULE_DEVICE_TABLE(of, spi_sirfsoc_of_match);
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MODULE_DEVICE_TABLE(of, spi_sirfsoc_of_match);
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@ -0,0 +1,504 @@
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/*
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* Copyright (c) 2008-2014 STMicroelectronics Limited
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*
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* Author: Angus Clark <Angus.Clark@st.com>
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* Patrice Chotard <patrice.chotard@st.com>
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* Lee Jones <lee.jones@linaro.org>
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*
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* SPI master mode controller driver, used in STMicroelectronics devices.
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*
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* May be copied or modified under the terms of the GNU General Public
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* License Version 2.0 only. See linux/COPYING for more information.
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*/
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#include <linux/clk.h>
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#include <linux/delay.h>
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#include <linux/interrupt.h>
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#include <linux/io.h>
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#include <linux/module.h>
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#include <linux/pinctrl/consumer.h>
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#include <linux/platform_device.h>
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#include <linux/of.h>
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#include <linux/of_gpio.h>
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#include <linux/of_irq.h>
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#include <linux/pm_runtime.h>
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#include <linux/spi/spi.h>
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#include <linux/spi/spi_bitbang.h>
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/* SSC registers */
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#define SSC_BRG 0x000
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#define SSC_TBUF 0x004
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#define SSC_RBUF 0x008
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#define SSC_CTL 0x00C
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#define SSC_IEN 0x010
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#define SSC_I2C 0x018
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/* SSC Control */
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#define SSC_CTL_DATA_WIDTH_9 0x8
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#define SSC_CTL_DATA_WIDTH_MSK 0xf
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#define SSC_CTL_BM 0xf
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#define SSC_CTL_HB BIT(4)
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#define SSC_CTL_PH BIT(5)
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#define SSC_CTL_PO BIT(6)
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#define SSC_CTL_SR BIT(7)
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#define SSC_CTL_MS BIT(8)
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#define SSC_CTL_EN BIT(9)
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#define SSC_CTL_LPB BIT(10)
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#define SSC_CTL_EN_TX_FIFO BIT(11)
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#define SSC_CTL_EN_RX_FIFO BIT(12)
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#define SSC_CTL_EN_CLST_RX BIT(13)
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/* SSC Interrupt Enable */
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#define SSC_IEN_TEEN BIT(2)
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#define FIFO_SIZE 8
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struct spi_st {
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/* SSC SPI Controller */
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void __iomem *base;
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struct clk *clk;
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struct device *dev;
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/* SSC SPI current transaction */
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const u8 *tx_ptr;
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u8 *rx_ptr;
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u16 bytes_per_word;
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unsigned int words_remaining;
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unsigned int baud;
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struct completion done;
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};
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static int spi_st_clk_enable(struct spi_st *spi_st)
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{
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/*
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* Current platforms use one of the core clocks for SPI and I2C.
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* If we attempt to disable the clock, the system will hang.
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*
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* TODO: Remove this when platform supports power domains.
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*/
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return 0;
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return clk_prepare_enable(spi_st->clk);
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}
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static void spi_st_clk_disable(struct spi_st *spi_st)
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{
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/*
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* Current platforms use one of the core clocks for SPI and I2C.
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* If we attempt to disable the clock, the system will hang.
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*
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* TODO: Remove this when platform supports power domains.
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*/
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return;
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clk_disable_unprepare(spi_st->clk);
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}
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/* Load the TX FIFO */
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static void ssc_write_tx_fifo(struct spi_st *spi_st)
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{
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unsigned int count, i;
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uint32_t word = 0;
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if (spi_st->words_remaining > FIFO_SIZE)
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count = FIFO_SIZE;
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|
else
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|
count = spi_st->words_remaining;
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|
|
||||||
|
for (i = 0; i < count; i++) {
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||||||
|
if (spi_st->tx_ptr) {
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||||||
|
if (spi_st->bytes_per_word == 1) {
|
||||||
|
word = *spi_st->tx_ptr++;
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|
} else {
|
||||||
|
word = *spi_st->tx_ptr++;
|
||||||
|
word = *spi_st->tx_ptr++ | (word << 8);
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||||||
|
}
|
||||||
|
}
|
||||||
|
writel_relaxed(word, spi_st->base + SSC_TBUF);
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|
}
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|
}
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||||||
|
|
||||||
|
/* Read the RX FIFO */
|
||||||
|
static void ssc_read_rx_fifo(struct spi_st *spi_st)
|
||||||
|
{
|
||||||
|
unsigned int count, i;
|
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|
uint32_t word = 0;
|
||||||
|
|
||||||
|
if (spi_st->words_remaining > FIFO_SIZE)
|
||||||
|
count = FIFO_SIZE;
|
||||||
|
else
|
||||||
|
count = spi_st->words_remaining;
|
||||||
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|
||||||
|
for (i = 0; i < count; i++) {
|
||||||
|
word = readl_relaxed(spi_st->base + SSC_RBUF);
|
||||||
|
|
||||||
|
if (spi_st->rx_ptr) {
|
||||||
|
if (spi_st->bytes_per_word == 1) {
|
||||||
|
*spi_st->rx_ptr++ = (uint8_t)word;
|
||||||
|
} else {
|
||||||
|
*spi_st->rx_ptr++ = (word >> 8);
|
||||||
|
*spi_st->rx_ptr++ = word & 0xff;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
}
|
||||||
|
spi_st->words_remaining -= count;
|
||||||
|
}
|
||||||
|
|
||||||
|
static int spi_st_transfer_one(struct spi_master *master,
|
||||||
|
struct spi_device *spi, struct spi_transfer *t)
|
||||||
|
{
|
||||||
|
struct spi_st *spi_st = spi_master_get_devdata(master);
|
||||||
|
uint32_t ctl = 0;
|
||||||
|
|
||||||
|
/* Setup transfer */
|
||||||
|
spi_st->tx_ptr = t->tx_buf;
|
||||||
|
spi_st->rx_ptr = t->rx_buf;
|
||||||
|
|
||||||
|
if (spi->bits_per_word > 8) {
|
||||||
|
/*
|
||||||
|
* Anything greater than 8 bits-per-word requires 2
|
||||||
|
* bytes-per-word in the RX/TX buffers
|
||||||
|
*/
|
||||||
|
spi_st->bytes_per_word = 2;
|
||||||
|
spi_st->words_remaining = t->len / 2;
|
||||||
|
|
||||||
|
} else if (spi->bits_per_word == 8 && !(t->len & 0x1)) {
|
||||||
|
/*
|
||||||
|
* If transfer is even-length, and 8 bits-per-word, then
|
||||||
|
* implement as half-length 16 bits-per-word transfer
|
||||||
|
*/
|
||||||
|
spi_st->bytes_per_word = 2;
|
||||||
|
spi_st->words_remaining = t->len / 2;
|
||||||
|
|
||||||
|
/* Set SSC_CTL to 16 bits-per-word */
|
||||||
|
ctl = readl_relaxed(spi_st->base + SSC_CTL);
|
||||||
|
writel_relaxed((ctl | 0xf), spi_st->base + SSC_CTL);
|
||||||
|
|
||||||
|
readl_relaxed(spi_st->base + SSC_RBUF);
|
||||||
|
|
||||||
|
} else {
|
||||||
|
spi_st->bytes_per_word = 1;
|
||||||
|
spi_st->words_remaining = t->len;
|
||||||
|
}
|
||||||
|
|
||||||
|
reinit_completion(&spi_st->done);
|
||||||
|
|
||||||
|
/* Start transfer by writing to the TX FIFO */
|
||||||
|
ssc_write_tx_fifo(spi_st);
|
||||||
|
writel_relaxed(SSC_IEN_TEEN, spi_st->base + SSC_IEN);
|
||||||
|
|
||||||
|
/* Wait for transfer to complete */
|
||||||
|
wait_for_completion(&spi_st->done);
|
||||||
|
|
||||||
|
/* Restore SSC_CTL if necessary */
|
||||||
|
if (ctl)
|
||||||
|
writel_relaxed(ctl, spi_st->base + SSC_CTL);
|
||||||
|
|
||||||
|
spi_finalize_current_transfer(spi->master);
|
||||||
|
|
||||||
|
return t->len;
|
||||||
|
}
|
||||||
|
|
||||||
|
static void spi_st_cleanup(struct spi_device *spi)
|
||||||
|
{
|
||||||
|
int cs = spi->cs_gpio;
|
||||||
|
|
||||||
|
if (gpio_is_valid(cs))
|
||||||
|
devm_gpio_free(&spi->dev, cs);
|
||||||
|
}
|
||||||
|
|
||||||
|
/* the spi->mode bits understood by this driver: */
|
||||||
|
#define MODEBITS (SPI_CPOL | SPI_CPHA | SPI_LSB_FIRST | SPI_LOOP | SPI_CS_HIGH)
|
||||||
|
static int spi_st_setup(struct spi_device *spi)
|
||||||
|
{
|
||||||
|
struct spi_st *spi_st = spi_master_get_devdata(spi->master);
|
||||||
|
u32 spi_st_clk, sscbrg, var;
|
||||||
|
u32 hz = spi->max_speed_hz;
|
||||||
|
int cs = spi->cs_gpio;
|
||||||
|
int ret;
|
||||||
|
|
||||||
|
if (!hz) {
|
||||||
|
dev_err(&spi->dev, "max_speed_hz unspecified\n");
|
||||||
|
return -EINVAL;
|
||||||
|
}
|
||||||
|
|
||||||
|
if (!gpio_is_valid(cs)) {
|
||||||
|
dev_err(&spi->dev, "%d is not a valid gpio\n", cs);
|
||||||
|
return -EINVAL;
|
||||||
|
}
|
||||||
|
|
||||||
|
if (devm_gpio_request(&spi->dev, cs, dev_name(&spi->dev))) {
|
||||||
|
dev_err(&spi->dev, "could not request gpio:%d\n", cs);
|
||||||
|
return -EINVAL;
|
||||||
|
}
|
||||||
|
|
||||||
|
ret = gpio_direction_output(cs, spi->mode & SPI_CS_HIGH);
|
||||||
|
if (ret)
|
||||||
|
return ret;
|
||||||
|
|
||||||
|
spi_st_clk = clk_get_rate(spi_st->clk);
|
||||||
|
|
||||||
|
/* Set SSC_BRF */
|
||||||
|
sscbrg = spi_st_clk / (2 * hz);
|
||||||
|
if (sscbrg < 0x07 || sscbrg > BIT(16)) {
|
||||||
|
dev_err(&spi->dev,
|
||||||
|
"baudrate %d outside valid range %d\n", sscbrg, hz);
|
||||||
|
return -EINVAL;
|
||||||
|
}
|
||||||
|
|
||||||
|
spi_st->baud = spi_st_clk / (2 * sscbrg);
|
||||||
|
if (sscbrg == BIT(16)) /* 16-bit counter wraps */
|
||||||
|
sscbrg = 0x0;
|
||||||
|
|
||||||
|
writel_relaxed(sscbrg, spi_st->base + SSC_BRG);
|
||||||
|
|
||||||
|
dev_dbg(&spi->dev,
|
||||||
|
"setting baudrate:target= %u hz, actual= %u hz, sscbrg= %u\n",
|
||||||
|
hz, spi_st->baud, sscbrg);
|
||||||
|
|
||||||
|
/* Set SSC_CTL and enable SSC */
|
||||||
|
var = readl_relaxed(spi_st->base + SSC_CTL);
|
||||||
|
var |= SSC_CTL_MS;
|
||||||
|
|
||||||
|
if (spi->mode & SPI_CPOL)
|
||||||
|
var |= SSC_CTL_PO;
|
||||||
|
else
|
||||||
|
var &= ~SSC_CTL_PO;
|
||||||
|
|
||||||
|
if (spi->mode & SPI_CPHA)
|
||||||
|
var |= SSC_CTL_PH;
|
||||||
|
else
|
||||||
|
var &= ~SSC_CTL_PH;
|
||||||
|
|
||||||
|
if ((spi->mode & SPI_LSB_FIRST) == 0)
|
||||||
|
var |= SSC_CTL_HB;
|
||||||
|
else
|
||||||
|
var &= ~SSC_CTL_HB;
|
||||||
|
|
||||||
|
if (spi->mode & SPI_LOOP)
|
||||||
|
var |= SSC_CTL_LPB;
|
||||||
|
else
|
||||||
|
var &= ~SSC_CTL_LPB;
|
||||||
|
|
||||||
|
var &= ~SSC_CTL_DATA_WIDTH_MSK;
|
||||||
|
var |= (spi->bits_per_word - 1);
|
||||||
|
|
||||||
|
var |= SSC_CTL_EN_TX_FIFO | SSC_CTL_EN_RX_FIFO;
|
||||||
|
var |= SSC_CTL_EN;
|
||||||
|
|
||||||
|
writel_relaxed(var, spi_st->base + SSC_CTL);
|
||||||
|
|
||||||
|
/* Clear the status register */
|
||||||
|
readl_relaxed(spi_st->base + SSC_RBUF);
|
||||||
|
|
||||||
|
return 0;
|
||||||
|
}
|
||||||
|
|
||||||
|
/* Interrupt fired when TX shift register becomes empty */
|
||||||
|
static irqreturn_t spi_st_irq(int irq, void *dev_id)
|
||||||
|
{
|
||||||
|
struct spi_st *spi_st = (struct spi_st *)dev_id;
|
||||||
|
|
||||||
|
/* Read RX FIFO */
|
||||||
|
ssc_read_rx_fifo(spi_st);
|
||||||
|
|
||||||
|
/* Fill TX FIFO */
|
||||||
|
if (spi_st->words_remaining) {
|
||||||
|
ssc_write_tx_fifo(spi_st);
|
||||||
|
} else {
|
||||||
|
/* TX/RX complete */
|
||||||
|
writel_relaxed(0x0, spi_st->base + SSC_IEN);
|
||||||
|
/*
|
||||||
|
* read SSC_IEN to ensure that this bit is set
|
||||||
|
* before re-enabling interrupt
|
||||||
|
*/
|
||||||
|
readl(spi_st->base + SSC_IEN);
|
||||||
|
complete(&spi_st->done);
|
||||||
|
}
|
||||||
|
|
||||||
|
return IRQ_HANDLED;
|
||||||
|
}
|
||||||
|
|
||||||
|
static int spi_st_probe(struct platform_device *pdev)
|
||||||
|
{
|
||||||
|
struct device_node *np = pdev->dev.of_node;
|
||||||
|
struct spi_master *master;
|
||||||
|
struct resource *res;
|
||||||
|
struct spi_st *spi_st;
|
||||||
|
int irq, ret = 0;
|
||||||
|
u32 var;
|
||||||
|
|
||||||
|
master = spi_alloc_master(&pdev->dev, sizeof(*spi_st));
|
||||||
|
if (!master)
|
||||||
|
return -ENOMEM;
|
||||||
|
|
||||||
|
master->dev.of_node = np;
|
||||||
|
master->mode_bits = MODEBITS;
|
||||||
|
master->setup = spi_st_setup;
|
||||||
|
master->cleanup = spi_st_cleanup;
|
||||||
|
master->transfer_one = spi_st_transfer_one;
|
||||||
|
master->bits_per_word_mask = SPI_BPW_MASK(8) | SPI_BPW_MASK(16);
|
||||||
|
master->auto_runtime_pm = true;
|
||||||
|
master->bus_num = pdev->id;
|
||||||
|
spi_st = spi_master_get_devdata(master);
|
||||||
|
|
||||||
|
spi_st->clk = devm_clk_get(&pdev->dev, "ssc");
|
||||||
|
if (IS_ERR(spi_st->clk)) {
|
||||||
|
dev_err(&pdev->dev, "Unable to request clock\n");
|
||||||
|
return PTR_ERR(spi_st->clk);
|
||||||
|
}
|
||||||
|
|
||||||
|
ret = spi_st_clk_enable(spi_st);
|
||||||
|
if (ret)
|
||||||
|
return ret;
|
||||||
|
|
||||||
|
init_completion(&spi_st->done);
|
||||||
|
|
||||||
|
/* Get resources */
|
||||||
|
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
|
||||||
|
spi_st->base = devm_ioremap_resource(&pdev->dev, res);
|
||||||
|
if (IS_ERR(spi_st->base)) {
|
||||||
|
ret = PTR_ERR(spi_st->base);
|
||||||
|
goto clk_disable;
|
||||||
|
}
|
||||||
|
|
||||||
|
/* Disable I2C and Reset SSC */
|
||||||
|
writel_relaxed(0x0, spi_st->base + SSC_I2C);
|
||||||
|
var = readw_relaxed(spi_st->base + SSC_CTL);
|
||||||
|
var |= SSC_CTL_SR;
|
||||||
|
writel_relaxed(var, spi_st->base + SSC_CTL);
|
||||||
|
|
||||||
|
udelay(1);
|
||||||
|
var = readl_relaxed(spi_st->base + SSC_CTL);
|
||||||
|
var &= ~SSC_CTL_SR;
|
||||||
|
writel_relaxed(var, spi_st->base + SSC_CTL);
|
||||||
|
|
||||||
|
/* Set SSC into slave mode before reconfiguring PIO pins */
|
||||||
|
var = readl_relaxed(spi_st->base + SSC_CTL);
|
||||||
|
var &= ~SSC_CTL_MS;
|
||||||
|
writel_relaxed(var, spi_st->base + SSC_CTL);
|
||||||
|
|
||||||
|
irq = irq_of_parse_and_map(np, 0);
|
||||||
|
if (!irq) {
|
||||||
|
dev_err(&pdev->dev, "IRQ missing or invalid\n");
|
||||||
|
ret = -EINVAL;
|
||||||
|
goto clk_disable;
|
||||||
|
}
|
||||||
|
|
||||||
|
ret = devm_request_irq(&pdev->dev, irq, spi_st_irq, 0,
|
||||||
|
pdev->name, spi_st);
|
||||||
|
if (ret) {
|
||||||
|
dev_err(&pdev->dev, "Failed to request irq %d\n", irq);
|
||||||
|
goto clk_disable;
|
||||||
|
}
|
||||||
|
|
||||||
|
/* by default the device is on */
|
||||||
|
pm_runtime_set_active(&pdev->dev);
|
||||||
|
pm_runtime_enable(&pdev->dev);
|
||||||
|
|
||||||
|
platform_set_drvdata(pdev, master);
|
||||||
|
|
||||||
|
ret = devm_spi_register_master(&pdev->dev, master);
|
||||||
|
if (ret) {
|
||||||
|
dev_err(&pdev->dev, "Failed to register master\n");
|
||||||
|
goto clk_disable;
|
||||||
|
}
|
||||||
|
|
||||||
|
return 0;
|
||||||
|
|
||||||
|
clk_disable:
|
||||||
|
spi_st_clk_disable(spi_st);
|
||||||
|
|
||||||
|
return ret;
|
||||||
|
}
|
||||||
|
|
||||||
|
static int spi_st_remove(struct platform_device *pdev)
|
||||||
|
{
|
||||||
|
struct spi_master *master = platform_get_drvdata(pdev);
|
||||||
|
struct spi_st *spi_st = spi_master_get_devdata(master);
|
||||||
|
|
||||||
|
spi_st_clk_disable(spi_st);
|
||||||
|
|
||||||
|
pinctrl_pm_select_sleep_state(&pdev->dev);
|
||||||
|
|
||||||
|
return 0;
|
||||||
|
}
|
||||||
|
|
||||||
|
#ifdef CONFIG_PM
|
||||||
|
static int spi_st_runtime_suspend(struct device *dev)
|
||||||
|
{
|
||||||
|
struct spi_master *master = dev_get_drvdata(dev);
|
||||||
|
struct spi_st *spi_st = spi_master_get_devdata(master);
|
||||||
|
|
||||||
|
writel_relaxed(0, spi_st->base + SSC_IEN);
|
||||||
|
pinctrl_pm_select_sleep_state(dev);
|
||||||
|
|
||||||
|
spi_st_clk_disable(spi_st);
|
||||||
|
|
||||||
|
return 0;
|
||||||
|
}
|
||||||
|
|
||||||
|
static int spi_st_runtime_resume(struct device *dev)
|
||||||
|
{
|
||||||
|
struct spi_master *master = dev_get_drvdata(dev);
|
||||||
|
struct spi_st *spi_st = spi_master_get_devdata(master);
|
||||||
|
int ret;
|
||||||
|
|
||||||
|
ret = spi_st_clk_enable(spi_st);
|
||||||
|
pinctrl_pm_select_default_state(dev);
|
||||||
|
|
||||||
|
return ret;
|
||||||
|
}
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#ifdef CONFIG_PM_SLEEP
|
||||||
|
static int spi_st_suspend(struct device *dev)
|
||||||
|
{
|
||||||
|
struct spi_master *master = dev_get_drvdata(dev);
|
||||||
|
int ret;
|
||||||
|
|
||||||
|
ret = spi_master_suspend(master);
|
||||||
|
if (ret)
|
||||||
|
return ret;
|
||||||
|
|
||||||
|
return pm_runtime_force_suspend(dev);
|
||||||
|
}
|
||||||
|
|
||||||
|
static int spi_st_resume(struct device *dev)
|
||||||
|
{
|
||||||
|
struct spi_master *master = dev_get_drvdata(dev);
|
||||||
|
int ret;
|
||||||
|
|
||||||
|
ret = spi_master_resume(master);
|
||||||
|
if (ret)
|
||||||
|
return ret;
|
||||||
|
|
||||||
|
return pm_runtime_force_resume(dev);
|
||||||
|
}
|
||||||
|
#endif
|
||||||
|
|
||||||
|
static const struct dev_pm_ops spi_st_pm = {
|
||||||
|
SET_SYSTEM_SLEEP_PM_OPS(spi_st_suspend, spi_st_resume)
|
||||||
|
SET_RUNTIME_PM_OPS(spi_st_runtime_suspend, spi_st_runtime_resume, NULL)
|
||||||
|
};
|
||||||
|
|
||||||
|
static struct of_device_id stm_spi_match[] = {
|
||||||
|
{ .compatible = "st,comms-ssc4-spi", },
|
||||||
|
{},
|
||||||
|
};
|
||||||
|
MODULE_DEVICE_TABLE(of, stm_spi_match);
|
||||||
|
|
||||||
|
static struct platform_driver spi_st_driver = {
|
||||||
|
.driver = {
|
||||||
|
.name = "spi-st",
|
||||||
|
.pm = &spi_st_pm,
|
||||||
|
.of_match_table = of_match_ptr(stm_spi_match),
|
||||||
|
},
|
||||||
|
.probe = spi_st_probe,
|
||||||
|
.remove = spi_st_remove,
|
||||||
|
};
|
||||||
|
module_platform_driver(spi_st_driver);
|
||||||
|
|
||||||
|
MODULE_AUTHOR("Patrice Chotard <patrice.chotard@st.com>");
|
||||||
|
MODULE_DESCRIPTION("STM SSC SPI driver");
|
||||||
|
MODULE_LICENSE("GPL v2");
|
|
@ -201,7 +201,7 @@ static void ti_qspi_restore_ctx(struct ti_qspi *qspi)
|
||||||
|
|
||||||
static int qspi_write_msg(struct ti_qspi *qspi, struct spi_transfer *t)
|
static int qspi_write_msg(struct ti_qspi *qspi, struct spi_transfer *t)
|
||||||
{
|
{
|
||||||
int wlen, count, ret;
|
int wlen, count;
|
||||||
unsigned int cmd;
|
unsigned int cmd;
|
||||||
const u8 *txbuf;
|
const u8 *txbuf;
|
||||||
|
|
||||||
|
@ -230,9 +230,8 @@ static int qspi_write_msg(struct ti_qspi *qspi, struct spi_transfer *t)
|
||||||
}
|
}
|
||||||
|
|
||||||
ti_qspi_write(qspi, cmd, QSPI_SPI_CMD_REG);
|
ti_qspi_write(qspi, cmd, QSPI_SPI_CMD_REG);
|
||||||
ret = wait_for_completion_timeout(&qspi->transfer_complete,
|
if (!wait_for_completion_timeout(&qspi->transfer_complete,
|
||||||
QSPI_COMPLETION_TIMEOUT);
|
QSPI_COMPLETION_TIMEOUT)) {
|
||||||
if (ret == 0) {
|
|
||||||
dev_err(qspi->dev, "write timed out\n");
|
dev_err(qspi->dev, "write timed out\n");
|
||||||
return -ETIMEDOUT;
|
return -ETIMEDOUT;
|
||||||
}
|
}
|
||||||
|
@ -245,7 +244,7 @@ static int qspi_write_msg(struct ti_qspi *qspi, struct spi_transfer *t)
|
||||||
|
|
||||||
static int qspi_read_msg(struct ti_qspi *qspi, struct spi_transfer *t)
|
static int qspi_read_msg(struct ti_qspi *qspi, struct spi_transfer *t)
|
||||||
{
|
{
|
||||||
int wlen, count, ret;
|
int wlen, count;
|
||||||
unsigned int cmd;
|
unsigned int cmd;
|
||||||
u8 *rxbuf;
|
u8 *rxbuf;
|
||||||
|
|
||||||
|
@ -268,9 +267,8 @@ static int qspi_read_msg(struct ti_qspi *qspi, struct spi_transfer *t)
|
||||||
while (count) {
|
while (count) {
|
||||||
dev_dbg(qspi->dev, "rx cmd %08x dc %08x\n", cmd, qspi->dc);
|
dev_dbg(qspi->dev, "rx cmd %08x dc %08x\n", cmd, qspi->dc);
|
||||||
ti_qspi_write(qspi, cmd, QSPI_SPI_CMD_REG);
|
ti_qspi_write(qspi, cmd, QSPI_SPI_CMD_REG);
|
||||||
ret = wait_for_completion_timeout(&qspi->transfer_complete,
|
if (!wait_for_completion_timeout(&qspi->transfer_complete,
|
||||||
QSPI_COMPLETION_TIMEOUT);
|
QSPI_COMPLETION_TIMEOUT)) {
|
||||||
if (ret == 0) {
|
|
||||||
dev_err(qspi->dev, "read timed out\n");
|
dev_err(qspi->dev, "read timed out\n");
|
||||||
return -ETIMEDOUT;
|
return -ETIMEDOUT;
|
||||||
}
|
}
|
||||||
|
|
|
@ -313,6 +313,37 @@ done:
|
||||||
return status;
|
return status;
|
||||||
}
|
}
|
||||||
|
|
||||||
|
static struct spi_ioc_transfer *
|
||||||
|
spidev_get_ioc_message(unsigned int cmd, struct spi_ioc_transfer __user *u_ioc,
|
||||||
|
unsigned *n_ioc)
|
||||||
|
{
|
||||||
|
struct spi_ioc_transfer *ioc;
|
||||||
|
u32 tmp;
|
||||||
|
|
||||||
|
/* Check type, command number and direction */
|
||||||
|
if (_IOC_TYPE(cmd) != SPI_IOC_MAGIC
|
||||||
|
|| _IOC_NR(cmd) != _IOC_NR(SPI_IOC_MESSAGE(0))
|
||||||
|
|| _IOC_DIR(cmd) != _IOC_WRITE)
|
||||||
|
return ERR_PTR(-ENOTTY);
|
||||||
|
|
||||||
|
tmp = _IOC_SIZE(cmd);
|
||||||
|
if ((tmp % sizeof(struct spi_ioc_transfer)) != 0)
|
||||||
|
return ERR_PTR(-EINVAL);
|
||||||
|
*n_ioc = tmp / sizeof(struct spi_ioc_transfer);
|
||||||
|
if (*n_ioc == 0)
|
||||||
|
return NULL;
|
||||||
|
|
||||||
|
/* copy into scratch area */
|
||||||
|
ioc = kmalloc(tmp, GFP_KERNEL);
|
||||||
|
if (!ioc)
|
||||||
|
return ERR_PTR(-ENOMEM);
|
||||||
|
if (__copy_from_user(ioc, u_ioc, tmp)) {
|
||||||
|
kfree(ioc);
|
||||||
|
return ERR_PTR(-EFAULT);
|
||||||
|
}
|
||||||
|
return ioc;
|
||||||
|
}
|
||||||
|
|
||||||
static long
|
static long
|
||||||
spidev_ioctl(struct file *filp, unsigned int cmd, unsigned long arg)
|
spidev_ioctl(struct file *filp, unsigned int cmd, unsigned long arg)
|
||||||
{
|
{
|
||||||
|
@ -452,32 +483,15 @@ spidev_ioctl(struct file *filp, unsigned int cmd, unsigned long arg)
|
||||||
|
|
||||||
default:
|
default:
|
||||||
/* segmented and/or full-duplex I/O request */
|
/* segmented and/or full-duplex I/O request */
|
||||||
if (_IOC_NR(cmd) != _IOC_NR(SPI_IOC_MESSAGE(0))
|
/* Check message and copy into scratch area */
|
||||||
|| _IOC_DIR(cmd) != _IOC_WRITE) {
|
ioc = spidev_get_ioc_message(cmd,
|
||||||
retval = -ENOTTY;
|
(struct spi_ioc_transfer __user *)arg, &n_ioc);
|
||||||
break;
|
if (IS_ERR(ioc)) {
|
||||||
}
|
retval = PTR_ERR(ioc);
|
||||||
|
|
||||||
tmp = _IOC_SIZE(cmd);
|
|
||||||
if ((tmp % sizeof(struct spi_ioc_transfer)) != 0) {
|
|
||||||
retval = -EINVAL;
|
|
||||||
break;
|
|
||||||
}
|
|
||||||
n_ioc = tmp / sizeof(struct spi_ioc_transfer);
|
|
||||||
if (n_ioc == 0)
|
|
||||||
break;
|
|
||||||
|
|
||||||
/* copy into scratch area */
|
|
||||||
ioc = kmalloc(tmp, GFP_KERNEL);
|
|
||||||
if (!ioc) {
|
|
||||||
retval = -ENOMEM;
|
|
||||||
break;
|
|
||||||
}
|
|
||||||
if (__copy_from_user(ioc, (void __user *)arg, tmp)) {
|
|
||||||
kfree(ioc);
|
|
||||||
retval = -EFAULT;
|
|
||||||
break;
|
break;
|
||||||
}
|
}
|
||||||
|
if (!ioc)
|
||||||
|
break; /* n_ioc is also 0 */
|
||||||
|
|
||||||
/* translate to spi_message, execute */
|
/* translate to spi_message, execute */
|
||||||
retval = spidev_message(spidev, ioc, n_ioc);
|
retval = spidev_message(spidev, ioc, n_ioc);
|
||||||
|
@ -491,9 +505,68 @@ spidev_ioctl(struct file *filp, unsigned int cmd, unsigned long arg)
|
||||||
}
|
}
|
||||||
|
|
||||||
#ifdef CONFIG_COMPAT
|
#ifdef CONFIG_COMPAT
|
||||||
|
static long
|
||||||
|
spidev_compat_ioc_message(struct file *filp, unsigned int cmd,
|
||||||
|
unsigned long arg)
|
||||||
|
{
|
||||||
|
struct spi_ioc_transfer __user *u_ioc;
|
||||||
|
int retval = 0;
|
||||||
|
struct spidev_data *spidev;
|
||||||
|
struct spi_device *spi;
|
||||||
|
unsigned n_ioc, n;
|
||||||
|
struct spi_ioc_transfer *ioc;
|
||||||
|
|
||||||
|
u_ioc = (struct spi_ioc_transfer __user *) compat_ptr(arg);
|
||||||
|
if (!access_ok(VERIFY_READ, u_ioc, _IOC_SIZE(cmd)))
|
||||||
|
return -EFAULT;
|
||||||
|
|
||||||
|
/* guard against device removal before, or while,
|
||||||
|
* we issue this ioctl.
|
||||||
|
*/
|
||||||
|
spidev = filp->private_data;
|
||||||
|
spin_lock_irq(&spidev->spi_lock);
|
||||||
|
spi = spi_dev_get(spidev->spi);
|
||||||
|
spin_unlock_irq(&spidev->spi_lock);
|
||||||
|
|
||||||
|
if (spi == NULL)
|
||||||
|
return -ESHUTDOWN;
|
||||||
|
|
||||||
|
/* SPI_IOC_MESSAGE needs the buffer locked "normally" */
|
||||||
|
mutex_lock(&spidev->buf_lock);
|
||||||
|
|
||||||
|
/* Check message and copy into scratch area */
|
||||||
|
ioc = spidev_get_ioc_message(cmd, u_ioc, &n_ioc);
|
||||||
|
if (IS_ERR(ioc)) {
|
||||||
|
retval = PTR_ERR(ioc);
|
||||||
|
goto done;
|
||||||
|
}
|
||||||
|
if (!ioc)
|
||||||
|
goto done; /* n_ioc is also 0 */
|
||||||
|
|
||||||
|
/* Convert buffer pointers */
|
||||||
|
for (n = 0; n < n_ioc; n++) {
|
||||||
|
ioc[n].rx_buf = (uintptr_t) compat_ptr(ioc[n].rx_buf);
|
||||||
|
ioc[n].tx_buf = (uintptr_t) compat_ptr(ioc[n].tx_buf);
|
||||||
|
}
|
||||||
|
|
||||||
|
/* translate to spi_message, execute */
|
||||||
|
retval = spidev_message(spidev, ioc, n_ioc);
|
||||||
|
kfree(ioc);
|
||||||
|
|
||||||
|
done:
|
||||||
|
mutex_unlock(&spidev->buf_lock);
|
||||||
|
spi_dev_put(spi);
|
||||||
|
return retval;
|
||||||
|
}
|
||||||
|
|
||||||
static long
|
static long
|
||||||
spidev_compat_ioctl(struct file *filp, unsigned int cmd, unsigned long arg)
|
spidev_compat_ioctl(struct file *filp, unsigned int cmd, unsigned long arg)
|
||||||
{
|
{
|
||||||
|
if (_IOC_TYPE(cmd) == SPI_IOC_MAGIC
|
||||||
|
&& _IOC_NR(cmd) == _IOC_NR(SPI_IOC_MESSAGE(0))
|
||||||
|
&& _IOC_DIR(cmd) == _IOC_WRITE)
|
||||||
|
return spidev_compat_ioc_message(filp, cmd, arg);
|
||||||
|
|
||||||
return spidev_ioctl(filp, cmd, (unsigned long)compat_ptr(arg));
|
return spidev_ioctl(filp, cmd, (unsigned long)compat_ptr(arg));
|
||||||
}
|
}
|
||||||
#else
|
#else
|
||||||
|
|
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