usb: phy: msm: Select secondary PHY via TCSR
Select the secondary PHY using the TCSR register, if phy-num=1 in the DTS (or phy_number is set in the platform data). The SOC has 2 PHYs which can be used with the OTG port, and this code allows configuring the correct one. Note: This resolves the problem I was seeing where I couldn't get the USB driver working at all on a dragonboard, from cold boot. This patch depends on patch 5/14 from Ivan's msm USB patch set. It does not use DT for the register address, as there's no evidence that this address changes between SoC versions. Signed-off-by: Tim Bird <tim.bird@sonymobile.com> Signed-off-by: Ivan T. Ivanov <iivanov@mm-sol.com> Signed-off-by: Felipe Balbi <balbi@ti.com>
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9f27984b9e
Коммит
30bf8667ce
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@ -1489,6 +1489,7 @@ static int msm_otg_probe(struct platform_device *pdev)
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struct resource *res;
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struct msm_otg *motg;
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struct usb_phy *phy;
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void __iomem *phy_select;
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motg = devm_kzalloc(&pdev->dev, sizeof(struct msm_otg), GFP_KERNEL);
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if (!motg) {
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@ -1553,6 +1554,19 @@ static int msm_otg_probe(struct platform_device *pdev)
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if (IS_ERR(motg->regs))
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return PTR_ERR(motg->regs);
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/*
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* NOTE: The PHYs can be multiplexed between the chipidea controller
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* and the dwc3 controller, using a single bit. It is important that
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* the dwc3 driver does not set this bit in an incompatible way.
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*/
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if (motg->phy_number) {
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phy_select = devm_ioremap_nocache(&pdev->dev, USB2_PHY_SEL, 4);
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if (IS_ERR(phy_select))
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return PTR_ERR(phy_select);
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/* Enable second PHY with the OTG port */
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writel_relaxed(0x1, phy_select);
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}
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dev_info(&pdev->dev, "OTG regs = %p\n", motg->regs);
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motg->irq = platform_get_irq(pdev, 0);
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@ -16,6 +16,9 @@
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#ifndef __LINUX_USB_GADGET_MSM72K_UDC_H__
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#define __LINUX_USB_GADGET_MSM72K_UDC_H__
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/* USB phy selector - in TCSR address range */
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#define USB2_PHY_SEL 0xfd4ab000
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#define USB_AHBBURST (MSM_USB_BASE + 0x0090)
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#define USB_AHBMODE (MSM_USB_BASE + 0x0098)
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#define USB_CAPLENGTH (MSM_USB_BASE + 0x0100) /* 8 bit */
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