qed: FW 8.42.2.0 Add fw overlay feature
This feature enables the FW to page out FW code when required Signed-off-by: Ariel Elior <ariel.elior@marvell.com> Signed-off-by: Michal Kalderon <michal.kalderon@marvell.com> Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
Michal Kalderon
David S. Miller
Родитель
0500a70d6e
Коммит
30d5f85895
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@ -462,6 +462,8 @@ struct qed_fw_data {
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const u8 *modes_tree_buf;
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union init_op *init_ops;
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const u32 *arr_data;
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const u32 *fw_overlays;
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u32 fw_overlays_len;
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u32 init_ops_size;
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};
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@ -686,6 +688,7 @@ struct qed_hwfn {
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/* Nvm images number and attributes */
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struct qed_nvm_image_info nvm_info;
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struct phys_mem_desc *fw_overlay_mem;
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struct qed_ptt *p_arfs_ptt;
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struct qed_simd_fp_handler simd_proto_handler[64];
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@ -1412,6 +1412,7 @@ void qed_resc_free(struct qed_dev *cdev)
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qed_dmae_info_free(p_hwfn);
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qed_dcbx_info_free(p_hwfn);
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qed_dbg_user_data_free(p_hwfn);
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qed_fw_overlay_mem_free(p_hwfn, p_hwfn->fw_overlay_mem);
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/* Destroy doorbell recovery mechanism */
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qed_db_recovery_teardown(p_hwfn);
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@ -2893,6 +2894,8 @@ static int qed_hw_init_pf(struct qed_hwfn *p_hwfn,
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if (rc)
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return rc;
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qed_fw_overlay_init_ram(p_hwfn, p_ptt, p_hwfn->fw_overlay_mem);
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/* Pure runtime initializations - directly to the HW */
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qed_int_igu_init_pure_rt(p_hwfn, p_ptt, true, true);
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@ -3002,8 +3005,10 @@ int qed_hw_init(struct qed_dev *cdev, struct qed_hw_init_params *p_params)
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u32 load_code, resp, param, drv_mb_param;
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bool b_default_mtu = true;
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struct qed_hwfn *p_hwfn;
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int rc = 0, i;
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const u32 *fw_overlays;
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u32 fw_overlays_len;
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u16 ether_type;
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int rc = 0, i;
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if ((p_params->int_mode == QED_INT_MODE_MSI) && (cdev->num_hwfns > 1)) {
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DP_NOTICE(cdev, "MSI mode is not supported for CMT devices\n");
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@ -3104,6 +3109,17 @@ int qed_hw_init(struct qed_dev *cdev, struct qed_hw_init_params *p_params)
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*/
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qed_pglueb_clear_err(p_hwfn, p_hwfn->p_main_ptt);
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fw_overlays = cdev->fw_data->fw_overlays;
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fw_overlays_len = cdev->fw_data->fw_overlays_len;
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p_hwfn->fw_overlay_mem =
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qed_fw_overlay_mem_alloc(p_hwfn, fw_overlays,
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fw_overlays_len);
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if (!p_hwfn->fw_overlay_mem) {
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DP_NOTICE(p_hwfn,
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"Failed to allocate fw overlay memory\n");
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goto load_err;
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}
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switch (load_code) {
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case FW_MSG_CODE_DRV_LOAD_ENGINE:
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rc = qed_hw_init_common(p_hwfn, p_hwfn->p_main_ptt,
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@ -1843,6 +1843,19 @@ struct sdm_op_gen {
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#define SDM_OP_GEN_RESERVED_SHIFT 20
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};
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/* Physical memory descriptor */
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struct phys_mem_desc {
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dma_addr_t phys_addr;
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void *virt_addr;
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u32 size; /* In bytes */
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};
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/* Virtual memory descriptor */
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struct virt_mem_desc {
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void *ptr;
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u32 size; /* In bytes */
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};
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/****************************************/
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/* Debug Tools HSI constants and macros */
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/****************************************/
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@ -2872,6 +2885,15 @@ enum bin_init_buffer_type {
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MAX_BIN_INIT_BUFFER_TYPE
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};
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/* FW overlay buffer header */
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struct fw_overlay_buf_hdr {
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u32 data;
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#define FW_OVERLAY_BUF_HDR_STORM_ID_MASK 0xFF
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#define FW_OVERLAY_BUF_HDR_STORM_ID_SHIFT 0
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#define FW_OVERLAY_BUF_HDR_BUF_SIZE_MASK 0xFFFFFF
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#define FW_OVERLAY_BUF_HDR_BUF_SIZE_SHIFT 8
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};
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/* init array header: raw */
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struct init_array_raw_hdr {
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u32 data;
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@ -4345,6 +4367,42 @@ void qed_memset_task_ctx(void *p_ctx_mem, u32 ctx_size, u8 ctx_type);
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void qed_set_rdma_error_level(struct qed_hwfn *p_hwfn,
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struct qed_ptt *p_ptt,
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u8 assert_level[NUM_STORMS]);
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/**
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* @brief qed_fw_overlay_mem_alloc - Allocates and fills the FW overlay memory.
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*
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* @param p_hwfn - HW device data
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* @param fw_overlay_in_buf - the input FW overlay buffer.
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* @param buf_size - the size of the input FW overlay buffer in bytes.
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* must be aligned to dwords.
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* @param fw_overlay_out_mem - OUT: a pointer to the allocated overlays memory.
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*
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* @return a pointer to the allocated overlays memory,
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* or NULL in case of failures.
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*/
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struct phys_mem_desc *
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qed_fw_overlay_mem_alloc(struct qed_hwfn *p_hwfn,
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const u32 * const fw_overlay_in_buf,
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u32 buf_size_in_bytes);
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/**
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* @brief qed_fw_overlay_init_ram - Initializes the FW overlay RAM.
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*
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* @param p_hwfn - HW device data.
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* @param p_ptt - ptt window used for writing the registers.
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* @param fw_overlay_mem - the allocated FW overlay memory.
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*/
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void qed_fw_overlay_init_ram(struct qed_hwfn *p_hwfn,
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struct qed_ptt *p_ptt,
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struct phys_mem_desc *fw_overlay_mem);
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/**
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* @brief qed_fw_overlay_mem_free - Frees the FW overlay memory.
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*
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* @param p_hwfn - HW device data.
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* @param fw_overlay_mem - the allocated FW overlay memory to free.
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*/
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void qed_fw_overlay_mem_free(struct qed_hwfn *p_hwfn,
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struct phys_mem_desc *fw_overlay_mem);
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/* Ystorm flow control mode. Use enum fw_flow_ctrl_mode */
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#define YSTORM_FLOW_CONTROL_MODE_OFFSET (IRO[0].base)
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@ -1572,3 +1572,144 @@ void qed_set_rdma_error_level(struct qed_hwfn *p_hwfn,
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qed_wr(p_hwfn, p_ptt, ram_addr, assert_level[storm_id]);
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}
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}
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#define PHYS_ADDR_DWORDS DIV_ROUND_UP(sizeof(dma_addr_t), 4)
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#define OVERLAY_HDR_SIZE_DWORDS (sizeof(struct fw_overlay_buf_hdr) / 4)
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static u32 qed_get_overlay_addr_ram_addr(struct qed_hwfn *p_hwfn, u8 storm_id)
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{
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switch (storm_id) {
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case 0:
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return TSEM_REG_FAST_MEMORY + SEM_FAST_REG_INT_RAM +
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TSTORM_OVERLAY_BUF_ADDR_OFFSET;
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case 1:
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return MSEM_REG_FAST_MEMORY + SEM_FAST_REG_INT_RAM +
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MSTORM_OVERLAY_BUF_ADDR_OFFSET;
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case 2:
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return USEM_REG_FAST_MEMORY + SEM_FAST_REG_INT_RAM +
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USTORM_OVERLAY_BUF_ADDR_OFFSET;
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case 3:
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return XSEM_REG_FAST_MEMORY + SEM_FAST_REG_INT_RAM +
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XSTORM_OVERLAY_BUF_ADDR_OFFSET;
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case 4:
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return YSEM_REG_FAST_MEMORY + SEM_FAST_REG_INT_RAM +
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YSTORM_OVERLAY_BUF_ADDR_OFFSET;
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case 5:
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return PSEM_REG_FAST_MEMORY + SEM_FAST_REG_INT_RAM +
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PSTORM_OVERLAY_BUF_ADDR_OFFSET;
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default:
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return 0;
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}
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}
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struct phys_mem_desc *qed_fw_overlay_mem_alloc(struct qed_hwfn *p_hwfn,
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const u32 * const
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fw_overlay_in_buf,
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u32 buf_size_in_bytes)
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{
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u32 buf_size = buf_size_in_bytes / sizeof(u32), buf_offset = 0;
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struct phys_mem_desc *allocated_mem;
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if (!buf_size)
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return NULL;
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allocated_mem = kcalloc(NUM_STORMS, sizeof(struct phys_mem_desc),
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GFP_KERNEL);
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if (!allocated_mem)
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return NULL;
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memset(allocated_mem, 0, NUM_STORMS * sizeof(struct phys_mem_desc));
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/* For each Storm, set physical address in RAM */
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while (buf_offset < buf_size) {
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struct phys_mem_desc *storm_mem_desc;
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struct fw_overlay_buf_hdr *hdr;
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u32 storm_buf_size;
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u8 storm_id;
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hdr =
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(struct fw_overlay_buf_hdr *)&fw_overlay_in_buf[buf_offset];
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storm_buf_size = GET_FIELD(hdr->data,
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FW_OVERLAY_BUF_HDR_BUF_SIZE);
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storm_id = GET_FIELD(hdr->data, FW_OVERLAY_BUF_HDR_STORM_ID);
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storm_mem_desc = allocated_mem + storm_id;
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storm_mem_desc->size = storm_buf_size * sizeof(u32);
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/* Allocate physical memory for Storm's overlays buffer */
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storm_mem_desc->virt_addr =
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dma_alloc_coherent(&p_hwfn->cdev->pdev->dev,
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storm_mem_desc->size,
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&storm_mem_desc->phys_addr, GFP_KERNEL);
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if (!storm_mem_desc->virt_addr)
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break;
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/* Skip overlays buffer header */
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buf_offset += OVERLAY_HDR_SIZE_DWORDS;
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/* Copy Storm's overlays buffer to allocated memory */
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memcpy(storm_mem_desc->virt_addr,
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&fw_overlay_in_buf[buf_offset], storm_mem_desc->size);
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/* Advance to next Storm */
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buf_offset += storm_buf_size;
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}
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/* If memory allocation has failed, free all allocated memory */
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if (buf_offset < buf_size) {
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qed_fw_overlay_mem_free(p_hwfn, allocated_mem);
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return NULL;
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}
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return allocated_mem;
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}
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void qed_fw_overlay_init_ram(struct qed_hwfn *p_hwfn,
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struct qed_ptt *p_ptt,
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struct phys_mem_desc *fw_overlay_mem)
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{
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u8 storm_id;
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for (storm_id = 0; storm_id < NUM_STORMS; storm_id++) {
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struct phys_mem_desc *storm_mem_desc =
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(struct phys_mem_desc *)fw_overlay_mem + storm_id;
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u32 ram_addr, i;
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/* Skip Storms with no FW overlays */
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if (!storm_mem_desc->virt_addr)
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continue;
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/* Calculate overlay RAM GRC address of current PF */
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ram_addr = qed_get_overlay_addr_ram_addr(p_hwfn, storm_id) +
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sizeof(dma_addr_t) * p_hwfn->rel_pf_id;
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/* Write Storm's overlay physical address to RAM */
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for (i = 0; i < PHYS_ADDR_DWORDS; i++, ram_addr += sizeof(u32))
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qed_wr(p_hwfn, p_ptt, ram_addr,
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((u32 *)&storm_mem_desc->phys_addr)[i]);
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}
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}
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void qed_fw_overlay_mem_free(struct qed_hwfn *p_hwfn,
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struct phys_mem_desc *fw_overlay_mem)
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{
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u8 storm_id;
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if (!fw_overlay_mem)
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return;
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for (storm_id = 0; storm_id < NUM_STORMS; storm_id++) {
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struct phys_mem_desc *storm_mem_desc =
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(struct phys_mem_desc *)fw_overlay_mem + storm_id;
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/* Free Storm's physical memory */
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if (storm_mem_desc->virt_addr)
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dma_free_coherent(&p_hwfn->cdev->pdev->dev,
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storm_mem_desc->size,
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storm_mem_desc->virt_addr,
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storm_mem_desc->phys_addr);
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}
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/* Free allocated virtual memory */
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kfree(fw_overlay_mem);
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}
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@ -589,5 +589,10 @@ int qed_init_fw_data(struct qed_dev *cdev, const u8 *data)
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len = buf_hdr[BIN_BUF_INIT_CMD].length;
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fw->init_ops_size = len / sizeof(struct init_raw_op);
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offset = buf_hdr[BIN_BUF_INIT_OVERLAYS].offset;
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fw->fw_overlays = (u32 *)(data + offset);
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len = buf_hdr[BIN_BUF_INIT_OVERLAYS].length;
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fw->fw_overlays_len = len;
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return 0;
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}
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