arm: zynq: Migrate platform to clock controller
Migrate the Zynq platform and its drivers to use the new clock controller driver. Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com> Cc: John Stultz <john.stultz@linaro.org> Cc: Thomas Gleixner <tglx@linutronix.de> Cc: Greg Kroah-Hartman <gregkh@linuxfoundation.org> Cc: Jiri Slaby <jslaby@suse.cz> Cc: linux-serial@vger.kernel.org Signed-off-by: Michal Simek <michal.simek@xilinx.com> Acked-by: Mike Turquette <mturquette@linaro.org>
This commit is contained in:
Soren Brinkmann
Michal Simek
Родитель
0ee52b157b
Коммит
30e1e28598
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@ -49,16 +49,18 @@
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uart0: uart@e0000000 {
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compatible = "xlnx,xuartps";
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clocks = <&clkc 23>, <&clkc 40>;
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clock-names = "ref_clk", "aper_clk";
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reg = <0xE0000000 0x1000>;
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interrupts = <0 27 4>;
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clocks = <&uart_clk 0>;
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};
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uart1: uart@e0001000 {
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compatible = "xlnx,xuartps";
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clocks = <&clkc 24>, <&clkc 41>;
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clock-names = "ref_clk", "aper_clk";
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reg = <0xE0001000 0x1000>;
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interrupts = <0 50 4>;
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clocks = <&uart_clk 1>;
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};
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slcr: slcr@f8000000 {
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@ -69,50 +71,21 @@
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#address-cells = <1>;
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#size-cells = <0>;
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ps_clk: ps_clk {
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#clock-cells = <0>;
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compatible = "fixed-clock";
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/* clock-frequency set in board-specific file */
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clock-output-names = "ps_clk";
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};
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armpll: armpll {
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#clock-cells = <0>;
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compatible = "xlnx,zynq-pll";
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clocks = <&ps_clk>;
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reg = <0x100 0x110>;
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clock-output-names = "armpll";
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};
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ddrpll: ddrpll {
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#clock-cells = <0>;
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compatible = "xlnx,zynq-pll";
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clocks = <&ps_clk>;
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reg = <0x104 0x114>;
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clock-output-names = "ddrpll";
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};
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iopll: iopll {
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#clock-cells = <0>;
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compatible = "xlnx,zynq-pll";
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clocks = <&ps_clk>;
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reg = <0x108 0x118>;
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clock-output-names = "iopll";
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};
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uart_clk: uart_clk {
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clkc: clkc {
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#clock-cells = <1>;
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compatible = "xlnx,zynq-periph-clock";
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clocks = <&iopll &armpll &ddrpll>;
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reg = <0x154>;
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clock-output-names = "uart0_ref_clk",
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"uart1_ref_clk";
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};
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cpu_clk: cpu_clk {
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#clock-cells = <1>;
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compatible = "xlnx,zynq-cpu-clock";
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clocks = <&iopll &armpll &ddrpll>;
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reg = <0x120 0x1C4>;
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clock-output-names = "cpu_6x4x",
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"cpu_3x2x",
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"cpu_2x",
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"cpu_1x";
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compatible = "xlnx,ps7-clkc";
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ps-clk-frequency = <33333333>;
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clock-output-names = "armpll", "ddrpll", "iopll", "cpu_6or4x",
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"cpu_3or2x", "cpu_2x", "cpu_1x", "ddr2x", "ddr3x",
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"dci", "lqspi", "smc", "pcap", "gem0", "gem1",
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"fclk0", "fclk1", "fclk2", "fclk3", "can0", "can1",
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"sdio0", "sdio1", "uart0", "uart1", "spi0", "spi1",
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"dma", "usb0_aper", "usb1_aper", "gem0_aper",
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"gem1_aper", "sdio0_aper", "sdio1_aper",
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"spi0_aper", "spi1_aper", "can0_aper", "can1_aper",
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"i2c0_aper", "i2c1_aper", "uart0_aper", "uart1_aper",
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"gpio_aper", "lqspi_aper", "smc_aper", "swdt",
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"dbg_trc", "dbg_apb";
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};
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};
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};
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@ -121,9 +94,8 @@
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interrupt-parent = <&intc>;
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interrupts = < 0 10 4 0 11 4 0 12 4 >;
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compatible = "cdns,ttc";
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clocks = <&clkc 6>;
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reg = <0xF8001000 0x1000>;
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clocks = <&cpu_clk 3>;
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clock-names = "cpu_1x";
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clock-ranges;
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};
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@ -131,9 +103,8 @@
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interrupt-parent = <&intc>;
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interrupts = < 0 37 4 0 38 4 0 39 4 >;
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compatible = "cdns,ttc";
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clocks = <&clkc 6>;
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reg = <0xF8002000 0x1000>;
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clocks = <&cpu_clk 3>;
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clock-names = "cpu_1x";
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clock-ranges;
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};
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scutimer: scutimer@f8f00600 {
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@ -141,7 +112,7 @@
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interrupts = < 1 13 0x301 >;
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compatible = "arm,cortex-a9-twd-timer";
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reg = < 0xf8f00600 0x20 >;
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clocks = <&cpu_clk 1>;
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clocks = <&clkc 4>;
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} ;
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};
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};
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@ -28,7 +28,3 @@
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};
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};
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&ps_clk {
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clock-frequency = <33333330>;
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};
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@ -117,7 +117,7 @@ int __init zynq_slcr_init(void)
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pr_info("%s mapped to %p\n", np->name, zynq_slcr_base);
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xilinx_zynq_clocks_init(zynq_slcr_base);
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zynq_clock_init(zynq_slcr_base);
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of_node_put(np);
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@ -27,7 +27,7 @@ obj-$(CONFIG_MACH_LOONGSON1) += clk-ls1x.o
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obj-$(CONFIG_ARCH_SUNXI) += sunxi/
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obj-$(CONFIG_ARCH_U8500) += ux500/
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obj-$(CONFIG_ARCH_VT8500) += clk-vt8500.o
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obj-$(CONFIG_ARCH_ZYNQ) += clk-zynq.o
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obj-$(CONFIG_ARCH_ZYNQ) += zynq/
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obj-$(CONFIG_ARCH_TEGRA) += tegra/
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obj-$(CONFIG_PLAT_SAMSUNG) += samsung/
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@ -0,0 +1,3 @@
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# Zynq clock specific Makefile
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obj-$(CONFIG_ARCH_ZYNQ) += clkc.o pll.o
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@ -51,6 +51,8 @@
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#define TTC_CNT_CNTRL_DISABLE_MASK 0x1
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#define TTC_CLK_CNTRL_CSRC_MASK (1 << 5) /* clock source */
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/*
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* Setup the timers to use pre-scaling, using a fixed value for now that will
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* work across most input frequency, but it may need to be more dynamic
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@ -396,8 +398,9 @@ static void __init ttc_timer_init(struct device_node *timer)
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{
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unsigned int irq;
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void __iomem *timer_baseaddr;
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struct clk *clk;
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struct clk *clk_cs, *clk_ce;
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static int initialized;
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int clksel;
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if (initialized)
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return;
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@ -421,14 +424,24 @@ static void __init ttc_timer_init(struct device_node *timer)
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BUG();
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}
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clk = of_clk_get_by_name(timer, "cpu_1x");
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if (IS_ERR(clk)) {
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clksel = __raw_readl(timer_baseaddr + TTC_CLK_CNTRL_OFFSET);
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clksel = !!(clksel & TTC_CLK_CNTRL_CSRC_MASK);
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clk_cs = of_clk_get(timer, clksel);
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if (IS_ERR(clk_cs)) {
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pr_err("ERROR: timer input clock not found\n");
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BUG();
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}
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ttc_setup_clocksource(clk, timer_baseaddr);
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ttc_setup_clockevent(clk, timer_baseaddr + 4, irq);
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clksel = __raw_readl(timer_baseaddr + 4 + TTC_CLK_CNTRL_OFFSET);
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clksel = !!(clksel & TTC_CLK_CNTRL_CSRC_MASK);
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clk_ce = of_clk_get(timer, clksel);
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if (IS_ERR(clk_ce)) {
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pr_err("ERROR: timer input clock not found\n");
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BUG();
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}
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ttc_setup_clocksource(clk_cs, timer_baseaddr);
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ttc_setup_clockevent(clk_ce, timer_baseaddr + 4, irq);
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pr_info("%s #0 at %p, irq=%d\n", timer->name, timer_baseaddr, irq);
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}
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@ -14,6 +14,7 @@
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#include <linux/platform_device.h>
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#include <linux/serial.h>
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#include <linux/serial_core.h>
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#include <linux/slab.h>
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#include <linux/tty.h>
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#include <linux/tty_flip.h>
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#include <linux/console.h>
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@ -138,6 +139,16 @@
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#define XUARTPS_SR_TXFULL 0x00000010 /* TX FIFO full */
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#define XUARTPS_SR_RXTRIG 0x00000001 /* Rx Trigger */
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/**
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* struct xuartps - device data
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* @refclk Reference clock
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* @aperclk APB clock
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*/
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struct xuartps {
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struct clk *refclk;
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struct clk *aperclk;
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};
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/**
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* xuartps_isr - Interrupt handler
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* @irq: Irq number
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@ -936,34 +947,55 @@ static int xuartps_probe(struct platform_device *pdev)
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int rc;
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struct uart_port *port;
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struct resource *res, *res2;
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struct clk *clk;
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struct xuartps *xuartps_data;
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clk = of_clk_get(pdev->dev.of_node, 0);
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if (IS_ERR(clk)) {
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dev_err(&pdev->dev, "no clock specified\n");
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return PTR_ERR(clk);
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xuartps_data = kzalloc(sizeof(*xuartps_data), GFP_KERNEL);
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if (!xuartps_data)
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return -ENOMEM;
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xuartps_data->aperclk = clk_get(&pdev->dev, "aper_clk");
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if (IS_ERR(xuartps_data->aperclk)) {
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dev_err(&pdev->dev, "aper_clk clock not found.\n");
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rc = PTR_ERR(xuartps_data->aperclk);
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goto err_out_free;
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}
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xuartps_data->refclk = clk_get(&pdev->dev, "ref_clk");
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if (IS_ERR(xuartps_data->refclk)) {
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dev_err(&pdev->dev, "ref_clk clock not found.\n");
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rc = PTR_ERR(xuartps_data->refclk);
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goto err_out_clk_put_aper;
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}
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rc = clk_prepare_enable(clk);
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rc = clk_prepare_enable(xuartps_data->aperclk);
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if (rc) {
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dev_err(&pdev->dev, "could not enable clock\n");
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return -EBUSY;
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dev_err(&pdev->dev, "Unable to enable APER clock.\n");
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goto err_out_clk_put;
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}
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rc = clk_prepare_enable(xuartps_data->refclk);
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if (rc) {
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dev_err(&pdev->dev, "Unable to enable device clock.\n");
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goto err_out_clk_dis_aper;
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}
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res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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if (!res)
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return -ENODEV;
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if (!res) {
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rc = -ENODEV;
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goto err_out_clk_disable;
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}
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res2 = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
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if (!res2)
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return -ENODEV;
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if (!res2) {
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rc = -ENODEV;
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goto err_out_clk_disable;
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}
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/* Initialize the port structure */
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port = xuartps_get_port();
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if (!port) {
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dev_err(&pdev->dev, "Cannot get uart_port structure\n");
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return -ENODEV;
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rc = -ENODEV;
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goto err_out_clk_disable;
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} else {
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/* Register the port.
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* This function also registers this device with the tty layer
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@ -972,18 +1004,31 @@ static int xuartps_probe(struct platform_device *pdev)
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port->mapbase = res->start;
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port->irq = res2->start;
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port->dev = &pdev->dev;
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port->uartclk = clk_get_rate(clk);
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port->private_data = clk;
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port->uartclk = clk_get_rate(xuartps_data->refclk);
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port->private_data = xuartps_data;
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dev_set_drvdata(&pdev->dev, port);
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rc = uart_add_one_port(&xuartps_uart_driver, port);
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if (rc) {
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dev_err(&pdev->dev,
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"uart_add_one_port() failed; err=%i\n", rc);
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dev_set_drvdata(&pdev->dev, NULL);
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return rc;
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goto err_out_clk_disable;
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}
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return 0;
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}
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err_out_clk_disable:
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clk_disable_unprepare(xuartps_data->refclk);
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err_out_clk_dis_aper:
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clk_disable_unprepare(xuartps_data->aperclk);
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err_out_clk_put:
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clk_put(xuartps_data->refclk);
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err_out_clk_put_aper:
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clk_put(xuartps_data->aperclk);
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err_out_free:
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kfree(xuartps_data);
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return rc;
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}
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/**
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@ -995,14 +1040,18 @@ static int xuartps_probe(struct platform_device *pdev)
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static int xuartps_remove(struct platform_device *pdev)
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{
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struct uart_port *port = dev_get_drvdata(&pdev->dev);
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struct clk *clk = port->private_data;
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struct xuartps *xuartps_data = port->private_data;
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int rc;
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/* Remove the xuartps port from the serial core */
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rc = uart_remove_one_port(&xuartps_uart_driver, port);
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dev_set_drvdata(&pdev->dev, NULL);
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port->mapbase = 0;
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clk_disable_unprepare(clk);
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clk_disable_unprepare(xuartps_data->refclk);
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clk_disable_unprepare(xuartps_data->aperclk);
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clk_put(xuartps_data->refclk);
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clk_put(xuartps_data->aperclk);
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kfree(xuartps_data);
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return rc;
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}
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@ -1,4 +1,5 @@
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/*
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* Copyright (C) 2013 Xilinx Inc.
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* Copyright (C) 2012 National Instruments
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*
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* This program is free software; you can redistribute it and/or modify
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@ -19,6 +20,11 @@
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#ifndef __LINUX_CLK_ZYNQ_H_
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#define __LINUX_CLK_ZYNQ_H_
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void __init xilinx_zynq_clocks_init(void __iomem *slcr);
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#include <linux/spinlock.h>
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void zynq_clock_init(void __iomem *slcr);
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struct clk *clk_register_zynq_pll(const char *name, const char *parent,
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void __iomem *pll_ctrl, void __iomem *pll_status, u8 lock_index,
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spinlock_t *lock);
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#endif
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