tg3: Move EEE definitions into mdio.h
In commit 52b02d04c8
entitled "tg3: Add
EEE support", Ben Hutchings had commented that the EEE advertisement
register will be in a standard location. This patch moves that
definition into mdio.h and changes the code to use it.
Signed-off-by: Matt Carlson <mcarlson@broadcom.com>
Reviewed-by: Benjamin Li <benli@broadcom.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
Родитель
8fc2f99561
Коммит
3110f5f554
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@ -32,6 +32,7 @@
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#include <linux/etherdevice.h>
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#include <linux/skbuff.h>
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#include <linux/ethtool.h>
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#include <linux/mdio.h>
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#include <linux/mii.h>
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#include <linux/phy.h>
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#include <linux/brcmphy.h>
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@ -1781,7 +1782,8 @@ static void tg3_phy_eee_adjust(struct tg3 *tp, u32 current_link_up)
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tw32(TG3_CPMU_EEE_CTRL, eeectl);
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tg3_phy_cl45_read(tp, 0x7, TG3_CL45_D7_EEERES_STAT, &val);
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tg3_phy_cl45_read(tp, MDIO_MMD_AN,
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TG3_CL45_D7_EEERES_STAT, &val);
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if (val == TG3_CL45_D7_EEERES_STAT_LP_1000T ||
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val == TG3_CL45_D7_EEERES_STAT_LP_100TX)
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@ -2987,16 +2989,14 @@ static void tg3_phy_copper_begin(struct tg3 *tp)
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if (tp->link_config.autoneg == AUTONEG_ENABLE) {
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/* Advertise 100-BaseTX EEE ability */
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if (tp->link_config.advertising &
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(ADVERTISED_100baseT_Half |
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ADVERTISED_100baseT_Full))
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val |= TG3_CL45_D7_EEEADV_CAP_100TX;
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ADVERTISED_100baseT_Full)
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val |= MDIO_AN_EEE_ADV_100TX;
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/* Advertise 1000-BaseT EEE ability */
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if (tp->link_config.advertising &
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(ADVERTISED_1000baseT_Half |
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ADVERTISED_1000baseT_Full))
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val |= TG3_CL45_D7_EEEADV_CAP_1000T;
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ADVERTISED_1000baseT_Full)
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val |= MDIO_AN_EEE_ADV_1000T;
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}
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tg3_phy_cl45_write(tp, 0x7, TG3_CL45_D7_EEEADV_CAP, val);
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tg3_phy_cl45_write(tp, MDIO_MMD_AN, MDIO_AN_EEE_ADV, val);
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/* Turn off SM_DSP clock. */
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val = MII_TG3_AUXCTL_SHDWSEL_AUXCTL |
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@ -2172,9 +2172,6 @@
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#define MII_TG3_TEST1_CRC_EN 0x8000
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/* Clause 45 expansion registers */
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#define TG3_CL45_D7_EEEADV_CAP 0x003c
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#define TG3_CL45_D7_EEEADV_CAP_100TX 0x0002
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#define TG3_CL45_D7_EEEADV_CAP_1000T 0x0004
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#define TG3_CL45_D7_EEERES_STAT 0x803e
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#define TG3_CL45_D7_EEERES_STAT_LP_100TX 0x0002
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#define TG3_CL45_D7_EEERES_STAT_LP_1000T 0x0004
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@ -55,6 +55,7 @@
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#define MDIO_PCS_10GBRT_STAT2 33 /* 10GBASE-R/-T PCS status 2 */
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#define MDIO_AN_10GBT_CTRL 32 /* 10GBASE-T auto-negotiation control */
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#define MDIO_AN_10GBT_STAT 33 /* 10GBASE-T auto-negotiation status */
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#define MDIO_AN_EEE_ADV 60 /* EEE advertisement */
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/* LASI (Link Alarm Status Interrupt) registers, defined by XENPAK MSA. */
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#define MDIO_PMA_LASI_RXCTRL 0x9000 /* RX_ALARM control */
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@ -235,6 +236,10 @@
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#define MDIO_AN_10GBT_STAT_MS 0x4000 /* Master/slave config */
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#define MDIO_AN_10GBT_STAT_MSFLT 0x8000 /* Master/slave config fault */
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/* AN EEE Advertisement register. */
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#define MDIO_AN_EEE_ADV_100TX 0x0002 /* Advertise 100TX EEE cap */
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#define MDIO_AN_EEE_ADV_1000T 0x0004 /* Advertise 1000T EEE cap */
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/* LASI RX_ALARM control/status registers. */
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#define MDIO_PMA_LASI_RX_PHYXSLFLT 0x0001 /* PHY XS RX local fault */
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#define MDIO_PMA_LASI_RX_PCSLFLT 0x0008 /* PCS RX local fault */
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