clk: qcom: handle alpha PLLs with 16bit alpha val registers
Some alpha PLLs have support for only a 16bit programable Alpha Value (as against the default 40bits). Add a flag to handle the 16bit alpha registers Signed-off-by: Rajendra Nayak <rnayak@codeaurora.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
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9f4e627702
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31256f4892
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@ -59,6 +59,7 @@
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*/
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#define ALPHA_REG_BITWIDTH 40
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#define ALPHA_BITWIDTH 32
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#define ALPHA_16BIT_MASK 0xffff
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#define to_clk_alpha_pll(_hw) container_of(to_clk_regmap(_hw), \
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struct clk_alpha_pll, clkr)
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@ -334,9 +335,14 @@ clk_alpha_pll_recalc_rate(struct clk_hw *hw, unsigned long parent_rate)
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regmap_read(pll->clkr.regmap, off + PLL_USER_CTL, &ctl);
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if (ctl & PLL_ALPHA_EN) {
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regmap_read(pll->clkr.regmap, off + PLL_ALPHA_VAL, &low);
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regmap_read(pll->clkr.regmap, off + PLL_ALPHA_VAL_U, &high);
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a = (u64)high << 32 | low;
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a >>= ALPHA_REG_BITWIDTH - ALPHA_BITWIDTH;
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if (pll->flags & SUPPORTS_16BIT_ALPHA) {
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a = low & ALPHA_16BIT_MASK;
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} else {
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regmap_read(pll->clkr.regmap, off + PLL_ALPHA_VAL_U,
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&high);
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a = (u64)high << 32 | low;
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a >>= ALPHA_REG_BITWIDTH - ALPHA_BITWIDTH;
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}
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}
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return alpha_pll_calc_rate(prate, l, a);
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@ -357,11 +363,15 @@ static int clk_alpha_pll_set_rate(struct clk_hw *hw, unsigned long rate,
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return -EINVAL;
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}
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a <<= (ALPHA_REG_BITWIDTH - ALPHA_BITWIDTH);
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regmap_write(pll->clkr.regmap, off + PLL_L_VAL, l);
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regmap_write(pll->clkr.regmap, off + PLL_ALPHA_VAL, a);
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regmap_write(pll->clkr.regmap, off + PLL_ALPHA_VAL_U, a >> 32);
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if (pll->flags & SUPPORTS_16BIT_ALPHA) {
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regmap_write(pll->clkr.regmap, off + PLL_ALPHA_VAL,
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a & ALPHA_16BIT_MASK);
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} else {
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a <<= (ALPHA_REG_BITWIDTH - ALPHA_BITWIDTH);
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regmap_write(pll->clkr.regmap, off + PLL_ALPHA_VAL_U, a >> 32);
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}
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regmap_update_bits(pll->clkr.regmap, off + PLL_USER_CTL,
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PLL_VCO_MASK << PLL_VCO_SHIFT,
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@ -35,6 +35,7 @@ struct clk_alpha_pll {
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const struct pll_vco *vco_table;
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size_t num_vco;
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#define SUPPORTS_OFFLINE_REQ BIT(0)
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#define SUPPORTS_16BIT_ALPHA BIT(1)
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u8 flags;
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struct clk_regmap clkr;
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