ASoC: mt6797: add PCM interface
Signed-off-by: KaiChieh Chuang <kaichieh.chuang@mediatek.com> Signed-off-by: Mark Brown <broonie@kernel.org>
This commit is contained in:
Kai Chieh Chuang
Mark Brown
Родитель
39f56b757c
Коммит
314b355f55
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@ -4,6 +4,7 @@
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snd-soc-mt6797-afe-objs := \
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mt6797-afe-pcm.o \
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mt6797-afe-clk.o \
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mt6797-dai-pcm.o \
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mt6797-dai-adda.o
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obj-$(CONFIG_SND_SOC_MT6797) += snd-soc-mt6797-afe.o
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@ -24,6 +24,8 @@ enum {
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MT6797_MEMIF_MOD_DAI,
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MT6797_MEMIF_NUM,
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MT6797_DAI_ADDA = MT6797_MEMIF_NUM,
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MT6797_DAI_PCM_1,
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MT6797_DAI_PCM_2,
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MT6797_DAI_NUM,
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};
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@ -49,4 +51,5 @@ unsigned int mt6797_rate_transform(struct device *dev,
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/* dai register */
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int mt6797_dai_adda_register(struct mtk_base_afe *afe);
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int mt6797_dai_pcm_register(struct mtk_base_afe *afe);
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#endif
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@ -819,6 +819,7 @@ static int mt6797_afe_pcm_dev_probe(struct platform_device *pdev)
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return -ENOMEM;
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mt6797_dai_adda_register(afe);
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mt6797_dai_pcm_register(afe);
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afe->sub_dais[MT6797_MEMIF_DL1].dai_drivers = mt6797_memif_dai_driver;
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afe->sub_dais[MT6797_MEMIF_DL1].num_dai_drivers =
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@ -0,0 +1,312 @@
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// SPDX-License-Identifier: GPL-2.0
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//
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// MediaTek ALSA SoC Audio DAI I2S Control
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//
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// Copyright (c) 2018 MediaTek Inc.
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// Author: KaiChieh Chuang <kaichieh.chuang@mediatek.com>
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#include <linux/regmap.h>
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#include <sound/pcm_params.h>
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#include "mt6797-afe-common.h"
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#include "mt6797-interconnection.h"
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#include "mt6797-reg.h"
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enum AUD_TX_LCH_RPT {
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AUD_TX_LCH_RPT_NO_REPEAT = 0,
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AUD_TX_LCH_RPT_REPEAT = 1
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};
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enum AUD_VBT_16K_MODE {
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AUD_VBT_16K_MODE_DISABLE = 0,
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AUD_VBT_16K_MODE_ENABLE = 1
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};
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enum AUD_EXT_MODEM {
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AUD_EXT_MODEM_SELECT_INTERNAL = 0,
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AUD_EXT_MODEM_SELECT_EXTERNAL = 1
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};
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enum AUD_PCM_SYNC_TYPE {
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/* bck sync length = 1 */
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AUD_PCM_ONE_BCK_CYCLE_SYNC = 0,
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/* bck sync length = PCM_INTF_CON1[9:13] */
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AUD_PCM_EXTENDED_BCK_CYCLE_SYNC = 1
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};
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enum AUD_BT_MODE {
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AUD_BT_MODE_DUAL_MIC_ON_TX = 0,
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AUD_BT_MODE_SINGLE_MIC_ON_TX = 1
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};
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enum AUD_PCM_AFIFO_SRC {
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/* slave mode & external modem uses different crystal */
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AUD_PCM_AFIFO_ASRC = 0,
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/* slave mode & external modem uses the same crystal */
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AUD_PCM_AFIFO_AFIFO = 1
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};
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enum AUD_PCM_CLOCK_SOURCE {
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AUD_PCM_CLOCK_MASTER_MODE = 0,
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AUD_PCM_CLOCK_SLAVE_MODE = 1
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};
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enum AUD_PCM_WLEN {
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AUD_PCM_WLEN_PCM_32_BCK_CYCLES = 0,
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AUD_PCM_WLEN_PCM_64_BCK_CYCLES = 1
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};
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enum AUD_PCM_MODE {
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AUD_PCM_MODE_PCM_MODE_8K = 0,
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AUD_PCM_MODE_PCM_MODE_16K = 1,
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AUD_PCM_MODE_PCM_MODE_32K = 2,
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AUD_PCM_MODE_PCM_MODE_48K = 3,
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};
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enum AUD_PCM_FMT {
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AUD_PCM_FMT_I2S = 0,
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AUD_PCM_FMT_EIAJ = 1,
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AUD_PCM_FMT_PCM_MODE_A = 2,
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AUD_PCM_FMT_PCM_MODE_B = 3
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};
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enum AUD_BCLK_OUT_INV {
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AUD_BCLK_OUT_INV_NO_INVERSE = 0,
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AUD_BCLK_OUT_INV_INVERSE = 1
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};
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enum AUD_PCM_EN {
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AUD_PCM_EN_DISABLE = 0,
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AUD_PCM_EN_ENABLE = 1
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};
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/* dai component */
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static const struct snd_kcontrol_new mtk_pcm_1_playback_ch1_mix[] = {
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SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH1", AFE_CONN7,
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I_ADDA_UL_CH1, 1, 0),
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SOC_DAPM_SINGLE_AUTODISABLE("DL2_CH1", AFE_CONN7,
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I_DL2_CH1, 1, 0),
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};
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static const struct snd_kcontrol_new mtk_pcm_1_playback_ch2_mix[] = {
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SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH2", AFE_CONN8,
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I_ADDA_UL_CH2, 1, 0),
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SOC_DAPM_SINGLE_AUTODISABLE("DL2_CH2", AFE_CONN8,
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I_DL2_CH2, 1, 0),
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};
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static const struct snd_kcontrol_new mtk_pcm_1_playback_ch4_mix[] = {
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SOC_DAPM_SINGLE_AUTODISABLE("DL1_CH1", AFE_CONN27,
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I_DL1_CH1, 1, 0),
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};
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static const struct snd_kcontrol_new mtk_pcm_2_playback_ch1_mix[] = {
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SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH1", AFE_CONN17,
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I_ADDA_UL_CH1, 1, 0),
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SOC_DAPM_SINGLE_AUTODISABLE("DL2_CH1", AFE_CONN17,
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I_DL2_CH1, 1, 0),
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};
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static const struct snd_kcontrol_new mtk_pcm_2_playback_ch2_mix[] = {
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SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH2", AFE_CONN18,
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I_ADDA_UL_CH2, 1, 0),
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SOC_DAPM_SINGLE_AUTODISABLE("DL2_CH2", AFE_CONN18,
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I_DL2_CH2, 1, 0),
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};
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static const struct snd_kcontrol_new mtk_pcm_2_playback_ch4_mix[] = {
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SOC_DAPM_SINGLE_AUTODISABLE("DL1_CH1", AFE_CONN24,
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I_DL1_CH1, 1, 0),
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};
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static const struct snd_soc_dapm_widget mtk_dai_pcm_widgets[] = {
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/* inter-connections */
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SND_SOC_DAPM_MIXER("PCM_1_PB_CH1", SND_SOC_NOPM, 0, 0,
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mtk_pcm_1_playback_ch1_mix,
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ARRAY_SIZE(mtk_pcm_1_playback_ch1_mix)),
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SND_SOC_DAPM_MIXER("PCM_1_PB_CH2", SND_SOC_NOPM, 0, 0,
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mtk_pcm_1_playback_ch2_mix,
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ARRAY_SIZE(mtk_pcm_1_playback_ch2_mix)),
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SND_SOC_DAPM_MIXER("PCM_1_PB_CH4", SND_SOC_NOPM, 0, 0,
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mtk_pcm_1_playback_ch4_mix,
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ARRAY_SIZE(mtk_pcm_1_playback_ch4_mix)),
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SND_SOC_DAPM_MIXER("PCM_2_PB_CH1", SND_SOC_NOPM, 0, 0,
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mtk_pcm_2_playback_ch1_mix,
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ARRAY_SIZE(mtk_pcm_2_playback_ch1_mix)),
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SND_SOC_DAPM_MIXER("PCM_2_PB_CH2", SND_SOC_NOPM, 0, 0,
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mtk_pcm_2_playback_ch2_mix,
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ARRAY_SIZE(mtk_pcm_2_playback_ch2_mix)),
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SND_SOC_DAPM_MIXER("PCM_2_PB_CH4", SND_SOC_NOPM, 0, 0,
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mtk_pcm_2_playback_ch4_mix,
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ARRAY_SIZE(mtk_pcm_2_playback_ch4_mix)),
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SND_SOC_DAPM_SUPPLY("PCM_1_EN", PCM_INTF_CON1, PCM_EN_SFT, 0,
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NULL, 0),
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SND_SOC_DAPM_SUPPLY("PCM_2_EN", PCM2_INTF_CON, PCM2_EN_SFT, 0,
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NULL, 0),
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SND_SOC_DAPM_INPUT("MD1_TO_AFE"),
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SND_SOC_DAPM_INPUT("MD2_TO_AFE"),
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SND_SOC_DAPM_OUTPUT("AFE_TO_MD1"),
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SND_SOC_DAPM_OUTPUT("AFE_TO_MD2"),
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};
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static const struct snd_soc_dapm_route mtk_dai_pcm_routes[] = {
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{"PCM 1 Playback", NULL, "PCM_1_PB_CH1"},
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{"PCM 1 Playback", NULL, "PCM_1_PB_CH2"},
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{"PCM 1 Playback", NULL, "PCM_1_PB_CH4"},
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{"PCM 2 Playback", NULL, "PCM_2_PB_CH1"},
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{"PCM 2 Playback", NULL, "PCM_2_PB_CH2"},
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{"PCM 2 Playback", NULL, "PCM_2_PB_CH4"},
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{"PCM 1 Playback", NULL, "PCM_1_EN"},
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{"PCM 2 Playback", NULL, "PCM_2_EN"},
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{"PCM 1 Capture", NULL, "PCM_1_EN"},
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{"PCM 2 Capture", NULL, "PCM_2_EN"},
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{"AFE_TO_MD1", NULL, "PCM 2 Playback"},
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{"AFE_TO_MD2", NULL, "PCM 1 Playback"},
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{"PCM 2 Capture", NULL, "MD1_TO_AFE"},
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{"PCM 1 Capture", NULL, "MD2_TO_AFE"},
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{"PCM_1_PB_CH1", "DL2_CH1", "DL2"},
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{"PCM_1_PB_CH2", "DL2_CH2", "DL2"},
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{"PCM_1_PB_CH4", "DL1_CH1", "DL1"},
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{"PCM_2_PB_CH1", "DL2_CH1", "DL2"},
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{"PCM_2_PB_CH2", "DL2_CH2", "DL2"},
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{"PCM_2_PB_CH4", "DL1_CH1", "DL1"},
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};
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/* dai ops */
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static int mtk_dai_pcm_hw_params(struct snd_pcm_substream *substream,
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struct snd_pcm_hw_params *params,
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struct snd_soc_dai *dai)
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{
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struct mtk_base_afe *afe = snd_soc_dai_get_drvdata(dai);
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unsigned int rate = params_rate(params);
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unsigned int rate_reg = mt6797_rate_transform(afe->dev, rate, dai->id);
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unsigned int pcm_con = 0;
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dev_dbg(afe->dev, "%s(), id %d, stream %d, rate %d, rate_reg %d, widget active p %d, c %d\n",
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__func__,
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dai->id,
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substream->stream,
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rate,
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rate_reg,
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dai->playback_widget->active,
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dai->capture_widget->active);
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if (dai->playback_widget->active || dai->capture_widget->active)
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return 0;
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switch (dai->id) {
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case MT6797_DAI_PCM_1:
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pcm_con |= AUD_BCLK_OUT_INV_NO_INVERSE << PCM_BCLK_OUT_INV_SFT;
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pcm_con |= AUD_TX_LCH_RPT_NO_REPEAT << PCM_TX_LCH_RPT_SFT;
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pcm_con |= AUD_VBT_16K_MODE_DISABLE << PCM_VBT_16K_MODE_SFT;
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pcm_con |= AUD_EXT_MODEM_SELECT_INTERNAL << PCM_EXT_MODEM_SFT;
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pcm_con |= 0 << PCM_SYNC_LENGTH_SFT;
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pcm_con |= AUD_PCM_ONE_BCK_CYCLE_SYNC << PCM_SYNC_TYPE_SFT;
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pcm_con |= AUD_BT_MODE_DUAL_MIC_ON_TX << PCM_BT_MODE_SFT;
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pcm_con |= AUD_PCM_AFIFO_AFIFO << PCM_BYP_ASRC_SFT;
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pcm_con |= AUD_PCM_CLOCK_SLAVE_MODE << PCM_SLAVE_SFT;
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pcm_con |= rate_reg << PCM_MODE_SFT;
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pcm_con |= AUD_PCM_FMT_PCM_MODE_B << PCM_FMT_SFT;
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regmap_update_bits(afe->regmap, PCM_INTF_CON1,
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0xfffffffe, pcm_con);
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break;
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case MT6797_DAI_PCM_2:
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pcm_con |= AUD_TX_LCH_RPT_NO_REPEAT << PCM2_TX_LCH_RPT_SFT;
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pcm_con |= AUD_VBT_16K_MODE_DISABLE << PCM2_VBT_16K_MODE_SFT;
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pcm_con |= AUD_BT_MODE_DUAL_MIC_ON_TX << PCM2_BT_MODE_SFT;
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pcm_con |= AUD_PCM_AFIFO_AFIFO << PCM2_AFIFO_SFT;
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pcm_con |= AUD_PCM_WLEN_PCM_32_BCK_CYCLES << PCM2_WLEN_SFT;
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pcm_con |= rate_reg << PCM2_MODE_SFT;
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pcm_con |= AUD_PCM_FMT_PCM_MODE_B << PCM2_FMT_SFT;
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regmap_update_bits(afe->regmap, PCM2_INTF_CON,
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0xfffffffe, pcm_con);
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break;
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default:
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dev_warn(afe->dev, "%s(), id %d not support\n",
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__func__, dai->id);
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return -EINVAL;
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}
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return 0;
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}
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static const struct snd_soc_dai_ops mtk_dai_pcm_ops = {
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.hw_params = mtk_dai_pcm_hw_params,
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};
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/* dai driver */
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#define MTK_PCM_RATES (SNDRV_PCM_RATE_8000 |\
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SNDRV_PCM_RATE_16000 |\
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SNDRV_PCM_RATE_32000 |\
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SNDRV_PCM_RATE_48000)
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#define MTK_PCM_FORMATS (SNDRV_PCM_FMTBIT_S16_LE |\
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SNDRV_PCM_FMTBIT_S24_LE |\
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SNDRV_PCM_FMTBIT_S32_LE)
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static struct snd_soc_dai_driver mtk_dai_pcm_driver[] = {
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{
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.name = "PCM 1",
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.id = MT6797_DAI_PCM_1,
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.playback = {
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.stream_name = "PCM 1 Playback",
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.channels_min = 1,
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.channels_max = 2,
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.rates = MTK_PCM_RATES,
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.formats = MTK_PCM_FORMATS,
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},
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.capture = {
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.stream_name = "PCM 1 Capture",
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.channels_min = 1,
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.channels_max = 2,
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.rates = MTK_PCM_RATES,
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.formats = MTK_PCM_FORMATS,
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},
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.ops = &mtk_dai_pcm_ops,
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.symmetric_rates = 1,
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.symmetric_samplebits = 1,
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},
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{
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.name = "PCM 2",
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.id = MT6797_DAI_PCM_2,
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.playback = {
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.stream_name = "PCM 2 Playback",
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.channels_min = 1,
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.channels_max = 2,
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.rates = MTK_PCM_RATES,
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.formats = MTK_PCM_FORMATS,
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},
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.capture = {
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.stream_name = "PCM 2 Capture",
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.channels_min = 1,
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.channels_max = 2,
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.rates = MTK_PCM_RATES,
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.formats = MTK_PCM_FORMATS,
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},
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.ops = &mtk_dai_pcm_ops,
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.symmetric_rates = 1,
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.symmetric_samplebits = 1,
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},
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};
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int mt6797_dai_pcm_register(struct mtk_base_afe *afe)
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{
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int id = MT6797_DAI_PCM_1;
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afe->sub_dais[id].dai_drivers = mtk_dai_pcm_driver;
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afe->sub_dais[id].num_dai_drivers = ARRAY_SIZE(mtk_dai_pcm_driver);
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afe->sub_dais[id].dapm_widgets = mtk_dai_pcm_widgets;
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afe->sub_dais[id].num_dapm_widgets = ARRAY_SIZE(mtk_dai_pcm_widgets);
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afe->sub_dais[id].dapm_routes = mtk_dai_pcm_routes;
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afe->sub_dais[id].num_dapm_routes = ARRAY_SIZE(mtk_dai_pcm_routes);
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return 0;
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}
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@ -835,4 +835,181 @@
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#define DL1_HD_ALIGN_SFT 0
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#define DL1_HD_ALIGN_MASK 0x1
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#define DL1_HD_ALIGN_MASK_SFT (0x1 << 0)
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/* PCM_INTF_CON1 */
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#define PCM_FIX_VALUE_SEL_SFT 31
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#define PCM_FIX_VALUE_SEL_MASK 0x1
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#define PCM_FIX_VALUE_SEL_MASK_SFT (0x1 << 31)
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#define PCM_BUFFER_LOOPBACK_SFT 30
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#define PCM_BUFFER_LOOPBACK_MASK 0x1
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#define PCM_BUFFER_LOOPBACK_MASK_SFT (0x1 << 30)
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#define PCM_PARALLEL_LOOPBACK_SFT 29
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#define PCM_PARALLEL_LOOPBACK_MASK 0x1
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#define PCM_PARALLEL_LOOPBACK_MASK_SFT (0x1 << 29)
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#define PCM_SERIAL_LOOPBACK_SFT 28
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#define PCM_SERIAL_LOOPBACK_MASK 0x1
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#define PCM_SERIAL_LOOPBACK_MASK_SFT (0x1 << 28)
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#define PCM_DAI_PCM_LOOPBACK_SFT 27
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#define PCM_DAI_PCM_LOOPBACK_MASK 0x1
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#define PCM_DAI_PCM_LOOPBACK_MASK_SFT (0x1 << 27)
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#define PCM_I2S_PCM_LOOPBACK_SFT 26
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#define PCM_I2S_PCM_LOOPBACK_MASK 0x1
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#define PCM_I2S_PCM_LOOPBACK_MASK_SFT (0x1 << 26)
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#define PCM_SYNC_DELSEL_SFT 25
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#define PCM_SYNC_DELSEL_MASK 0x1
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#define PCM_SYNC_DELSEL_MASK_SFT (0x1 << 25)
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#define PCM_TX_LR_SWAP_SFT 24
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#define PCM_TX_LR_SWAP_MASK 0x1
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#define PCM_TX_LR_SWAP_MASK_SFT (0x1 << 24)
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||||
#define PCM_SYNC_OUT_INV_SFT 23
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||||
#define PCM_SYNC_OUT_INV_MASK 0x1
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||||
#define PCM_SYNC_OUT_INV_MASK_SFT (0x1 << 23)
|
||||
#define PCM_BCLK_OUT_INV_SFT 22
|
||||
#define PCM_BCLK_OUT_INV_MASK 0x1
|
||||
#define PCM_BCLK_OUT_INV_MASK_SFT (0x1 << 22)
|
||||
#define PCM_SYNC_IN_INV_SFT 21
|
||||
#define PCM_SYNC_IN_INV_MASK 0x1
|
||||
#define PCM_SYNC_IN_INV_MASK_SFT (0x1 << 21)
|
||||
#define PCM_BCLK_IN_INV_SFT 20
|
||||
#define PCM_BCLK_IN_INV_MASK 0x1
|
||||
#define PCM_BCLK_IN_INV_MASK_SFT (0x1 << 20)
|
||||
#define PCM_TX_LCH_RPT_SFT 19
|
||||
#define PCM_TX_LCH_RPT_MASK 0x1
|
||||
#define PCM_TX_LCH_RPT_MASK_SFT (0x1 << 19)
|
||||
#define PCM_VBT_16K_MODE_SFT 18
|
||||
#define PCM_VBT_16K_MODE_MASK 0x1
|
||||
#define PCM_VBT_16K_MODE_MASK_SFT (0x1 << 18)
|
||||
#define PCM_EXT_MODEM_SFT 17
|
||||
#define PCM_EXT_MODEM_MASK 0x1
|
||||
#define PCM_EXT_MODEM_MASK_SFT (0x1 << 17)
|
||||
#define PCM_24BIT_SFT 16
|
||||
#define PCM_24BIT_MASK 0x1
|
||||
#define PCM_24BIT_MASK_SFT (0x1 << 16)
|
||||
#define PCM_WLEN_SFT 14
|
||||
#define PCM_WLEN_MASK 0x3
|
||||
#define PCM_WLEN_MASK_SFT (0x3 << 14)
|
||||
#define PCM_SYNC_LENGTH_SFT 9
|
||||
#define PCM_SYNC_LENGTH_MASK 0x1f
|
||||
#define PCM_SYNC_LENGTH_MASK_SFT (0x1f << 9)
|
||||
#define PCM_SYNC_TYPE_SFT 8
|
||||
#define PCM_SYNC_TYPE_MASK 0x1
|
||||
#define PCM_SYNC_TYPE_MASK_SFT (0x1 << 8)
|
||||
#define PCM_BT_MODE_SFT 7
|
||||
#define PCM_BT_MODE_MASK 0x1
|
||||
#define PCM_BT_MODE_MASK_SFT (0x1 << 7)
|
||||
#define PCM_BYP_ASRC_SFT 6
|
||||
#define PCM_BYP_ASRC_MASK 0x1
|
||||
#define PCM_BYP_ASRC_MASK_SFT (0x1 << 6)
|
||||
#define PCM_SLAVE_SFT 5
|
||||
#define PCM_SLAVE_MASK 0x1
|
||||
#define PCM_SLAVE_MASK_SFT (0x1 << 5)
|
||||
#define PCM_MODE_SFT 3
|
||||
#define PCM_MODE_MASK 0x3
|
||||
#define PCM_MODE_MASK_SFT (0x3 << 3)
|
||||
#define PCM_FMT_SFT 1
|
||||
#define PCM_FMT_MASK 0x3
|
||||
#define PCM_FMT_MASK_SFT (0x3 << 1)
|
||||
#define PCM_EN_SFT 0
|
||||
#define PCM_EN_MASK 0x1
|
||||
#define PCM_EN_MASK_SFT (0x1 << 0)
|
||||
|
||||
/* PCM_INTF_CON2 */
|
||||
#define PCM1_TX_FIFO_OV_SFT 31
|
||||
#define PCM1_TX_FIFO_OV_MASK 0x1
|
||||
#define PCM1_TX_FIFO_OV_MASK_SFT (0x1 << 31)
|
||||
#define PCM1_RX_FIFO_OV_SFT 30
|
||||
#define PCM1_RX_FIFO_OV_MASK 0x1
|
||||
#define PCM1_RX_FIFO_OV_MASK_SFT (0x1 << 30)
|
||||
#define PCM2_TX_FIFO_OV_SFT 29
|
||||
#define PCM2_TX_FIFO_OV_MASK 0x1
|
||||
#define PCM2_TX_FIFO_OV_MASK_SFT (0x1 << 29)
|
||||
#define PCM2_RX_FIFO_OV_SFT 28
|
||||
#define PCM2_RX_FIFO_OV_MASK 0x1
|
||||
#define PCM2_RX_FIFO_OV_MASK_SFT (0x1 << 28)
|
||||
#define PCM1_SYNC_GLITCH_SFT 27
|
||||
#define PCM1_SYNC_GLITCH_MASK 0x1
|
||||
#define PCM1_SYNC_GLITCH_MASK_SFT (0x1 << 27)
|
||||
#define PCM2_SYNC_GLITCH_SFT 26
|
||||
#define PCM2_SYNC_GLITCH_MASK 0x1
|
||||
#define PCM2_SYNC_GLITCH_MASK_SFT (0x1 << 26)
|
||||
#define PCM1_PCM2_LOOPBACK_SFT 15
|
||||
#define PCM1_PCM2_LOOPBACK_MASK 0x1
|
||||
#define PCM1_PCM2_LOOPBACK_MASK_SFT (0x1 << 15)
|
||||
#define DAI_PCM_LOOPBACK_CH_SFT 13
|
||||
#define DAI_PCM_LOOPBACK_CH_MASK 0x1
|
||||
#define DAI_PCM_LOOPBACK_CH_MASK_SFT (0x1 << 13)
|
||||
#define I2S_PCM_LOOPBACK_CH_SFT 12
|
||||
#define I2S_PCM_LOOPBACK_CH_MASK 0x1
|
||||
#define I2S_PCM_LOOPBACK_CH_MASK_SFT (0x1 << 12)
|
||||
#define PCM_USE_MD3_SFT 8
|
||||
#define PCM_USE_MD3_MASK 0x1
|
||||
#define PCM_USE_MD3_MASK_SFT (0x1 << 8)
|
||||
#define TX_FIX_VALUE_SFT 0
|
||||
#define TX_FIX_VALUE_MASK 0xff
|
||||
#define TX_FIX_VALUE_MASK_SFT (0xff << 0)
|
||||
|
||||
/* PCM2_INTF_CON */
|
||||
#define PCM2_TX_FIX_VALUE_SFT 24
|
||||
#define PCM2_TX_FIX_VALUE_MASK 0xff
|
||||
#define PCM2_TX_FIX_VALUE_MASK_SFT (0xff << 24)
|
||||
#define PCM2_FIX_VALUE_SEL_SFT 23
|
||||
#define PCM2_FIX_VALUE_SEL_MASK 0x1
|
||||
#define PCM2_FIX_VALUE_SEL_MASK_SFT (0x1 << 23)
|
||||
#define PCM2_BUFFER_LOOPBACK_SFT 22
|
||||
#define PCM2_BUFFER_LOOPBACK_MASK 0x1
|
||||
#define PCM2_BUFFER_LOOPBACK_MASK_SFT (0x1 << 22)
|
||||
#define PCM2_PARALLEL_LOOPBACK_SFT 21
|
||||
#define PCM2_PARALLEL_LOOPBACK_MASK 0x1
|
||||
#define PCM2_PARALLEL_LOOPBACK_MASK_SFT (0x1 << 21)
|
||||
#define PCM2_SERIAL_LOOPBACK_SFT 20
|
||||
#define PCM2_SERIAL_LOOPBACK_MASK 0x1
|
||||
#define PCM2_SERIAL_LOOPBACK_MASK_SFT (0x1 << 20)
|
||||
#define PCM2_DAI_PCM_LOOPBACK_SFT 19
|
||||
#define PCM2_DAI_PCM_LOOPBACK_MASK 0x1
|
||||
#define PCM2_DAI_PCM_LOOPBACK_MASK_SFT (0x1 << 19)
|
||||
#define PCM2_I2S_PCM_LOOPBACK_SFT 18
|
||||
#define PCM2_I2S_PCM_LOOPBACK_MASK 0x1
|
||||
#define PCM2_I2S_PCM_LOOPBACK_MASK_SFT (0x1 << 18)
|
||||
#define PCM2_SYNC_DELSEL_SFT 17
|
||||
#define PCM2_SYNC_DELSEL_MASK 0x1
|
||||
#define PCM2_SYNC_DELSEL_MASK_SFT (0x1 << 17)
|
||||
#define PCM2_TX_LR_SWAP_SFT 16
|
||||
#define PCM2_TX_LR_SWAP_MASK 0x1
|
||||
#define PCM2_TX_LR_SWAP_MASK_SFT (0x1 << 16)
|
||||
#define PCM2_SYNC_IN_INV_SFT 15
|
||||
#define PCM2_SYNC_IN_INV_MASK 0x1
|
||||
#define PCM2_SYNC_IN_INV_MASK_SFT (0x1 << 15)
|
||||
#define PCM2_BCLK_IN_INV_SFT 14
|
||||
#define PCM2_BCLK_IN_INV_MASK 0x1
|
||||
#define PCM2_BCLK_IN_INV_MASK_SFT (0x1 << 14)
|
||||
#define PCM2_TX_LCH_RPT_SFT 13
|
||||
#define PCM2_TX_LCH_RPT_MASK 0x1
|
||||
#define PCM2_TX_LCH_RPT_MASK_SFT (0x1 << 13)
|
||||
#define PCM2_VBT_16K_MODE_SFT 12
|
||||
#define PCM2_VBT_16K_MODE_MASK 0x1
|
||||
#define PCM2_VBT_16K_MODE_MASK_SFT (0x1 << 12)
|
||||
#define PCM2_LOOPBACK_CH_SEL_SFT 10
|
||||
#define PCM2_LOOPBACK_CH_SEL_MASK 0x3
|
||||
#define PCM2_LOOPBACK_CH_SEL_MASK_SFT (0x3 << 10)
|
||||
#define PCM2_TX2_BT_MODE_SFT 8
|
||||
#define PCM2_TX2_BT_MODE_MASK 0x1
|
||||
#define PCM2_TX2_BT_MODE_MASK_SFT (0x1 << 8)
|
||||
#define PCM2_BT_MODE_SFT 7
|
||||
#define PCM2_BT_MODE_MASK 0x1
|
||||
#define PCM2_BT_MODE_MASK_SFT (0x1 << 7)
|
||||
#define PCM2_AFIFO_SFT 6
|
||||
#define PCM2_AFIFO_MASK 0x1
|
||||
#define PCM2_AFIFO_MASK_SFT (0x1 << 6)
|
||||
#define PCM2_WLEN_SFT 5
|
||||
#define PCM2_WLEN_MASK 0x1
|
||||
#define PCM2_WLEN_MASK_SFT (0x1 << 5)
|
||||
#define PCM2_MODE_SFT 3
|
||||
#define PCM2_MODE_MASK 0x3
|
||||
#define PCM2_MODE_MASK_SFT (0x3 << 3)
|
||||
#define PCM2_FMT_SFT 1
|
||||
#define PCM2_FMT_MASK 0x3
|
||||
#define PCM2_FMT_MASK_SFT (0x3 << 1)
|
||||
#define PCM2_EN_SFT 0
|
||||
#define PCM2_EN_MASK 0x1
|
||||
#define PCM2_EN_MASK_SFT (0x1 << 0)
|
||||
#endif
|
||||
|
|
|
|||
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