ARM/nommu: use the generic dma-direct code for non-coherent devices
Select the right options to just use the generic dma-direct code instead of reimplementing it. Signed-off-by: Christoph Hellwig <hch@lst.de> Tested-by: Dillon Min <dillon.minfei@gmail.com>
This commit is contained in:
Christoph Hellwig
Родитель
faf4ef823a
Коммит
31b089bbc1
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@ -18,8 +18,8 @@ config ARM
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select ARCH_HAS_SET_MEMORY
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select ARCH_HAS_STRICT_KERNEL_RWX if MMU && !XIP_KERNEL
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select ARCH_HAS_STRICT_MODULE_RWX if MMU
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select ARCH_HAS_SYNC_DMA_FOR_DEVICE if SWIOTLB
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select ARCH_HAS_SYNC_DMA_FOR_CPU if SWIOTLB
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select ARCH_HAS_SYNC_DMA_FOR_DEVICE if SWIOTLB || !MMU
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select ARCH_HAS_SYNC_DMA_FOR_CPU if SWIOTLB || !MMU
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select ARCH_HAS_TEARDOWN_DMA_OPS if MMU
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select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST
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select ARCH_HAVE_CUSTOM_GPIO_H
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@ -44,6 +44,7 @@ config ARM
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select CPU_PM if SUSPEND || CPU_IDLE
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select DCACHE_WORD_ACCESS if HAVE_EFFICIENT_UNALIGNED_ACCESS
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select DMA_DECLARE_COHERENT
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select DMA_GLOBAL_POOL if !MMU
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select DMA_OPS
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select DMA_REMAP if MMU
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select EDAC_SUPPORT
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@ -5,12 +5,7 @@
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* Copyright (C) 2000-2004 Russell King
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*/
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#include <linux/export.h>
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#include <linux/mm.h>
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#include <linux/dma-direct.h>
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#include <linux/dma-map-ops.h>
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#include <linux/scatterlist.h>
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#include <asm/cachetype.h>
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#include <asm/cacheflush.h>
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#include <asm/outercache.h>
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@ -18,65 +13,8 @@
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#include "dma.h"
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/*
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* The generic direct mapping code is used if
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* - MMU/MPU is off
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* - cpu is v7m w/o cache support
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* - device is coherent
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* otherwise arm_nommu_dma_ops is used.
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*
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* arm_nommu_dma_ops rely on consistent DMA memory (please, refer to
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* [1] on how to declare such memory).
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*
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* [1] Documentation/devicetree/bindings/reserved-memory/reserved-memory.txt
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*/
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static void *arm_nommu_dma_alloc(struct device *dev, size_t size,
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dma_addr_t *dma_handle, gfp_t gfp,
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unsigned long attrs)
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{
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void *ret = dma_alloc_from_global_coherent(dev, size, dma_handle);
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/*
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* dma_alloc_from_global_coherent() may fail because:
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*
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* - no consistent DMA region has been defined, so we can't
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* continue.
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* - there is no space left in consistent DMA region, so we
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* only can fallback to generic allocator if we are
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* advertised that consistency is not required.
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*/
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WARN_ON_ONCE(ret == NULL);
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return ret;
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}
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static void arm_nommu_dma_free(struct device *dev, size_t size,
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void *cpu_addr, dma_addr_t dma_addr,
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unsigned long attrs)
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{
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int ret = dma_release_from_global_coherent(get_order(size), cpu_addr);
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WARN_ON_ONCE(ret == 0);
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}
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static int arm_nommu_dma_mmap(struct device *dev, struct vm_area_struct *vma,
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void *cpu_addr, dma_addr_t dma_addr, size_t size,
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unsigned long attrs)
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{
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int ret;
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if (dma_mmap_from_global_coherent(vma, cpu_addr, size, &ret))
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return ret;
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if (dma_mmap_from_dev_coherent(dev, vma, cpu_addr, size, &ret))
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return ret;
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return -ENXIO;
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}
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static void __dma_page_cpu_to_dev(phys_addr_t paddr, size_t size,
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enum dma_data_direction dir)
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void arch_sync_dma_for_device(phys_addr_t paddr, size_t size,
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enum dma_data_direction dir)
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{
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dmac_map_area(__va(paddr), size, dir);
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@ -86,8 +24,8 @@ static void __dma_page_cpu_to_dev(phys_addr_t paddr, size_t size,
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outer_clean_range(paddr, paddr + size);
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}
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static void __dma_page_dev_to_cpu(phys_addr_t paddr, size_t size,
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enum dma_data_direction dir)
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void arch_sync_dma_for_cpu(phys_addr_t paddr, size_t size,
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enum dma_data_direction dir)
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{
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if (dir != DMA_TO_DEVICE) {
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outer_inv_range(paddr, paddr + size);
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@ -95,102 +33,6 @@ static void __dma_page_dev_to_cpu(phys_addr_t paddr, size_t size,
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}
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}
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static dma_addr_t arm_nommu_dma_map_page(struct device *dev, struct page *page,
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unsigned long offset, size_t size,
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enum dma_data_direction dir,
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unsigned long attrs)
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{
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dma_addr_t handle = page_to_phys(page) + offset;
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__dma_page_cpu_to_dev(handle, size, dir);
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return handle;
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}
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static void arm_nommu_dma_unmap_page(struct device *dev, dma_addr_t handle,
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size_t size, enum dma_data_direction dir,
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unsigned long attrs)
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{
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__dma_page_dev_to_cpu(handle, size, dir);
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}
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static int arm_nommu_dma_map_sg(struct device *dev, struct scatterlist *sgl,
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int nents, enum dma_data_direction dir,
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unsigned long attrs)
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{
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int i;
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struct scatterlist *sg;
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for_each_sg(sgl, sg, nents, i) {
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sg_dma_address(sg) = sg_phys(sg);
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sg_dma_len(sg) = sg->length;
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__dma_page_cpu_to_dev(sg_dma_address(sg), sg_dma_len(sg), dir);
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}
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return nents;
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}
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static void arm_nommu_dma_unmap_sg(struct device *dev, struct scatterlist *sgl,
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int nents, enum dma_data_direction dir,
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unsigned long attrs)
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{
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struct scatterlist *sg;
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int i;
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for_each_sg(sgl, sg, nents, i)
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__dma_page_dev_to_cpu(sg_dma_address(sg), sg_dma_len(sg), dir);
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}
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static void arm_nommu_dma_sync_single_for_device(struct device *dev,
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dma_addr_t handle, size_t size, enum dma_data_direction dir)
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{
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__dma_page_cpu_to_dev(handle, size, dir);
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}
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static void arm_nommu_dma_sync_single_for_cpu(struct device *dev,
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dma_addr_t handle, size_t size, enum dma_data_direction dir)
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{
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__dma_page_cpu_to_dev(handle, size, dir);
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}
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static void arm_nommu_dma_sync_sg_for_device(struct device *dev, struct scatterlist *sgl,
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int nents, enum dma_data_direction dir)
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{
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struct scatterlist *sg;
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int i;
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for_each_sg(sgl, sg, nents, i)
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__dma_page_cpu_to_dev(sg_dma_address(sg), sg_dma_len(sg), dir);
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}
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static void arm_nommu_dma_sync_sg_for_cpu(struct device *dev, struct scatterlist *sgl,
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int nents, enum dma_data_direction dir)
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{
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struct scatterlist *sg;
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int i;
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for_each_sg(sgl, sg, nents, i)
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__dma_page_dev_to_cpu(sg_dma_address(sg), sg_dma_len(sg), dir);
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}
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const struct dma_map_ops arm_nommu_dma_ops = {
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.alloc = arm_nommu_dma_alloc,
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.free = arm_nommu_dma_free,
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.alloc_pages = dma_direct_alloc_pages,
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.free_pages = dma_direct_free_pages,
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.mmap = arm_nommu_dma_mmap,
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.map_page = arm_nommu_dma_map_page,
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.unmap_page = arm_nommu_dma_unmap_page,
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.map_sg = arm_nommu_dma_map_sg,
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.unmap_sg = arm_nommu_dma_unmap_sg,
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.sync_single_for_device = arm_nommu_dma_sync_single_for_device,
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.sync_single_for_cpu = arm_nommu_dma_sync_single_for_cpu,
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.sync_sg_for_device = arm_nommu_dma_sync_sg_for_device,
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.sync_sg_for_cpu = arm_nommu_dma_sync_sg_for_cpu,
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};
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EXPORT_SYMBOL(arm_nommu_dma_ops);
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void arch_setup_dma_ops(struct device *dev, u64 dma_base, u64 size,
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const struct iommu_ops *iommu, bool coherent)
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{
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@ -201,14 +43,11 @@ void arch_setup_dma_ops(struct device *dev, u64 dma_base, u64 size,
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* enough to check if MPU is in use or not since in absense of
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* MPU system memory map is used.
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*/
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dev->archdata.dma_coherent = (cacheid) ? coherent : true;
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dev->dma_coherent = cacheid ? coherent : true;
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} else {
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/*
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* Assume coherent DMA in case MMU/MPU has not been set up.
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*/
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dev->archdata.dma_coherent = (get_cr() & CR_M) ? coherent : true;
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dev->dma_coherent = (get_cr() & CR_M) ? coherent : true;
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}
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if (!dev->archdata.dma_coherent)
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set_dma_ops(dev, &arm_nommu_dma_ops);
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}
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