V4L/DVB (7464): Convert driver to use a single SRAM memory map
This reduces the memory footprint and removes the need to manually configure each map, which lead to a bug where the Fusion EXP 5 board broke for a while. This also fixes digital support again for the DViCO FusionHDTV5Express. Signed-off-by: Steven Toth <stoth@hauppauge.com> Signed-off-by: Mauro Carvalho Chehab <mchehab@infradead.org>
This commit is contained in:
Steven Toth
Mauro Carvalho Chehab
Родитель
1a002ebf60
Коммит
31c8cc9742
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@ -56,137 +56,6 @@ LIST_HEAD(cx23885_devlist);
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#define NO_SYNC_LINE (-1U)
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/*
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* CX23885 Assumptions
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* 1 line = 16 bytes of CDT
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* cmds size = 80
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* cdt size = 16 * linesize
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* iqsize = 64
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* maxlines = 6
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*
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* Address Space:
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* 0x00000000 0x00008fff FIFO clusters
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* 0x00010000 0x000104af Channel Management Data Structures
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* 0x000104b0 0x000104ff Free
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* 0x00010500 0x000108bf 15 channels * iqsize
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* 0x000108c0 0x000108ff Free
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* 0x00010900 0x00010e9f IQ's + Cluster Descriptor Tables
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* 15 channels * (iqsize + (maxlines * linesize))
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* 0x00010ea0 0x00010xxx Free
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*/
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static struct sram_channel cx23885_sram_channels[] = {
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[SRAM_CH01] = {
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.name = "VID A",
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.cmds_start = 0x10000,
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.ctrl_start = 0x105b0,
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.cdt = 0x107b0,
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.fifo_start = 0x40,
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.fifo_size = 0x2800,
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.ptr1_reg = DMA1_PTR1,
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.ptr2_reg = DMA1_PTR2,
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.cnt1_reg = DMA1_CNT1,
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.cnt2_reg = DMA1_CNT2,
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.jumponly = 1,
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},
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[SRAM_CH02] = {
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.name = "ch2",
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.cmds_start = 0x0,
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.ctrl_start = 0x0,
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.cdt = 0x0,
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.fifo_start = 0x0,
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.fifo_size = 0x0,
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.ptr1_reg = DMA2_PTR1,
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.ptr2_reg = DMA2_PTR2,
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.cnt1_reg = DMA2_CNT1,
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.cnt2_reg = DMA2_CNT2,
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},
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[SRAM_CH03] = {
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.name = "TS1 B",
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.cmds_start = 0x100A0,
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.ctrl_start = 0x10630,
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.cdt = 0x10870,
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.fifo_start = 0x5000,
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.fifo_size = 0x1000,
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.ptr1_reg = DMA3_PTR1,
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.ptr2_reg = DMA3_PTR2,
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.cnt1_reg = DMA3_CNT1,
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.cnt2_reg = DMA3_CNT2,
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},
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[SRAM_CH04] = {
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.name = "ch4",
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.cmds_start = 0x0,
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.ctrl_start = 0x0,
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.cdt = 0x0,
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.fifo_start = 0x0,
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.fifo_size = 0x0,
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.ptr1_reg = DMA4_PTR1,
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.ptr2_reg = DMA4_PTR2,
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.cnt1_reg = DMA4_CNT1,
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.cnt2_reg = DMA4_CNT2,
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},
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[SRAM_CH05] = {
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.name = "ch5",
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.cmds_start = 0x0,
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.ctrl_start = 0x0,
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.cdt = 0x0,
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.fifo_start = 0x0,
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.fifo_size = 0x0,
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.ptr1_reg = DMA5_PTR1,
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.ptr2_reg = DMA5_PTR2,
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.cnt1_reg = DMA5_CNT1,
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.cnt2_reg = DMA5_CNT2,
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},
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[SRAM_CH06] = {
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.name = "TS2 C",
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.cmds_start = 0x10140,
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.ctrl_start = 0x10680,
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.cdt = 0x108d0,
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.fifo_start = 0x6000,
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.fifo_size = 0x1000,
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.ptr1_reg = DMA5_PTR1,
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.ptr2_reg = DMA5_PTR2,
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.cnt1_reg = DMA5_CNT1,
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.cnt2_reg = DMA5_CNT2,
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},
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[SRAM_CH07] = {
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.name = "ch7",
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.cmds_start = 0x0,
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.ctrl_start = 0x0,
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.cdt = 0x0,
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.fifo_start = 0x0,
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.fifo_size = 0x0,
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.ptr1_reg = DMA6_PTR1,
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.ptr2_reg = DMA6_PTR2,
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.cnt1_reg = DMA6_CNT1,
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.cnt2_reg = DMA6_CNT2,
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},
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[SRAM_CH08] = {
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.name = "ch8",
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.cmds_start = 0x0,
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.ctrl_start = 0x0,
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.cdt = 0x0,
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.fifo_start = 0x0,
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.fifo_size = 0x0,
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.ptr1_reg = DMA7_PTR1,
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.ptr2_reg = DMA7_PTR2,
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.cnt1_reg = DMA7_CNT1,
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.cnt2_reg = DMA7_CNT2,
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},
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[SRAM_CH09] = {
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.name = "ch9",
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.cmds_start = 0x0,
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.ctrl_start = 0x0,
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.cdt = 0x0,
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.fifo_start = 0x0,
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.fifo_size = 0x0,
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.ptr1_reg = DMA8_PTR1,
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.ptr2_reg = DMA8_PTR2,
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.cnt1_reg = DMA8_CNT1,
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.cnt2_reg = DMA8_CNT2,
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},
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};
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/* FIXME, these allocations will change when
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* analog arrives. The be reviewed.
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* CX23887 Assumptions
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@ -754,6 +623,7 @@ static int cx23885_dev_setup(struct cx23885_dev *dev)
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atomic_inc(&dev->refcount);
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dev->nr = cx23885_devcount++;
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dev->sram_channels = cx23887_sram_channels;
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sprintf(dev->name, "cx23885[%d]", dev->nr);
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mutex_lock(&devlist);
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@ -763,13 +633,11 @@ static int cx23885_dev_setup(struct cx23885_dev *dev)
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/* Configure the internal memory */
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if(dev->pci->device == 0x8880) {
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dev->bridge = CX23885_BRIDGE_887;
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dev->sram_channels = cx23887_sram_channels;
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/* Apply a sensible clock frequency for the PCIe bridge */
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dev->clk_freq = 25000000;
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} else
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if(dev->pci->device == 0x8852) {
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dev->bridge = CX23885_BRIDGE_885;
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dev->sram_channels = cx23885_sram_channels;
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/* Apply a sensible clock frequency for the PCIe bridge */
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dev->clk_freq = 28000000;
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} else
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