[SPARC32]: clean include/asm-sparc/irq.h
Move stuff used only by arch/sparc/kernel/* into arch/sparc/kernel/irq.h and into individual files in there (e.g. macros internal to sun4m_irq.c, etc.) Signed-off-by: Al Viro <viro@zeniv.linux.org.uk> Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
Al Viro
David S. Miller
Родитель
196bffa5dc
Коммит
32231a66b4
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@ -47,6 +47,8 @@
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#include <asm/cacheflush.h>
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#include <asm/irq_regs.h>
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#include "irq.h"
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#ifdef CONFIG_SMP
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#define SMP_NOP2 "nop; nop;\n\t"
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#define SMP_NOP3 "nop; nop; nop;\n\t"
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@ -0,0 +1,48 @@
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#include <asm/btfixup.h>
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BTFIXUPDEF_CALL(void, disable_pil_irq, unsigned int)
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BTFIXUPDEF_CALL(void, enable_pil_irq, unsigned int)
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BTFIXUPDEF_CALL(void, clear_clock_irq, void)
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BTFIXUPDEF_CALL(void, clear_profile_irq, int)
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BTFIXUPDEF_CALL(void, load_profile_irq, int, unsigned int)
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static inline void disable_pil_irq(unsigned int irq)
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{
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BTFIXUP_CALL(disable_pil_irq)(irq);
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}
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static inline void enable_pil_irq(unsigned int irq)
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{
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BTFIXUP_CALL(enable_pil_irq)(irq);
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}
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static inline void clear_clock_irq(void)
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{
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BTFIXUP_CALL(clear_clock_irq)();
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}
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static inline void clear_profile_irq(int irq)
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{
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BTFIXUP_CALL(clear_profile_irq)(irq);
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}
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static inline void load_profile_irq(int cpu, int limit)
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{
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BTFIXUP_CALL(load_profile_irq)(cpu, limit);
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}
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extern void (*sparc_init_timers)(irq_handler_t lvl10_irq);
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extern void claim_ticker14(irq_handler_t irq_handler,
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int irq,
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unsigned int timeout);
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#ifdef CONFIG_SMP
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BTFIXUPDEF_CALL(void, set_cpu_int, int, int)
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BTFIXUPDEF_CALL(void, clear_cpu_int, int, int)
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BTFIXUPDEF_CALL(void, set_irq_udt, int)
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#define set_cpu_int(cpu,level) BTFIXUP_CALL(set_cpu_int)(cpu,level)
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#define clear_cpu_int(cpu,level) BTFIXUP_CALL(clear_cpu_int)(cpu,level)
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#define set_irq_udt(cpu) BTFIXUP_CALL(set_irq_udt)(cpu)
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#endif
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@ -36,6 +36,7 @@
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#include <asm/uaccess.h>
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#include <asm/irq_regs.h>
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#include "irq.h"
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/*
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* I studied different documents and many live PROMs both from 2.30
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@ -33,6 +33,8 @@
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#include <asm/tlbflush.h>
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#include <asm/cpudata.h>
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#include "irq.h"
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int smp_num_cpus = 1;
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volatile unsigned long cpu_callin_map[NR_CPUS] __initdata = {0,};
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unsigned char boot_cpu_id = 0;
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@ -18,6 +18,7 @@
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#include <linux/interrupt.h>
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#include <linux/slab.h>
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#include <linux/init.h>
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#include "irq.h"
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#include <asm/ptrace.h>
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#include <asm/processor.h>
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@ -40,6 +41,20 @@ static struct resource sun4c_timer_eb = { "sun4c_timer" };
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static struct resource sun4c_intr_eb = { "sun4c_intr" };
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#endif
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/*
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* Bit field defines for the interrupt registers on various
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* Sparc machines.
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*/
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/* The sun4c interrupt register. */
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#define SUN4C_INT_ENABLE 0x01 /* Allow interrupts. */
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#define SUN4C_INT_E14 0x80 /* Enable level 14 IRQ. */
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#define SUN4C_INT_E10 0x20 /* Enable level 10 IRQ. */
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#define SUN4C_INT_E8 0x10 /* Enable level 8 IRQ. */
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#define SUN4C_INT_E6 0x08 /* Enable level 6 IRQ. */
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#define SUN4C_INT_E4 0x04 /* Enable level 4 IRQ. */
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#define SUN4C_INT_E1 0x02 /* Enable level 1 IRQ. */
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/* Pointer to the interrupt enable byte
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*
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* Dave Redman (djhr@tadpole.co.uk)
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@ -39,6 +39,8 @@
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#include <asm/cacheflush.h>
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#include <asm/irq_regs.h>
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#include "irq.h"
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/* If you trust current SCSI layer to handle different SCSI IRQs, enable this. I don't trust it... -jj */
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/* #define DISTRIBUTE_IRQS */
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@ -36,6 +36,7 @@
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#include <asm/cacheflush.h>
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#include <asm/cpudata.h>
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#include "irq.h"
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#define IRQ_CROSS_CALL 15
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extern ctxd_t *srmmu_ctx_table_phys;
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@ -38,11 +38,85 @@
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#include <asm/sbus.h>
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#include <asm/cacheflush.h>
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#include "irq.h"
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/* On the sun4m, just like the timers, we have both per-cpu and master
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* interrupt registers.
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*/
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/* These registers are used for sending/receiving irqs from/to
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* different cpu's.
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*/
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struct sun4m_intreg_percpu {
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unsigned int tbt; /* Interrupts still pending for this cpu. */
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/* These next two registers are WRITE-ONLY and are only
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* "on bit" sensitive, "off bits" written have NO affect.
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*/
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unsigned int clear; /* Clear this cpus irqs here. */
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unsigned int set; /* Set this cpus irqs here. */
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unsigned char space[PAGE_SIZE - 12];
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};
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/*
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* djhr
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* Actually the clear and set fields in this struct are misleading..
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* according to the SLAVIO manual (and the same applies for the SEC)
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* the clear field clears bits in the mask which will ENABLE that IRQ
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* the set field sets bits in the mask to DISABLE the IRQ.
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*
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* Also the undirected_xx address in the SLAVIO is defined as
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* RESERVED and write only..
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*
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* DAVEM_NOTE: The SLAVIO only specifies behavior on uniprocessor
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* sun4m machines, for MP the layout makes more sense.
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*/
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struct sun4m_intregs {
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struct sun4m_intreg_percpu cpu_intregs[SUN4M_NCPUS];
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unsigned int tbt; /* IRQ's that are still pending. */
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unsigned int irqs; /* Master IRQ bits. */
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/* Again, like the above, two these registers are WRITE-ONLY. */
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unsigned int clear; /* Clear master IRQ's by setting bits here. */
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unsigned int set; /* Set master IRQ's by setting bits here. */
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/* This register is both READ and WRITE. */
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unsigned int undirected_target; /* Which cpu gets undirected irqs. */
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};
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static unsigned long dummy;
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struct sun4m_intregs *sun4m_interrupts;
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unsigned long *irq_rcvreg = &dummy;
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/* Dave Redman (djhr@tadpole.co.uk)
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* The sun4m interrupt registers.
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*/
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#define SUN4M_INT_ENABLE 0x80000000
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#define SUN4M_INT_E14 0x00000080
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#define SUN4M_INT_E10 0x00080000
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#define SUN4M_HARD_INT(x) (0x000000001 << (x))
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#define SUN4M_SOFT_INT(x) (0x000010000 << (x))
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#define SUN4M_INT_MASKALL 0x80000000 /* mask all interrupts */
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#define SUN4M_INT_MODULE_ERR 0x40000000 /* module error */
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#define SUN4M_INT_M2S_WRITE 0x20000000 /* write buffer error */
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#define SUN4M_INT_ECC 0x10000000 /* ecc memory error */
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#define SUN4M_INT_FLOPPY 0x00400000 /* floppy disk */
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#define SUN4M_INT_MODULE 0x00200000 /* module interrupt */
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#define SUN4M_INT_VIDEO 0x00100000 /* onboard video */
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#define SUN4M_INT_REALTIME 0x00080000 /* system timer */
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#define SUN4M_INT_SCSI 0x00040000 /* onboard scsi */
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#define SUN4M_INT_AUDIO 0x00020000 /* audio/isdn */
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#define SUN4M_INT_ETHERNET 0x00010000 /* onboard ethernet */
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#define SUN4M_INT_SERIAL 0x00008000 /* serial ports */
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#define SUN4M_INT_KBDMS 0x00004000 /* keyboard/mouse */
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#define SUN4M_INT_SBUSBITS 0x00003F80 /* sbus int bits */
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#define SUN4M_INT_SBUS(x) (1 << (x+7))
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#define SUN4M_INT_VME(x) (1 << (x))
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/* These tables only apply for interrupts greater than 15..
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*
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* any intr value below 0x10 is considered to be a soft-int
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@ -31,6 +31,8 @@
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#include <asm/oplib.h>
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#include <asm/cpudata.h>
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#include "irq.h"
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#define IRQ_RESCHEDULE 13
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#define IRQ_STOP_CPU 14
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#define IRQ_CROSS_CALL 15
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@ -25,6 +25,8 @@
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#include <asm/irq.h>
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#include <asm/io.h>
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#include "irq.h"
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extern unsigned long lvl14_save[5];
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static unsigned long *linux_lvl14 = NULL;
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static unsigned long obp_lvl14[4];
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@ -44,6 +44,8 @@
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#include <asm/of_device.h>
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#include <asm/irq_regs.h>
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#include "irq.h"
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DEFINE_SPINLOCK(rtc_lock);
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enum sparc_clock_type sp_clock_typ;
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DEFINE_SPINLOCK(mostek_lock);
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@ -14,9 +14,6 @@
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#include <asm/system.h> /* For SUN4M_NCPUS */
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#include <asm/btfixup.h>
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#define __irq_ino(irq) irq
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#define __irq_pil(irq) irq
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#define NR_IRQS 16
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#define irq_canonicalize(irq) (irq)
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@ -30,11 +27,6 @@
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*/
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BTFIXUPDEF_CALL(void, disable_irq, unsigned int)
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BTFIXUPDEF_CALL(void, enable_irq, unsigned int)
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BTFIXUPDEF_CALL(void, disable_pil_irq, unsigned int)
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BTFIXUPDEF_CALL(void, enable_pil_irq, unsigned int)
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BTFIXUPDEF_CALL(void, clear_clock_irq, void)
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BTFIXUPDEF_CALL(void, clear_profile_irq, int)
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BTFIXUPDEF_CALL(void, load_profile_irq, int, unsigned int)
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static inline void disable_irq_nosync(unsigned int irq)
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{
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@ -51,134 +43,6 @@ static inline void enable_irq(unsigned int irq)
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BTFIXUP_CALL(enable_irq)(irq);
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}
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static inline void disable_pil_irq(unsigned int irq)
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{
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BTFIXUP_CALL(disable_pil_irq)(irq);
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}
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static inline void enable_pil_irq(unsigned int irq)
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{
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BTFIXUP_CALL(enable_pil_irq)(irq);
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}
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static inline void clear_clock_irq(void)
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{
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BTFIXUP_CALL(clear_clock_irq)();
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}
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static inline void clear_profile_irq(int irq)
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{
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BTFIXUP_CALL(clear_profile_irq)(irq);
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}
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static inline void load_profile_irq(int cpu, int limit)
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{
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BTFIXUP_CALL(load_profile_irq)(cpu, limit);
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}
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extern void (*sparc_init_timers)(irq_handler_t lvl10_irq);
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extern void claim_ticker14(irq_handler_t irq_handler,
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int irq,
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unsigned int timeout);
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#ifdef CONFIG_SMP
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BTFIXUPDEF_CALL(void, set_cpu_int, int, int)
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BTFIXUPDEF_CALL(void, clear_cpu_int, int, int)
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BTFIXUPDEF_CALL(void, set_irq_udt, int)
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#define set_cpu_int(cpu,level) BTFIXUP_CALL(set_cpu_int)(cpu,level)
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#define clear_cpu_int(cpu,level) BTFIXUP_CALL(clear_cpu_int)(cpu,level)
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#define set_irq_udt(cpu) BTFIXUP_CALL(set_irq_udt)(cpu)
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#endif
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extern int request_fast_irq(unsigned int irq, irq_handler_t handler, unsigned long flags, __const__ char *devname);
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/* On the sun4m, just like the timers, we have both per-cpu and master
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* interrupt registers.
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*/
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/* These registers are used for sending/receiving irqs from/to
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* different cpu's.
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*/
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struct sun4m_intreg_percpu {
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unsigned int tbt; /* Interrupts still pending for this cpu. */
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/* These next two registers are WRITE-ONLY and are only
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* "on bit" sensitive, "off bits" written have NO affect.
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*/
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unsigned int clear; /* Clear this cpus irqs here. */
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unsigned int set; /* Set this cpus irqs here. */
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unsigned char space[PAGE_SIZE - 12];
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};
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/*
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* djhr
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* Actually the clear and set fields in this struct are misleading..
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* according to the SLAVIO manual (and the same applies for the SEC)
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* the clear field clears bits in the mask which will ENABLE that IRQ
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* the set field sets bits in the mask to DISABLE the IRQ.
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*
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* Also the undirected_xx address in the SLAVIO is defined as
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* RESERVED and write only..
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*
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* DAVEM_NOTE: The SLAVIO only specifies behavior on uniprocessor
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* sun4m machines, for MP the layout makes more sense.
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*/
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struct sun4m_intregs {
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struct sun4m_intreg_percpu cpu_intregs[SUN4M_NCPUS];
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unsigned int tbt; /* IRQ's that are still pending. */
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unsigned int irqs; /* Master IRQ bits. */
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/* Again, like the above, two these registers are WRITE-ONLY. */
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unsigned int clear; /* Clear master IRQ's by setting bits here. */
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unsigned int set; /* Set master IRQ's by setting bits here. */
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/* This register is both READ and WRITE. */
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unsigned int undirected_target; /* Which cpu gets undirected irqs. */
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};
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extern struct sun4m_intregs *sun4m_interrupts;
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/*
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* Bit field defines for the interrupt registers on various
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* Sparc machines.
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*/
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/* The sun4c interrupt register. */
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#define SUN4C_INT_ENABLE 0x01 /* Allow interrupts. */
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#define SUN4C_INT_E14 0x80 /* Enable level 14 IRQ. */
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#define SUN4C_INT_E10 0x20 /* Enable level 10 IRQ. */
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#define SUN4C_INT_E8 0x10 /* Enable level 8 IRQ. */
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#define SUN4C_INT_E6 0x08 /* Enable level 6 IRQ. */
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#define SUN4C_INT_E4 0x04 /* Enable level 4 IRQ. */
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#define SUN4C_INT_E1 0x02 /* Enable level 1 IRQ. */
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/* Dave Redman (djhr@tadpole.co.uk)
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* The sun4m interrupt registers.
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*/
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#define SUN4M_INT_ENABLE 0x80000000
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#define SUN4M_INT_E14 0x00000080
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#define SUN4M_INT_E10 0x00080000
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#define SUN4M_HARD_INT(x) (0x000000001 << (x))
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#define SUN4M_SOFT_INT(x) (0x000010000 << (x))
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#define SUN4M_INT_MASKALL 0x80000000 /* mask all interrupts */
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#define SUN4M_INT_MODULE_ERR 0x40000000 /* module error */
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#define SUN4M_INT_M2S_WRITE 0x20000000 /* write buffer error */
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#define SUN4M_INT_ECC 0x10000000 /* ecc memory error */
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#define SUN4M_INT_FLOPPY 0x00400000 /* floppy disk */
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#define SUN4M_INT_MODULE 0x00200000 /* module interrupt */
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#define SUN4M_INT_VIDEO 0x00100000 /* onboard video */
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#define SUN4M_INT_REALTIME 0x00080000 /* system timer */
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#define SUN4M_INT_SCSI 0x00040000 /* onboard scsi */
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#define SUN4M_INT_AUDIO 0x00020000 /* audio/isdn */
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#define SUN4M_INT_ETHERNET 0x00010000 /* onboard ethernet */
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#define SUN4M_INT_SERIAL 0x00008000 /* serial ports */
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#define SUN4M_INT_KBDMS 0x00004000 /* keyboard/mouse */
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#define SUN4M_INT_SBUSBITS 0x00003F80 /* sbus int bits */
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#define SUN4M_INT_SBUS(x) (1 << (x+7))
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#define SUN4M_INT_VME(x) (1 << (x))
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#endif
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