sh: Add SH7785 Highlander board support (R7785RP).
This adds preliminary support for the SH7785-based Highlander board. Some of the Highlander support code is reordered so that most of it can be reused directly. This also plugs in missing SH7785 checks in the places that need it, as this is the first board to support the CPU. Signed-off-by: Paul Mundt <lethal@linux-sh.org>
This commit is contained in:
Paul Mundt
Paul Mundt
Родитель
be782df54c
Коммит
32351a28a7
|
|
@ -197,12 +197,8 @@ config SH_RTS7751R2D
|
|||
Select RTS7751R2D if configuring for a Renesas Technology
|
||||
Sales SH-Graphics board.
|
||||
|
||||
config SH_R7780RP
|
||||
bool "R7780RP-1"
|
||||
select CPU_SUBTYPE_SH7780
|
||||
help
|
||||
Select R7780RP-1 if configuring for a Renesas Solutions
|
||||
HIGHLANDER board.
|
||||
config SH_HIGHLANDER
|
||||
bool "Highlander"
|
||||
|
||||
config SH_EDOSK7705
|
||||
bool "EDOSK7705"
|
||||
|
|
@ -262,6 +258,10 @@ config SH_UNKNOWN
|
|||
|
||||
endchoice
|
||||
|
||||
source "arch/sh/boards/renesas/hs7751rvoip/Kconfig"
|
||||
source "arch/sh/boards/renesas/rts7751r2d/Kconfig"
|
||||
source "arch/sh/boards/renesas/r7780rp/Kconfig"
|
||||
|
||||
source "arch/sh/mm/Kconfig"
|
||||
|
||||
config CF_ENABLER
|
||||
|
|
@ -412,8 +412,9 @@ config CPU_HAS_PTEA
|
|||
|
||||
endmenu
|
||||
|
||||
menu "Timer support"
|
||||
depends on !GENERIC_TIME
|
||||
menu "Timer and clock configuration"
|
||||
|
||||
if !GENERIC_TIME
|
||||
|
||||
config SH_TMU
|
||||
bool "TMU timer support"
|
||||
|
|
@ -436,17 +437,11 @@ config SH_MTU2
|
|||
help
|
||||
This enables the use of the MTU2 as the system timer.
|
||||
|
||||
endmenu
|
||||
|
||||
source "arch/sh/boards/renesas/hs7751rvoip/Kconfig"
|
||||
|
||||
source "arch/sh/boards/renesas/rts7751r2d/Kconfig"
|
||||
|
||||
source "arch/sh/boards/renesas/r7780rp/Kconfig"
|
||||
endif
|
||||
|
||||
config SH_TIMER_IRQ
|
||||
int
|
||||
default "28" if CPU_SUBTYPE_SH7780
|
||||
default "28" if CPU_SUBTYPE_SH7780 || CPU_SUBTYPE_SH7785
|
||||
default "86" if CPU_SUBTYPE_SH7619
|
||||
default "140" if CPU_SUBTYPE_SH7206
|
||||
default "16"
|
||||
|
|
@ -476,7 +471,8 @@ config SH_PCLK_FREQ
|
|||
default "33333333" if CPU_SUBTYPE_SH7300 || CPU_SUBTYPE_SH7770 || \
|
||||
CPU_SUBTYPE_SH7760 || CPU_SUBTYPE_SH7705 || \
|
||||
CPU_SUBTYPE_SH7206
|
||||
default "50000000" if CPU_SUBTYPE_SH7750 || CPU_SUBTYPE_SH7780
|
||||
default "50000000" if CPU_SUBTYPE_SH7750 || CPU_SUBTYPE_SH7780 || \
|
||||
CPU_SUBTYPE_SH7785
|
||||
default "60000000" if CPU_SUBTYPE_SH7751
|
||||
default "66000000" if CPU_SUBTYPE_SH4_202
|
||||
help
|
||||
|
|
@ -491,6 +487,8 @@ config SH_CLK_MD
|
|||
help
|
||||
MD2 - MD0 pin setting.
|
||||
|
||||
endmenu
|
||||
|
||||
menu "CPU Frequency scaling"
|
||||
|
||||
source "drivers/cpufreq/Kconfig"
|
||||
|
|
@ -509,21 +507,6 @@ config SH_CPU_FREQ
|
|||
|
||||
endmenu
|
||||
|
||||
source "arch/sh/drivers/dma/Kconfig"
|
||||
|
||||
source "arch/sh/cchips/Kconfig"
|
||||
|
||||
config HEARTBEAT
|
||||
bool "Heartbeat LED"
|
||||
depends on SH_MPC1211 || SH_SH03 || \
|
||||
SOLUTION_ENGINE || \
|
||||
SH_RTS7751R2D || SH_SH4202_MICRODEV || SH_LANDISK || \
|
||||
SH_R7780RP
|
||||
help
|
||||
Use the power-on LED on your machine as a load meter. The exact
|
||||
behavior is platform-dependent, but normally the flash frequency is
|
||||
a hyperbolic function of the 5-minute load average.
|
||||
|
||||
source "arch/sh/drivers/Kconfig"
|
||||
|
||||
endmenu
|
||||
|
|
|
|||
|
|
@ -102,7 +102,7 @@ machdir-$(CONFIG_SH_HS7751RVOIP) := renesas/hs7751rvoip
|
|||
machdir-$(CONFIG_SH_RTS7751R2D) := renesas/rts7751r2d
|
||||
machdir-$(CONFIG_SH_7751_SYSTEMH) := renesas/systemh
|
||||
machdir-$(CONFIG_SH_EDOSK7705) := renesas/edosk7705
|
||||
machdir-$(CONFIG_SH_R7780RP) := renesas/r7780rp
|
||||
machdir-$(CONFIG_SH_HIGHLANDER) := renesas/r7780rp
|
||||
machdir-$(CONFIG_SH_7710VOIPGW) := renesas/sh7710voipgw
|
||||
machdir-$(CONFIG_SH_SH4202_MICRODEV) := superh/microdev
|
||||
machdir-$(CONFIG_SH_LANDISK) := landisk
|
||||
|
|
|
|||
|
|
@ -1,14 +1,24 @@
|
|||
if SH_R7780RP
|
||||
if SH_HIGHLANDER
|
||||
|
||||
menu "R7780RP options"
|
||||
choice
|
||||
prompt "Highlander options"
|
||||
default SH_R7780MP
|
||||
|
||||
config SH_R7780RP
|
||||
bool "R7780RP-1 board support"
|
||||
select CPU_SUBTYPE_SH7780
|
||||
|
||||
config SH_R7780MP
|
||||
bool "R7780MP board support"
|
||||
default y
|
||||
select CPU_SUBTYPE_SH7780
|
||||
help
|
||||
Selecting this option will enable support for the mass-production
|
||||
version of the R7780RP. If in doubt, say Y.
|
||||
|
||||
endmenu
|
||||
config SH_R7785RP
|
||||
bool "R7785RP board support"
|
||||
select CPU_SUBTYPE_SH7785
|
||||
|
||||
endchoice
|
||||
|
||||
endif
|
||||
|
|
|
|||
|
|
@ -1,7 +1,7 @@
|
|||
#
|
||||
# Makefile for the R7780RP-1 specific parts of the kernel
|
||||
#
|
||||
|
||||
obj-y := setup.o irq.o
|
||||
|
||||
irqinit-y := irq-r7780rp.o
|
||||
irqinit-$(CONFIG_SH_R7785RP) := irq-r7785rp.o
|
||||
obj-$(CONFIG_PUSH_SWITCH) += psw.o
|
||||
obj-y := setup.o irq.o $(irqinit-y)
|
||||
|
|
|
|||
|
|
@ -0,0 +1,21 @@
|
|||
/*
|
||||
* Renesas Solutions Highlander R7780RP-1 Support.
|
||||
*
|
||||
* Copyright (C) 2002 Atom Create Engineering Co., Ltd.
|
||||
* Copyright (C) 2006 Paul Mundt
|
||||
*
|
||||
* This file is subject to the terms and conditions of the GNU General Public
|
||||
* License. See the file "COPYING" in the main directory of this archive
|
||||
* for more details.
|
||||
*/
|
||||
#include <linux/init.h>
|
||||
#include <asm/io.h>
|
||||
#include <asm/r7780rp.h>
|
||||
|
||||
void __init highlander_init_irq(void)
|
||||
{
|
||||
int i;
|
||||
|
||||
for (i = 0; i < 15; i++)
|
||||
make_r7780rp_irq(i);
|
||||
}
|
||||
|
|
@ -0,0 +1,29 @@
|
|||
/*
|
||||
* Renesas Solutions Highlander R7780RP-1 Support.
|
||||
*
|
||||
* Copyright (C) 2002 Atom Create Engineering Co., Ltd.
|
||||
* Copyright (C) 2006 Paul Mundt
|
||||
*
|
||||
* This file is subject to the terms and conditions of the GNU General Public
|
||||
* License. See the file "COPYING" in the main directory of this archive
|
||||
* for more details.
|
||||
*/
|
||||
#include <linux/init.h>
|
||||
#include <asm/io.h>
|
||||
#include <asm/r7780rp.h>
|
||||
|
||||
void __init highlander_init_irq(void)
|
||||
{
|
||||
ctrl_outw(0x0000, PA_IRLSSR1); /* FPGA IRLSSR1(CF_CD clear) */
|
||||
|
||||
/* Setup the FPGA IRL */
|
||||
ctrl_outw(0x0000, PA_IRLPRA); /* FPGA IRLA */
|
||||
ctrl_outw(0xe598, PA_IRLPRB); /* FPGA IRLB */
|
||||
ctrl_outw(0x7060, PA_IRLPRC); /* FPGA IRLC */
|
||||
ctrl_outw(0x0000, PA_IRLPRD); /* FPGA IRLD */
|
||||
ctrl_outw(0x4321, PA_IRLPRE); /* FPGA IRLE */
|
||||
ctrl_outw(0x0000, PA_IRLPRF); /* FPGA IRLF */
|
||||
|
||||
make_r7780rp_irq(1); /* CF card */
|
||||
make_r7780rp_irq(10); /* On-board ethernet */
|
||||
}
|
||||
|
|
@ -14,10 +14,12 @@
|
|||
#include <linux/io.h>
|
||||
#include <asm/r7780rp.h>
|
||||
|
||||
#ifdef CONFIG_SH_R7780MP
|
||||
static int mask_pos[] = {12, 11, 9, 14, 15, 8, 13, 6, 5, 4, 3, 2, 0, 0, 1, 0};
|
||||
#else
|
||||
#ifdef CONFIG_SH_R7780RP
|
||||
static int mask_pos[] = {15, 14, 13, 12, 11, 10, 9, 8, 7, 5, 6, 4, 0, 1, 2, 0};
|
||||
#elif defined(CONFIG_SH_R7780MP)
|
||||
static int mask_pos[] = {12, 11, 9, 14, 15, 8, 13, 6, 5, 4, 3, 2, 0, 0, 1, 0};
|
||||
#elif defined(CONFIG_SH_R7785RP)
|
||||
static int mask_pos[] = {2, 11, 2, 2, 2, 2, 9, 8, 7, 5, 10, 2, 2, 2, 2, 2};
|
||||
#endif
|
||||
|
||||
static void enable_r7780rp_irq(unsigned int irq)
|
||||
|
|
@ -40,17 +42,10 @@ static struct irq_chip r7780rp_irq_chip __read_mostly = {
|
|||
.mask_ack = disable_r7780rp_irq,
|
||||
};
|
||||
|
||||
/*
|
||||
* Initialize IRQ setting
|
||||
*/
|
||||
void __init init_r7780rp_IRQ(void)
|
||||
void make_r7780rp_irq(unsigned int irq)
|
||||
{
|
||||
int i;
|
||||
|
||||
for (i = 0; i < 15; i++) {
|
||||
disable_irq_nosync(i);
|
||||
set_irq_chip_and_handler_name(i, &r7780rp_irq_chip,
|
||||
handle_level_irq, "level");
|
||||
enable_r7780rp_irq(i);
|
||||
}
|
||||
disable_irq_nosync(irq);
|
||||
set_irq_chip_and_handler_name(irq, &r7780rp_irq_chip,
|
||||
handle_level_irq, "level");
|
||||
enable_r7780rp_irq(irq);
|
||||
}
|
||||
|
|
|
|||
|
|
@ -1,10 +1,13 @@
|
|||
/*
|
||||
* arch/sh/boards/renesas/r7780rp/setup.c
|
||||
*
|
||||
* Renesas Solutions Highlander Support.
|
||||
*
|
||||
* Copyright (C) 2002 Atom Create Engineering Co., Ltd.
|
||||
* Copyright (C) 2005 - 2007 Paul Mundt
|
||||
*
|
||||
* Renesas Solutions Highlander R7780RP-1 Support.
|
||||
* This contains support for the R7780RP-1, R7780MP, and R7785RP
|
||||
* Highlander modules.
|
||||
*
|
||||
* This file is subject to the terms and conditions of the GNU General Public
|
||||
* License. See the file "COPYING" in the main directory of this archive
|
||||
|
|
@ -18,32 +21,6 @@
|
|||
#include <asm/clock.h>
|
||||
#include <asm/io.h>
|
||||
|
||||
extern void init_r7780rp_IRQ(void);
|
||||
|
||||
static struct resource m66596_usb_host_resources[] = {
|
||||
[0] = {
|
||||
.start = 0xa4800000,
|
||||
.end = 0xa4ffffff,
|
||||
.flags = IORESOURCE_MEM,
|
||||
},
|
||||
[1] = {
|
||||
.start = 6, /* irq number */
|
||||
.end = 6,
|
||||
.flags = IORESOURCE_IRQ,
|
||||
},
|
||||
};
|
||||
|
||||
static struct platform_device m66596_usb_host_device = {
|
||||
.name = "m66596-hcd",
|
||||
.id = 0,
|
||||
.dev = {
|
||||
.dma_mask = NULL, /* don't use dma */
|
||||
.coherent_dma_mask = 0xffffffff,
|
||||
},
|
||||
.num_resources = ARRAY_SIZE(m66596_usb_host_resources),
|
||||
.resource = m66596_usb_host_resources,
|
||||
};
|
||||
|
||||
static struct resource cf_ide_resources[] = {
|
||||
[0] = {
|
||||
.start = PA_AREA5_IO + 0x1000,
|
||||
|
|
@ -56,10 +33,10 @@ static struct resource cf_ide_resources[] = {
|
|||
.flags = IORESOURCE_MEM,
|
||||
},
|
||||
[2] = {
|
||||
#ifdef CONFIG_SH_R7780MP
|
||||
.start = 1,
|
||||
#else
|
||||
#ifdef CONFIG_SH_R7780RP
|
||||
.start = 4,
|
||||
#else
|
||||
.start = 1,
|
||||
#endif
|
||||
.flags = IORESOURCE_IRQ,
|
||||
},
|
||||
|
|
@ -92,15 +69,18 @@ static struct resource heartbeat_resources[] = {
|
|||
static struct platform_device heartbeat_device = {
|
||||
.name = "heartbeat",
|
||||
.id = -1,
|
||||
|
||||
/* R7785RP has a slightly more sensible FPGA.. */
|
||||
#ifndef CONFIG_SH_R7785RP
|
||||
.dev = {
|
||||
.platform_data = heartbeat_bit_pos,
|
||||
},
|
||||
#endif
|
||||
.num_resources = ARRAY_SIZE(heartbeat_resources),
|
||||
.resource = heartbeat_resources,
|
||||
};
|
||||
|
||||
static struct platform_device *r7780rp_devices[] __initdata = {
|
||||
&m66596_usb_host_device,
|
||||
&cf_ide_device,
|
||||
&heartbeat_device,
|
||||
};
|
||||
|
|
@ -110,6 +90,7 @@ static int __init r7780rp_devices_setup(void)
|
|||
return platform_add_devices(r7780rp_devices,
|
||||
ARRAY_SIZE(r7780rp_devices));
|
||||
}
|
||||
device_initcall(r7780rp_devices_setup);
|
||||
|
||||
/*
|
||||
* Platform specific clocks
|
||||
|
|
@ -140,22 +121,22 @@ static struct clk *r7780rp_clocks[] = {
|
|||
|
||||
static void r7780rp_power_off(void)
|
||||
{
|
||||
#ifdef CONFIG_SH_R7780MP
|
||||
ctrl_outw(0x0001, PA_POFF);
|
||||
#endif
|
||||
if (mach_is_r7780mp() || mach_is_r7785rp())
|
||||
ctrl_outw(0x0001, PA_POFF);
|
||||
}
|
||||
|
||||
/*
|
||||
* Initialize the board
|
||||
*/
|
||||
static void __init r7780rp_setup(char **cmdline_p)
|
||||
static void __init highlander_setup(char **cmdline_p)
|
||||
{
|
||||
u16 ver = ctrl_inw(PA_VERREG);
|
||||
int i;
|
||||
|
||||
device_initcall(r7780rp_devices_setup);
|
||||
|
||||
printk(KERN_INFO "Renesas Solutions Highlander R7780RP-1 support.\n");
|
||||
printk(KERN_INFO "Renesas Solutions Highlander %s support.\n",
|
||||
mach_is_r7780rp() ? "R7780RP-1" :
|
||||
mach_is_r7780mp() ? "R7780MP" :
|
||||
"R7785RP");
|
||||
|
||||
printk(KERN_INFO "Board version: %d (revision %d), "
|
||||
"FPGA version: %d (revision %d)\n",
|
||||
|
|
@ -173,9 +154,10 @@ static void __init r7780rp_setup(char **cmdline_p)
|
|||
}
|
||||
|
||||
ctrl_outw(0x0000, PA_OBLED); /* Clear LED. */
|
||||
#ifndef CONFIG_SH_R7780MP
|
||||
ctrl_outw(0x0001, PA_SDPOW); /* SD Power ON */
|
||||
#endif
|
||||
|
||||
if (mach_is_r7780rp())
|
||||
ctrl_outw(0x0001, PA_SDPOW); /* SD Power ON */
|
||||
|
||||
ctrl_outw(ctrl_inw(PA_IVDRCTL) | 0x01, PA_IVDRCTL); /* Si13112 */
|
||||
|
||||
pm_power_off = r7780rp_power_off;
|
||||
|
|
@ -184,10 +166,10 @@ static void __init r7780rp_setup(char **cmdline_p)
|
|||
/*
|
||||
* The Machine Vector
|
||||
*/
|
||||
struct sh_machine_vector mv_r7780rp __initmv = {
|
||||
.mv_name = "Highlander R7780RP-1",
|
||||
.mv_setup = r7780rp_setup,
|
||||
struct sh_machine_vector mv_highlander __initmv = {
|
||||
.mv_name = "Highlander",
|
||||
.mv_nr_irqs = 109,
|
||||
.mv_init_irq = init_r7780rp_IRQ,
|
||||
.mv_setup = highlander_setup,
|
||||
.mv_init_irq = highlander_init_irq,
|
||||
};
|
||||
ALIAS_MV(r7780rp)
|
||||
ALIAS_MV(highlander)
|
||||
|
|
|
|||
Разница между файлами не показана из-за своего большого размера
Загрузить разницу
|
|
@ -1,5 +1,15 @@
|
|||
source "arch/sh/drivers/dma/Kconfig"
|
||||
source "arch/sh/cchips/Kconfig"
|
||||
|
||||
menu "Additional SuperH Device Drivers"
|
||||
|
||||
config HEARTBEAT
|
||||
bool "Heartbeat LED"
|
||||
help
|
||||
Use the power-on LED on your machine as a load meter. The exact
|
||||
behavior is platform-dependent, but normally the flash frequency is
|
||||
a hyperbolic function of the 5-minute load average.
|
||||
|
||||
config PUSH_SWITCH
|
||||
tristate "Push switch support"
|
||||
help
|
||||
|
|
|
|||
|
|
@ -8,12 +8,13 @@ obj-$(CONFIG_PCI_AUTO) += pci-auto.o
|
|||
obj-$(CONFIG_CPU_SUBTYPE_ST40STB1) += pci-st40.o
|
||||
obj-$(CONFIG_CPU_SUBTYPE_SH7751) += pci-sh7751.o ops-sh4.o
|
||||
obj-$(CONFIG_CPU_SUBTYPE_SH7780) += pci-sh7780.o ops-sh4.o
|
||||
obj-$(CONFIG_CPU_SUBTYPE_SH7785) += pci-sh7780.o ops-sh4.o
|
||||
|
||||
obj-$(CONFIG_SH_DREAMCAST) += ops-dreamcast.o fixups-dreamcast.o \
|
||||
dma-dreamcast.o
|
||||
obj-$(CONFIG_SH_SECUREEDGE5410) += ops-snapgear.o
|
||||
obj-$(CONFIG_SH_RTS7751R2D) += ops-rts7751r2d.o fixups-rts7751r2d.o
|
||||
obj-$(CONFIG_SH_SH03) += ops-sh03.o fixups-sh03.o
|
||||
obj-$(CONFIG_SH_R7780RP) += ops-r7780rp.o fixups-r7780rp.o
|
||||
obj-$(CONFIG_SH_HIGHLANDER) += ops-r7780rp.o fixups-r7780rp.o
|
||||
obj-$(CONFIG_SH_TITAN) += ops-titan.o
|
||||
obj-$(CONFIG_SH_LANDISK) += ops-landisk.o
|
||||
|
|
|
|||
|
|
@ -17,18 +17,35 @@
|
|||
#include <asm/io.h>
|
||||
#include "pci-sh4.h"
|
||||
|
||||
static char r7780rp_irq_tab[] __initdata = {
|
||||
0, 1, 2, 3,
|
||||
};
|
||||
|
||||
static char r7780mp_irq_tab[] __initdata = {
|
||||
65, 66, 67, 68,
|
||||
};
|
||||
|
||||
static char r7785rp_irq_tab[][4] __initdata = {
|
||||
{ 65, 66, 67, 68 }, /* INT ABCD */
|
||||
{ 66, 67, 68, 65 }, /* INT BCDA */
|
||||
{ 67, 68, 65, 66 }, /* INT CDAB */
|
||||
{ 68, 65, 66, 67 }, /* INT DABC */
|
||||
{ 64, 64, 64, 64 }, /* PCI Host */
|
||||
};
|
||||
|
||||
int __init pcibios_map_platform_irq(struct pci_dev *pdev, u8 slot, u8 pin)
|
||||
{
|
||||
switch (slot) {
|
||||
case 0: return IRQ_PCISLOT1; /* PCI Interrupt #1 */
|
||||
case 1: return IRQ_PCISLOT2; /* PCI Interrupt #2 */
|
||||
case 2: return IRQ_PCISLOT3; /* PCI Interrupt #3 */
|
||||
case 3: return IRQ_PCISLOT4; /* PCI Interrupt E4 */
|
||||
default:
|
||||
printk(KERN_ERR "PCI: Bad IRQ mapping "
|
||||
"request for slot %d, func %d\n", slot, pin-1);
|
||||
return -1;
|
||||
}
|
||||
if (mach_is_r7780rp())
|
||||
return r7780rp_irq_tab[slot];
|
||||
if (mach_is_r7780mp())
|
||||
return r7780mp_irq_tab[slot];
|
||||
if (mach_is_r7785rp())
|
||||
return r7785rp_irq_tab[slot][pin];
|
||||
|
||||
printk(KERN_ERR "PCI: Bad IRQ mapping "
|
||||
"request for slot %d, func %d\n", slot, pin-1);
|
||||
|
||||
return -1;
|
||||
}
|
||||
|
||||
static struct resource sh7780_io_resource = {
|
||||
|
|
|
|||
|
|
@ -1,7 +1,7 @@
|
|||
#ifndef __PCI_SH4_H
|
||||
#define __PCI_SH4_H
|
||||
|
||||
#ifdef CONFIG_CPU_SUBTYPE_SH7780
|
||||
#if defined(CONFIG_CPU_SUBTYPE_SH7780) || defined(CONFIG_CPU_SUBTYPE_SH7785)
|
||||
#include "pci-sh7780.h"
|
||||
#else
|
||||
#include "pci-sh7751.h"
|
||||
|
|
|
|||
|
|
@ -48,7 +48,7 @@
|
|||
static int __init sh7780_pci_init(void)
|
||||
{
|
||||
unsigned int id;
|
||||
int ret;
|
||||
int ret, match = 0;
|
||||
|
||||
pr_debug("PCI: Starting intialization.\n");
|
||||
|
||||
|
|
@ -56,8 +56,17 @@ static int __init sh7780_pci_init(void)
|
|||
|
||||
/* check for SH7780/SH7780R hardware */
|
||||
id = pci_read_reg(SH7780_PCIVID);
|
||||
if ((id != ((SH7780_DEVICE_ID << 16) | SH7780_VENDOR_ID)) &&
|
||||
(id != ((SH7781_DEVICE_ID << 16) | SH7780_VENDOR_ID))) {
|
||||
if ((id & 0xffff) == SH7780_VENDOR_ID) {
|
||||
switch ((id >> 16) & 0xffff) {
|
||||
case SH7780_DEVICE_ID:
|
||||
case SH7781_DEVICE_ID:
|
||||
case SH7785_DEVICE_ID:
|
||||
match = 1;
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
if (unlikely(!match)) {
|
||||
printk(KERN_ERR "PCI: This is not an SH7780 (%x)\n", id);
|
||||
return -ENODEV;
|
||||
}
|
||||
|
|
@ -138,7 +147,7 @@ int __init sh7780_pcic_init(struct sh4_pci_address_map *map)
|
|||
* DMA interrupts...
|
||||
*/
|
||||
|
||||
#ifdef CONFIG_SH_R7780RP
|
||||
#ifdef CONFIG_SH_HIGHLANDER
|
||||
pci_fixup_pcic();
|
||||
#endif
|
||||
|
||||
|
|
|
|||
|
|
@ -14,8 +14,9 @@
|
|||
|
||||
/* Platform Specific Values */
|
||||
#define SH7780_VENDOR_ID 0x1912
|
||||
#define SH7780_DEVICE_ID 0x0002
|
||||
#define SH7781_DEVICE_ID 0x0001
|
||||
#define SH7780_DEVICE_ID 0x0002
|
||||
#define SH7785_DEVICE_ID 0x0007
|
||||
|
||||
/* SH7780 Control Registers */
|
||||
#define SH7780_PCI_VCR0 0xFE000000
|
||||
|
|
|
|||
|
|
@ -18,7 +18,8 @@
|
|||
#define INTC2_BASE 0xfe080000
|
||||
#define INTC2_INTMSK (INTC2_BASE + 0x40)
|
||||
#define INTC2_INTMSKCLR (INTC2_BASE + 0x60)
|
||||
#elif defined(CONFIG_CPU_SUBTYPE_SH7780)
|
||||
#elif defined(CONFIG_CPU_SUBTYPE_SH7780) || \
|
||||
defined(CONFIG_CPU_SUBTYPE_SH7785)
|
||||
#define INTC2_BASE 0xffd40000
|
||||
#define INTC2_INTMSK (INTC2_BASE + 0x38)
|
||||
#define INTC2_INTMSKCLR (INTC2_BASE + 0x3c)
|
||||
|
|
|
|||
|
|
@ -124,6 +124,14 @@ int __init detect_cpu_and_cache_system(void)
|
|||
current_cpu_data.dcache.ways = 4;
|
||||
current_cpu_data.flags |= CPU_HAS_LLSC;
|
||||
break;
|
||||
case 0x3004:
|
||||
case 0x3007:
|
||||
current_cpu_data.type = CPU_SH7785;
|
||||
current_cpu_data.icache.ways = 4;
|
||||
current_cpu_data.dcache.ways = 4;
|
||||
current_cpu_data.flags |= CPU_HAS_FPU | CPU_HAS_PERF_COUNTER |
|
||||
CPU_HAS_LLSC;
|
||||
break;
|
||||
case 0x3008:
|
||||
if (prr == 0xa0) {
|
||||
current_cpu_data.type = CPU_SH7722;
|
||||
|
|
|
|||
|
|
@ -5,6 +5,7 @@
|
|||
# CPU subtype setup
|
||||
obj-$(CONFIG_CPU_SUBTYPE_SH7770) += setup-sh7770.o
|
||||
obj-$(CONFIG_CPU_SUBTYPE_SH7780) += setup-sh7780.o
|
||||
obj-$(CONFIG_CPU_SUBTYPE_SH7785) += setup-sh7785.o
|
||||
obj-$(CONFIG_CPU_SUBTYPE_SH73180) += setup-sh73180.o
|
||||
obj-$(CONFIG_CPU_SUBTYPE_SH7343) += setup-sh7343.o
|
||||
obj-$(CONFIG_CPU_SUBTYPE_SH7722) += setup-sh7722.o
|
||||
|
|
@ -13,6 +14,7 @@ obj-$(CONFIG_CPU_SUBTYPE_SH7722) += setup-sh7722.o
|
|||
clock-$(CONFIG_CPU_SUBTYPE_SH73180) := clock-sh73180.o
|
||||
clock-$(CONFIG_CPU_SUBTYPE_SH7770) := clock-sh7770.o
|
||||
clock-$(CONFIG_CPU_SUBTYPE_SH7780) := clock-sh7780.o
|
||||
clock-$(CONFIG_CPU_SUBTYPE_SH7785) := clock-sh7785.o
|
||||
clock-$(CONFIG_CPU_SUBTYPE_SH7343) := clock-sh7343.o
|
||||
clock-$(CONFIG_CPU_SUBTYPE_SH7722) := clock-sh7343.o
|
||||
|
||||
|
|
|
|||
|
|
@ -0,0 +1,162 @@
|
|||
/*
|
||||
* arch/sh/kernel/cpu/sh4a/clock-sh7785.c
|
||||
*
|
||||
* SH7785 support for the clock framework
|
||||
*
|
||||
* Copyright (C) 2007 Paul Mundt
|
||||
*
|
||||
* This file is subject to the terms and conditions of the GNU General Public
|
||||
* License. See the file "COPYING" in the main directory of this archive
|
||||
* for more details.
|
||||
*/
|
||||
#include <linux/init.h>
|
||||
#include <linux/kernel.h>
|
||||
#include <asm/clock.h>
|
||||
#include <asm/freq.h>
|
||||
#include <asm/io.h>
|
||||
|
||||
static int ifc_divisors[] = { 1, 2, 4, 6 };
|
||||
static int ufc_divisors[] = { 1, 1, 4, 6 };
|
||||
static int sfc_divisors[] = { 1, 1, 4, 6 };
|
||||
static int bfc_divisors[] = { 1, 1, 1, 1, 1, 12, 16, 18,
|
||||
24, 32, 36, 48, 1, 1, 1, 1 };
|
||||
static int mfc_divisors[] = { 1, 1, 4, 6 };
|
||||
static int pfc_divisors[] = { 1, 1, 1, 1, 1, 1, 1, 18,
|
||||
24, 32, 36, 48, 1, 1, 1, 1 };
|
||||
|
||||
static void master_clk_init(struct clk *clk)
|
||||
{
|
||||
clk->rate *= 36;
|
||||
}
|
||||
|
||||
static struct clk_ops sh7785_master_clk_ops = {
|
||||
.init = master_clk_init,
|
||||
};
|
||||
|
||||
static void module_clk_recalc(struct clk *clk)
|
||||
{
|
||||
int idx = (ctrl_inl(FRQMR1) & 0x000f);
|
||||
clk->rate = clk->parent->rate / pfc_divisors[idx];
|
||||
}
|
||||
|
||||
static struct clk_ops sh7785_module_clk_ops = {
|
||||
.recalc = module_clk_recalc,
|
||||
};
|
||||
|
||||
static void bus_clk_recalc(struct clk *clk)
|
||||
{
|
||||
int idx = ((ctrl_inl(FRQMR1) >> 16) & 0x000f);
|
||||
clk->rate = clk->parent->rate / bfc_divisors[idx];
|
||||
}
|
||||
|
||||
static struct clk_ops sh7785_bus_clk_ops = {
|
||||
.recalc = bus_clk_recalc,
|
||||
};
|
||||
|
||||
static void cpu_clk_recalc(struct clk *clk)
|
||||
{
|
||||
int idx = ((ctrl_inl(FRQMR1) >> 28) & 0x0003);
|
||||
clk->rate = clk->parent->rate / ifc_divisors[idx];
|
||||
}
|
||||
|
||||
static struct clk_ops sh7785_cpu_clk_ops = {
|
||||
.recalc = cpu_clk_recalc,
|
||||
};
|
||||
|
||||
static struct clk_ops *sh7785_clk_ops[] = {
|
||||
&sh7785_master_clk_ops,
|
||||
&sh7785_module_clk_ops,
|
||||
&sh7785_bus_clk_ops,
|
||||
&sh7785_cpu_clk_ops,
|
||||
};
|
||||
|
||||
void __init arch_init_clk_ops(struct clk_ops **ops, int idx)
|
||||
{
|
||||
if (idx < ARRAY_SIZE(sh7785_clk_ops))
|
||||
*ops = sh7785_clk_ops[idx];
|
||||
}
|
||||
|
||||
static void shyway_clk_recalc(struct clk *clk)
|
||||
{
|
||||
int idx = ((ctrl_inl(FRQMR1) >> 20) & 0x0003);
|
||||
clk->rate = clk->parent->rate / sfc_divisors[idx];
|
||||
}
|
||||
|
||||
static struct clk_ops sh7785_shyway_clk_ops = {
|
||||
.recalc = shyway_clk_recalc,
|
||||
};
|
||||
|
||||
static struct clk sh7785_shyway_clk = {
|
||||
.name = "shyway_clk",
|
||||
.flags = CLK_ALWAYS_ENABLED,
|
||||
.ops = &sh7785_shyway_clk_ops,
|
||||
};
|
||||
|
||||
static void ddr_clk_recalc(struct clk *clk)
|
||||
{
|
||||
int idx = ((ctrl_inl(FRQMR1) >> 12) & 0x0003);
|
||||
clk->rate = clk->parent->rate / mfc_divisors[idx];
|
||||
}
|
||||
|
||||
static struct clk_ops sh7785_ddr_clk_ops = {
|
||||
.recalc = ddr_clk_recalc,
|
||||
};
|
||||
|
||||
static struct clk sh7785_ddr_clk = {
|
||||
.name = "ddr_clk",
|
||||
.flags = CLK_ALWAYS_ENABLED,
|
||||
.ops = &sh7785_ddr_clk_ops,
|
||||
};
|
||||
|
||||
static void ram_clk_recalc(struct clk *clk)
|
||||
{
|
||||
int idx = ((ctrl_inl(FRQMR1) >> 24) & 0x0003);
|
||||
clk->rate = clk->parent->rate / ufc_divisors[idx];
|
||||
}
|
||||
|
||||
static struct clk_ops sh7785_ram_clk_ops = {
|
||||
.recalc = ram_clk_recalc,
|
||||
};
|
||||
|
||||
static struct clk sh7785_ram_clk = {
|
||||
.name = "ram_clk",
|
||||
.flags = CLK_ALWAYS_ENABLED,
|
||||
.ops = &sh7785_ram_clk_ops,
|
||||
};
|
||||
|
||||
/*
|
||||
* Additional SH7785-specific on-chip clocks that aren't already part of the
|
||||
* clock framework
|
||||
*/
|
||||
static struct clk *sh7785_onchip_clocks[] = {
|
||||
&sh7785_shyway_clk,
|
||||
&sh7785_ddr_clk,
|
||||
&sh7785_ram_clk,
|
||||
};
|
||||
|
||||
static int __init sh7785_clk_init(void)
|
||||
{
|
||||
struct clk *clk = clk_get(NULL, "master_clk");
|
||||
int i;
|
||||
|
||||
for (i = 0; i < ARRAY_SIZE(sh7785_onchip_clocks); i++) {
|
||||
struct clk *clkp = sh7785_onchip_clocks[i];
|
||||
|
||||
clkp->parent = clk;
|
||||
clk_register(clkp);
|
||||
clk_enable(clkp);
|
||||
}
|
||||
|
||||
/*
|
||||
* Now that we have the rest of the clocks registered, we need to
|
||||
* force the parent clock to propagate so that these clocks will
|
||||
* automatically figure out their rate. We cheat by handing the
|
||||
* parent clock its current rate and forcing child propagation.
|
||||
*/
|
||||
clk_set_rate(clk, clk_get_rate(clk));
|
||||
|
||||
clk_put(clk);
|
||||
|
||||
return 0;
|
||||
}
|
||||
arch_initcall(sh7785_clk_init);
|
||||
|
|
@ -0,0 +1,98 @@
|
|||
/*
|
||||
* SH7785 Setup
|
||||
*
|
||||
* Copyright (C) 2007 Paul Mundt
|
||||
*
|
||||
* This file is subject to the terms and conditions of the GNU General Public
|
||||
* License. See the file "COPYING" in the main directory of this archive
|
||||
* for more details.
|
||||
*/
|
||||
#include <linux/platform_device.h>
|
||||
#include <linux/init.h>
|
||||
#include <linux/serial.h>
|
||||
#include <asm/sci.h>
|
||||
|
||||
static struct plat_sci_port sci_platform_data[] = {
|
||||
{
|
||||
.mapbase = 0xffea0000,
|
||||
.flags = UPF_BOOT_AUTOCONF,
|
||||
.type = PORT_SCIF,
|
||||
.irqs = { 40, 41, 43, 42 },
|
||||
}, {
|
||||
.mapbase = 0xffeb0000,
|
||||
.flags = UPF_BOOT_AUTOCONF,
|
||||
.type = PORT_SCIF,
|
||||
.irqs = { 44, 45, 47, 46 },
|
||||
},
|
||||
|
||||
/*
|
||||
* The rest of these all have multiplexed IRQs
|
||||
*/
|
||||
{
|
||||
.mapbase = 0xffec0000,
|
||||
.flags = UPF_BOOT_AUTOCONF,
|
||||
.type = PORT_SCIF,
|
||||
.irqs = { 60, 60, 60, 60 },
|
||||
}, {
|
||||
.mapbase = 0xffed0000,
|
||||
.flags = UPF_BOOT_AUTOCONF,
|
||||
.type = PORT_SCIF,
|
||||
.irqs = { 61, 61, 61, 61 },
|
||||
}, {
|
||||
.mapbase = 0xffee0000,
|
||||
.flags = UPF_BOOT_AUTOCONF,
|
||||
.type = PORT_SCIF,
|
||||
.irqs = { 62, 62, 62, 62 },
|
||||
}, {
|
||||
.mapbase = 0xffef0000,
|
||||
.flags = UPF_BOOT_AUTOCONF,
|
||||
.type = PORT_SCIF,
|
||||
.irqs = { 63, 63, 63, 63 },
|
||||
}, {
|
||||
.flags = 0,
|
||||
}
|
||||
};
|
||||
|
||||
static struct platform_device sci_device = {
|
||||
.name = "sh-sci",
|
||||
.id = -1,
|
||||
.dev = {
|
||||
.platform_data = sci_platform_data,
|
||||
},
|
||||
};
|
||||
|
||||
static struct platform_device *sh7785_devices[] __initdata = {
|
||||
&sci_device,
|
||||
};
|
||||
|
||||
static int __init sh7785_devices_setup(void)
|
||||
{
|
||||
return platform_add_devices(sh7785_devices,
|
||||
ARRAY_SIZE(sh7785_devices));
|
||||
}
|
||||
__initcall(sh7785_devices_setup);
|
||||
|
||||
static struct intc2_data intc2_irq_table[] = {
|
||||
{ 28, 0, 24, 0, 0, 2 }, /* TMU0 */
|
||||
|
||||
{ 40, 8, 24, 0, 3, 3 }, /* SCIF0 ERI */
|
||||
{ 41, 8, 24, 0, 3, 3 }, /* SCIF0 RXI */
|
||||
{ 42, 8, 24, 0, 3, 3 }, /* SCIF0 BRI */
|
||||
{ 43, 8, 24, 0, 3, 3 }, /* SCIF0 TXI */
|
||||
|
||||
{ 76, 8, 16, 0, 4, 3 }, /* SCIF1 ERI */
|
||||
{ 77, 8, 16, 0, 4, 3 }, /* SCIF1 RXI */
|
||||
{ 78, 8, 16, 0, 4, 3 }, /* SCIF1 BRI */
|
||||
{ 79, 8, 16, 0, 4, 3 }, /* SCIF1 TXI */
|
||||
|
||||
{ 64, 0x14, 8, 0, 14, 2 }, /* PCIC0 */
|
||||
{ 65, 0x14, 0, 0, 15, 2 }, /* PCIC1 */
|
||||
{ 66, 0x18, 24, 0, 16, 2 }, /* PCIC2 */
|
||||
{ 67, 0x18, 16, 0, 17, 2 }, /* PCIC3 */
|
||||
{ 68, 0x18, 8, 0, 18, 2 }, /* PCIC4 */
|
||||
};
|
||||
|
||||
void __init init_IRQ_intc2(void)
|
||||
{
|
||||
make_intc2_irq(intc2_irq_table, ARRAY_SIZE(intc2_irq_table));
|
||||
}
|
||||
|
|
@ -148,7 +148,9 @@ static int tmu_timer_init(void)
|
|||
|
||||
/* Start TMU0 */
|
||||
tmu_timer_stop();
|
||||
#if !defined(CONFIG_CPU_SUBTYPE_SH7300) && !defined(CONFIG_CPU_SUBTYPE_SH7760)
|
||||
#if !defined(CONFIG_CPU_SUBTYPE_SH7300) && \
|
||||
!defined(CONFIG_CPU_SUBTYPE_SH7760) && \
|
||||
!defined(CONFIG_CPU_SUBTYPE_SH7785)
|
||||
ctrl_outb(TMU_TOCR_INIT, TMU_TOCR);
|
||||
#endif
|
||||
|
||||
|
|
|
|||
|
|
@ -26,6 +26,7 @@ SH03 SH_SH03
|
|||
LANDISK SH_LANDISK
|
||||
R7780RP SH_R7780RP
|
||||
R7780MP SH_R7780MP
|
||||
R7785RP SH_R7785RP
|
||||
TITAN SH_TITAN
|
||||
SHMIN SH_SHMIN
|
||||
7710VOIPGW SH_7710VOIPGW
|
||||
|
|
|
|||
|
|
@ -351,7 +351,7 @@ static void sci_init_pins_scif(struct uart_port *port, unsigned int cflag)
|
|||
} else {
|
||||
#ifdef CONFIG_CPU_SUBTYPE_SH7343
|
||||
/* Nothing */
|
||||
#elif defined(CONFIG_CPU_SUBTYPE_SH7780)
|
||||
#elif defined(CONFIG_CPU_SUBTYPE_SH7780) || defined(CONFIG_CPU_SUBTYPE_SH7785)
|
||||
ctrl_outw(0x0080, SCSPTR0); /* Set RTS = 1 */
|
||||
#else
|
||||
ctrl_outw(0x0080, SCSPTR2); /* Set RTS = 1 */
|
||||
|
|
@ -361,7 +361,9 @@ static void sci_init_pins_scif(struct uart_port *port, unsigned int cflag)
|
|||
}
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_CPU_SUBTYPE_SH7760) || defined(CONFIG_CPU_SUBTYPE_SH7780)
|
||||
#if defined(CONFIG_CPU_SUBTYPE_SH7760) || \
|
||||
defined(CONFIG_CPU_SUBTYPE_SH7780) || \
|
||||
defined(CONFIG_CPU_SUBTYPE_SH7785)
|
||||
static inline int scif_txroom(struct uart_port *port)
|
||||
{
|
||||
return SCIF_TXROOM_MAX - (sci_in(port, SCTFDR) & 0x7f);
|
||||
|
|
@ -1368,9 +1370,19 @@ static int __devinit sci_probe(struct platform_device *dev)
|
|||
struct plat_sci_port *p = dev->dev.platform_data;
|
||||
int i;
|
||||
|
||||
for (i = 0; p && p->flags != 0 && i < SCI_NPORTS; p++, i++) {
|
||||
for (i = 0; p && p->flags != 0; p++, i++) {
|
||||
struct sci_port *sciport = &sci_ports[i];
|
||||
|
||||
/* Sanity check */
|
||||
if (unlikely(i == SCI_NPORTS)) {
|
||||
dev_notice(&dev->dev, "Attempting to register port "
|
||||
"%d when only %d are available.\n",
|
||||
i+1, SCI_NPORTS);
|
||||
dev_notice(&dev->dev, "Consider bumping "
|
||||
"CONFIG_SERIAL_SH_SCI_NR_UARTS!\n");
|
||||
break;
|
||||
}
|
||||
|
||||
sciport->port.mapbase = p->mapbase;
|
||||
|
||||
/*
|
||||
|
|
|
|||
|
|
@ -140,6 +140,16 @@
|
|||
# define SCIF_ORER 0x0001 /* Overrun error bit */
|
||||
# define SCSCR_INIT(port) 0x3a /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
|
||||
# define SCIF_ONLY
|
||||
#elif defined(CONFIG_CPU_SUBTYPE_SH7785)
|
||||
# define SCSPTR0 0xffea0024 /* 16 bit SCIF */
|
||||
# define SCSPTR1 0xffeb0024 /* 16 bit SCIF */
|
||||
# define SCSPTR2 0xffec0024 /* 16 bit SCIF */
|
||||
# define SCSPTR3 0xffed0024 /* 16 bit SCIF */
|
||||
# define SCSPTR4 0xffee0024 /* 16 bit SCIF */
|
||||
# define SCSPTR5 0xffef0024 /* 16 bit SCIF */
|
||||
# define SCIF_OPER 0x0001 /* Overrun error bit */
|
||||
# define SCSCR_INIT(port) 0x3a /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
|
||||
# define SCIF_ONLY
|
||||
#elif defined(CONFIG_CPU_SUBTYPE_SH7206)
|
||||
# define SCSPTR0 0xfffe8020 /* 16 bit SCIF */
|
||||
# define SCSPTR1 0xfffe8820 /* 16 bit SCIF */
|
||||
|
|
@ -163,7 +173,10 @@
|
|||
#define SCI_CTRL_FLAGS_RIE 0x40 /* all */
|
||||
#define SCI_CTRL_FLAGS_TE 0x20 /* all */
|
||||
#define SCI_CTRL_FLAGS_RE 0x10 /* all */
|
||||
#if defined(CONFIG_CPU_SUBTYPE_SH7750) || defined(CONFIG_CPU_SUBTYPE_SH7751) || defined(CONFIG_CPU_SUBTYPE_SH7780)
|
||||
#if defined(CONFIG_CPU_SUBTYPE_SH7750) || \
|
||||
defined(CONFIG_CPU_SUBTYPE_SH7751) || \
|
||||
defined(CONFIG_CPU_SUBTYPE_SH7780) || \
|
||||
defined(CONFIG_CPU_SUBTYPE_SH7785)
|
||||
#define SCI_CTRL_FLAGS_REIE 0x08 /* 7750 SCIF */
|
||||
#else
|
||||
#define SCI_CTRL_FLAGS_REIE 0
|
||||
|
|
@ -385,7 +398,9 @@ SCIx_FNS(SCxTDR, 0x06, 8, 0x0c, 8, 0x06, 8, 0x0C, 8, 0x03, 8)
|
|||
SCIx_FNS(SCxSR, 0x08, 8, 0x10, 8, 0x08, 16, 0x10, 16, 0x04, 8)
|
||||
SCIx_FNS(SCxRDR, 0x0a, 8, 0x14, 8, 0x0A, 8, 0x14, 8, 0x05, 8)
|
||||
SCIF_FNS(SCFCR, 0x0c, 8, 0x18, 16)
|
||||
#if defined(CONFIG_CPU_SUBTYPE_SH7760) || defined(CONFIG_CPU_SUBTYPE_SH7780)
|
||||
#if defined(CONFIG_CPU_SUBTYPE_SH7760) || \
|
||||
defined(CONFIG_CPU_SUBTYPE_SH7780) || \
|
||||
defined(CONFIG_CPU_SUBTYPE_SH7785)
|
||||
SCIF_FNS(SCFDR, 0x0e, 16, 0x1C, 16)
|
||||
SCIF_FNS(SCTFDR, 0x0e, 16, 0x1C, 16)
|
||||
SCIF_FNS(SCRFDR, 0x0e, 16, 0x20, 16)
|
||||
|
|
@ -576,6 +591,23 @@ static inline int sci_rxd_in(struct uart_port *port)
|
|||
return ctrl_inw(SCSPTR1) & 0x0001 ? 1 : 0; /* SCIF */
|
||||
return 1;
|
||||
}
|
||||
#elif defined(CONFIG_CPU_SUBTYPE_SH7785)
|
||||
static inline int sci_rxd_in(struct uart_port *port)
|
||||
{
|
||||
if (port->mapbase == 0xffea0000)
|
||||
return ctrl_inw(SCSPTR0) & 0x0001 ? 1 : 0; /* SCIF */
|
||||
if (port->mapbase == 0xffeb0000)
|
||||
return ctrl_inw(SCSPTR1) & 0x0001 ? 1 : 0; /* SCIF */
|
||||
if (port->mapbase == 0xffec0000)
|
||||
return ctrl_inw(SCSPTR2) & 0x0001 ? 1 : 0; /* SCIF */
|
||||
if (port->mapbase == 0xffed0000)
|
||||
return ctrl_inw(SCSPTR3) & 0x0001 ? 1 : 0; /* SCIF */
|
||||
if (port->mapbase == 0xffee0000)
|
||||
return ctrl_inw(SCSPTR4) & 0x0001 ? 1 : 0; /* SCIF */
|
||||
if (port->mapbase == 0xffef0000)
|
||||
return ctrl_inw(SCSPTR5) & 0x0001 ? 1 : 0; /* SCIF */
|
||||
return 1;
|
||||
}
|
||||
#elif defined(CONFIG_CPU_SUBTYPE_SH7206)
|
||||
static inline int sci_rxd_in(struct uart_port *port)
|
||||
{
|
||||
|
|
@ -634,7 +666,9 @@ static inline int sci_rxd_in(struct uart_port *port)
|
|||
* -- Mitch Davis - 15 Jul 2000
|
||||
*/
|
||||
|
||||
#if defined(CONFIG_CPU_SUBTYPE_SH7300) || defined(CONFIG_CPU_SUBTYPE_SH7780)
|
||||
#if defined(CONFIG_CPU_SUBTYPE_SH7300) || \
|
||||
defined(CONFIG_CPU_SUBTYPE_SH7780) || \
|
||||
defined(CONFIG_CPU_SUBTYPE_SH7785)
|
||||
#define SCBRR_VALUE(bps, clk) ((clk+16*bps)/(16*bps)-1)
|
||||
#elif defined(CONFIG_CPU_SUBTYPE_SH7705)
|
||||
#define SCBRR_VALUE(bps, clk) (((clk*2)+16*bps)/(32*bps)-1)
|
||||
|
|
|
|||
|
|
@ -14,6 +14,10 @@
|
|||
#define FRQCR 0xa4150000
|
||||
#elif defined(CONFIG_CPU_SUBTYPE_SH7780)
|
||||
#define FRQCR 0xffc80000
|
||||
#elif defined(CONFIG_CPU_SUBTYPE_SH7785)
|
||||
#define FRQCR0 0xffc80000
|
||||
#define FRQCR1 0xffc80004
|
||||
#define FRQMR1 0xffc80014
|
||||
#else
|
||||
#define FRQCR 0xffc00000
|
||||
#endif
|
||||
|
|
|
|||
|
|
@ -35,7 +35,7 @@ extern struct pci_channel board_pci_channels[];
|
|||
/*
|
||||
* I/O routine helpers
|
||||
*/
|
||||
#ifdef CONFIG_CPU_SUBTYPE_SH7780
|
||||
#if defined(CONFIG_CPU_SUBTYPE_SH7780) || defined(CONFIG_CPU_SUBTYPE_SH7785)
|
||||
#define PCI_IO_AREA 0xFE400000
|
||||
#define PCI_IO_SIZE 0x00400000
|
||||
#else
|
||||
|
|
|
|||
|
|
@ -1,17 +1,11 @@
|
|||
#ifndef __ASM_SH_RENESAS_R7780RP_H
|
||||
#define __ASM_SH_RENESAS_R7780RP_H
|
||||
|
||||
/*
|
||||
* linux/include/asm-sh/r7780rp.h
|
||||
*
|
||||
* Copyright (C) 2000 Atom Create Engineering Co., Ltd.
|
||||
*
|
||||
* Renesas Solutions Highlander R7780RP support
|
||||
*/
|
||||
|
||||
/* Box specific addresses. */
|
||||
#if defined(CONFIG_SH_R7780MP)
|
||||
#define PA_BCR 0xa4000000 /* FPGA */
|
||||
#define PA_SDPOW (-1)
|
||||
|
||||
#define PA_IRLMSK (PA_BCR+0x0000) /* Interrupt Mask control */
|
||||
#define PA_IRLMON (PA_BCR+0x0002) /* Interrupt Status control */
|
||||
#define PA_IRLPRI1 (PA_BCR+0x0004) /* Interrupt Priorty 1 */
|
||||
|
|
@ -70,18 +64,12 @@
|
|||
#define PA_POFF (PA_BCR+0x0800) /* System Power Off control */
|
||||
#define PA_PMR (PA_BCR+0x0900) /* */
|
||||
|
||||
#define PA_AX88796L 0xa4100400 /* AX88796L Area */
|
||||
#define PA_SC1602BSLB 0xa6000000 /* SC1602BSLB Area */
|
||||
#define PA_IDE_OFFSET 0x1f0 /* CF IDE Offset */
|
||||
#define AX88796L_IO_BASE 0x1000 /* AX88796L IO Base Address */
|
||||
|
||||
#define IRLCNTR1 (PA_BCR + 0) /* Interrupt Control Register1 */
|
||||
|
||||
#define IRQ_PCISLOT1 65 /* PCI Slot #1 IRQ */
|
||||
#define IRQ_PCISLOT2 66 /* PCI Slot #2 IRQ */
|
||||
#define IRQ_PCISLOT3 67 /* PCI Slot #3 IRQ */
|
||||
#define IRQ_PCISLOT4 68 /* PCI Slot #4 IRQ */
|
||||
// #define IRQ_CFINST 0 /* CF Card Insert IRQ */
|
||||
#define IRQ_TP 2 /* Touch Panel IRQ */
|
||||
#define IRQ_SCI1 3 /* SCI1 IRQ */
|
||||
#define IRQ_SCI0 4 /* SCI0 IRQ */
|
||||
|
|
@ -95,7 +83,7 @@
|
|||
#define IRQ_ONETH 13 /* On board Ethernet IRQ */
|
||||
#define IRQ_PSW 14 /* Push Switch IRQ */
|
||||
|
||||
#else /* R7780RP */
|
||||
#elif defined(CONFIG_SH_R7780RP)
|
||||
|
||||
#define PA_BCR 0xa5000000 /* FPGA */
|
||||
#define PA_IRLMSK (PA_BCR+0x0000) /* Interrupt Mask control */
|
||||
|
|
@ -163,7 +151,55 @@
|
|||
#define IRQ_PSW 13 /* Push Switch IRQ */
|
||||
#define IRQ_ZIGBEE 14 /* Ziggbee IO IRQ */
|
||||
|
||||
#endif /* CONFIG_SH_R7780MP */
|
||||
#elif defined(CONFIG_SH_R7785RP)
|
||||
#define PA_BCR 0xa4000000 /* FPGA */
|
||||
#define PA_SDPOW (-1)
|
||||
|
||||
#define PA_PCISCR (PA_BCR+0x0000)
|
||||
#define PA_IRLPRA (PA_BCR+0x0002)
|
||||
#define PA_IRLPRB (PA_BCR+0x0004)
|
||||
#define PA_IRLPRC (PA_BCR+0x0006)
|
||||
#define PA_IRLPRD (PA_BCR+0x0008)
|
||||
#define IRLCNTR1 (PA_BCR+0x0010)
|
||||
#define PA_IRLPRE (PA_BCR+0x000a)
|
||||
#define PA_IRLPRF (PA_BCR+0x000c)
|
||||
#define PA_EXIRLCR (PA_BCR+0x000e)
|
||||
#define PA_IRLMCR1 (PA_BCR+0x0010)
|
||||
#define PA_IRLMCR2 (PA_BCR+0x0012)
|
||||
#define PA_IRLSSR1 (PA_BCR+0x0014)
|
||||
#define PA_IRLSSR2 (PA_BCR+0x0016)
|
||||
#define PA_CFTCR (PA_BCR+0x0100)
|
||||
#define PA_CFPCR (PA_BCR+0x0102)
|
||||
#define PA_PCICR (PA_BCR+0x0110)
|
||||
#define PA_IVDRCTL (PA_BCR+0x0112)
|
||||
#define PA_IVDRSR (PA_BCR+0x0114)
|
||||
#define PA_PDRSTCR (PA_BCR+0x0116)
|
||||
#define PA_POFF (PA_BCR+0x0120)
|
||||
#define PA_LCDCR (PA_BCR+0x0130)
|
||||
#define PA_TPCR (PA_BCR+0x0140)
|
||||
#define PA_TPCKCR (PA_BCR+0x0142)
|
||||
#define PA_TPRSTR (PA_BCR+0x0144)
|
||||
#define PA_TPXPDR (PA_BCR+0x0146)
|
||||
#define PA_TPYPDR (PA_BCR+0x0148)
|
||||
#define PA_GPIOPFR (PA_BCR+0x0150)
|
||||
#define PA_GPIODR (PA_BCR+0x0152)
|
||||
#define PA_OBLED (PA_BCR+0x0154)
|
||||
#define PA_SWSR (PA_BCR+0x0156)
|
||||
#define PA_VERREG (PA_BCR+0x0158)
|
||||
#define PA_SMCR (PA_BCR+0x0200)
|
||||
#define PA_SMSMADR (PA_BCR+0x0202)
|
||||
#define PA_SMMR (PA_BCR+0x0204)
|
||||
#define PA_SMSADR1 (PA_BCR+0x0206)
|
||||
#define PA_SMSADR32 (PA_BCR+0x0244)
|
||||
#define PA_SMTRDR1 (PA_BCR+0x0246)
|
||||
#define PA_SMTRDR16 (PA_BCR+0x0264)
|
||||
#define PA_CU3MDR (PA_BCR+0x0300)
|
||||
#define PA_CU5MDR (PA_BCR+0x0302)
|
||||
#define PA_MMSR (PA_BCR+0x0400)
|
||||
#endif
|
||||
|
||||
void make_r7780rp_irq(unsigned int irq);
|
||||
void highlander_init_irq(void);
|
||||
|
||||
#define __IO_PREFIX r7780rp
|
||||
#include <asm/io_generic.h>
|
||||
|
|
|
|||
Загрузка…
Ссылка в новой задаче