drm/nouveau: decode PFIFO DMA_PUSHER error codes
Signed-off-by: Marcin Slusarz <marcin.slusarz@gmail.com> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
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4dcf905c84
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3248421670
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@ -379,6 +379,15 @@ out:
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return handled;
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}
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static const char *nv_dma_state_err(u32 state)
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{
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static const char * const desc[] = {
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"NONE", "CALL_SUBR_ACTIVE", "INVALID_MTHD", "RET_SUBR_INACTIVE",
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"INVALID_CMD", "IB_EMPTY"/* NV50+ */, "MEM_FAULT", "UNK"
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};
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return desc[(state >> 29) & 0x7];
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}
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void
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nv04_fifo_isr(struct drm_device *dev)
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{
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@ -460,9 +469,10 @@ nv04_fifo_isr(struct drm_device *dev)
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if (nouveau_ratelimit())
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NV_INFO(dev, "PFIFO_DMA_PUSHER - Ch %d Get 0x%02x%08x "
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"Put 0x%02x%08x IbGet 0x%08x IbPut 0x%08x "
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"State 0x%08x Push 0x%08x\n",
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"State 0x%08x (err: %s) Push 0x%08x\n",
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chid, ho_get, dma_get, ho_put,
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dma_put, ib_get, ib_put, state,
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nv_dma_state_err(state),
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push);
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/* METHOD_COUNT, in DMA_STATE on earlier chipsets */
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@ -476,8 +486,9 @@ nv04_fifo_isr(struct drm_device *dev)
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}
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} else {
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NV_INFO(dev, "PFIFO_DMA_PUSHER - Ch %d Get 0x%08x "
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"Put 0x%08x State 0x%08x Push 0x%08x\n",
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chid, dma_get, dma_put, state, push);
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"Put 0x%08x State 0x%08x (err: %s) Push 0x%08x\n",
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chid, dma_get, dma_put, state,
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nv_dma_state_err(state), push);
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if (dma_get != dma_put)
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nv_wr32(dev, 0x003244, dma_put);
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