ath9k_hw: Add radio retention support for AR9480
Supported calibrations of radio retention table (RTT) are - DC offset - Filter - Peak detect Signed-off-by: Rajkumar Manoharan <rmanohar@qca.qualcomm.com> Signed-off-by: John W. Linville <linville@tuxdriver.com>
This commit is contained in:
Rajkumar Manoharan
John W. Linville
Родитель
1aef40b82c
Коммит
324c74ad64
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@ -21,6 +21,7 @@ ath9k_hw-y:= \
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ar5008_phy.o \
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ar9002_calib.o \
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ar9003_calib.o \
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ar9003_rtt.o \
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calib.o \
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eeprom.o \
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eeprom_def.o \
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@ -17,6 +17,7 @@
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#include "hw.h"
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#include "hw-ops.h"
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#include "ar9003_phy.h"
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#include "ar9003_rtt.h"
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#define MAX_MEASUREMENT MAX_IQCAL_MEASUREMENT
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#define MAX_MAG_DELTA 11
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@ -900,25 +901,81 @@ static void ar9003_hw_tx_iq_cal_reload(struct ath_hw *ah)
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AR_PHY_RX_IQCAL_CORR_B0_LOOPBACK_IQCORR_EN, 0x1);
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}
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static bool ar9003_hw_rtt_restore(struct ath_hw *ah, struct ath9k_channel *chan)
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{
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struct ath9k_rtt_hist *hist;
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u32 *table;
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int i;
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bool restore;
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if (!(ah->caps.hw_caps & ATH9K_HW_CAP_RTT) || !ah->caldata)
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return false;
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hist = &ah->caldata->rtt_hist;
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ar9003_hw_rtt_enable(ah);
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ar9003_hw_rtt_set_mask(ah, 0x10);
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for (i = 0; i < AR9300_MAX_CHAINS; i++) {
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if (!(ah->rxchainmask & (1 << i)))
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continue;
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table = &hist->table[i][hist->num_readings][0];
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ar9003_hw_rtt_load_hist(ah, i, table);
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}
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restore = ar9003_hw_rtt_force_restore(ah);
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ar9003_hw_rtt_disable(ah);
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return restore;
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}
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static bool ar9003_hw_init_cal(struct ath_hw *ah,
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struct ath9k_channel *chan)
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{
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struct ath_common *common = ath9k_hw_common(ah);
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struct ath9k_hw_cal_data *caldata = ah->caldata;
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bool txiqcal_done = false, txclcal_done = false;
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bool is_reusable = true;
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bool is_reusable = true, status = true;
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bool run_rtt_cal = false, run_agc_cal;
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bool rtt = !!(ah->caps.hw_caps & ATH9K_HW_CAP_RTT);
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u32 agc_ctrl = 0, agc_supp_cals = AR_PHY_AGC_CONTROL_OFFSET_CAL |
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AR_PHY_AGC_CONTROL_FLTR_CAL |
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AR_PHY_AGC_CONTROL_PKDET_CAL;
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int i, j;
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u32 cl_idx[AR9300_MAX_CHAINS] = { AR_PHY_CL_TAB_0,
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AR_PHY_CL_TAB_1,
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AR_PHY_CL_TAB_2 };
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if (rtt) {
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if (!ar9003_hw_rtt_restore(ah, chan))
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run_rtt_cal = true;
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ath_dbg(common, ATH_DBG_CALIBRATE, "RTT restore %s\n",
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run_rtt_cal ? "failed" : "succeed");
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}
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run_agc_cal = run_rtt_cal;
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if (run_rtt_cal) {
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ar9003_hw_rtt_enable(ah);
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ar9003_hw_rtt_set_mask(ah, 0x00);
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ar9003_hw_rtt_clear_hist(ah);
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}
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if (rtt && !run_rtt_cal) {
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agc_ctrl = REG_READ(ah, AR_PHY_AGC_CONTROL);
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agc_supp_cals &= agc_ctrl;
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agc_ctrl &= ~(AR_PHY_AGC_CONTROL_OFFSET_CAL |
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AR_PHY_AGC_CONTROL_FLTR_CAL |
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AR_PHY_AGC_CONTROL_PKDET_CAL);
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REG_WRITE(ah, AR_PHY_AGC_CONTROL, agc_ctrl);
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}
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if (ah->enabled_cals & TX_CL_CAL) {
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if (caldata && caldata->done_txclcal_once)
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REG_CLR_BIT(ah, AR_PHY_CL_CAL_CTL,
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AR_PHY_CL_CAL_ENABLE);
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else
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else {
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REG_SET_BIT(ah, AR_PHY_CL_CAL_CTL,
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AR_PHY_CL_CAL_ENABLE);
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run_agc_cal = true;
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}
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}
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if (!(ah->enabled_cals & TX_IQ_CAL))
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@ -940,25 +997,41 @@ static bool ar9003_hw_init_cal(struct ath_hw *ah,
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else
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REG_CLR_BIT(ah, AR_PHY_TX_IQCAL_CONTROL_0,
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AR_PHY_TX_IQCAL_CONTROL_0_ENABLE_TXIQ_CAL);
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txiqcal_done = true;
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txiqcal_done = run_agc_cal = true;
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goto skip_tx_iqcal;
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}
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} else if (caldata && !caldata->done_txiqcal_once)
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run_agc_cal = true;
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txiqcal_done = ar9003_hw_tx_iq_cal_run(ah);
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REG_WRITE(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_DIS);
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udelay(5);
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REG_WRITE(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_EN);
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skip_tx_iqcal:
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/* Calibrate the AGC */
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REG_WRITE(ah, AR_PHY_AGC_CONTROL,
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REG_READ(ah, AR_PHY_AGC_CONTROL) |
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AR_PHY_AGC_CONTROL_CAL);
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/* Poll for offset calibration complete */
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if (!ath9k_hw_wait(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_CAL,
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0, AH_WAIT_TIMEOUT)) {
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if (run_agc_cal) {
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/* Calibrate the AGC */
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REG_WRITE(ah, AR_PHY_AGC_CONTROL,
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REG_READ(ah, AR_PHY_AGC_CONTROL) |
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AR_PHY_AGC_CONTROL_CAL);
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/* Poll for offset calibration complete */
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status = ath9k_hw_wait(ah, AR_PHY_AGC_CONTROL,
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AR_PHY_AGC_CONTROL_CAL,
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0, AH_WAIT_TIMEOUT);
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}
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if (rtt && !run_rtt_cal) {
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agc_ctrl |= agc_supp_cals;
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REG_WRITE(ah, AR_PHY_AGC_CONTROL, agc_ctrl);
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}
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if (!status) {
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if (run_rtt_cal)
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ar9003_hw_rtt_disable(ah);
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ath_dbg(common, ATH_DBG_CALIBRATE,
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"offset calibration failed to complete in 1ms; noisy environment?\n");
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"offset calibration failed to complete in 1ms;"
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"noisy environment?\n");
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return false;
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}
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@ -993,6 +1066,22 @@ skip_tx_iqcal:
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}
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#undef CL_TAB_ENTRY
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if (run_rtt_cal && caldata) {
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struct ath9k_rtt_hist *hist = &caldata->rtt_hist;
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if (is_reusable && (hist->num_readings < RTT_HIST_MAX)) {
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u32 *table;
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for (i = 0; i < AR9300_MAX_CHAINS; i++) {
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if (!(ah->rxchainmask & (1 << i)))
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continue;
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table = &hist->table[i][hist->num_readings][0];
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ar9003_hw_rtt_fill_hist(ah, i, table);
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}
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}
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ar9003_hw_rtt_disable(ah);
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}
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ath9k_hw_loadnf(ah, chan);
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ath9k_hw_start_nfcal(ah, true);
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@ -584,8 +584,6 @@
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(AR_SREV_9485(ah) ? \
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0x3d0 : 0x450) + ((_i) << 2))
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#define AR_PHY_RTT_CTRL (AR_SM_BASE + 0x380)
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#define AR_PHY_RTT_TABLE_SW_INTF_B (AR_SM_BASE + 0x384)
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#define AR_PHY_RTT_TABLE_SW_INTF_1_B0 (AR_SM_BASE + 0x388)
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#define AR_PHY_WATCHDOG_STATUS (AR_SM_BASE + 0x5c0)
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#define AR_PHY_WATCHDOG_CTL_1 (AR_SM_BASE + 0x5c4)
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@ -825,6 +823,20 @@
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#define AR_PHY_SPECTRAL_SCAN_SHORT_REPEAT 0x01000000
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#define AR_PHY_SPECTRAL_SCAN_SHORT_REPEAT_S 24
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#define AR_PHY_CHANNEL_STATUS_RX_CLEAR 0x00000004
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#define AR_PHY_RTT_CTRL_ENA_RADIO_RETENTION 0x00000001
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#define AR_PHY_RTT_CTRL_ENA_RADIO_RETENTION_S 0
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#define AR_PHY_RTT_CTRL_RESTORE_MASK 0x0000007E
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#define AR_PHY_RTT_CTRL_RESTORE_MASK_S 1
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#define AR_PHY_RTT_CTRL_FORCE_RADIO_RESTORE 0x00000080
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#define AR_PHY_RTT_CTRL_FORCE_RADIO_RESTORE_S 7
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#define AR_PHY_RTT_SW_RTT_TABLE_ACCESS 0x00000001
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#define AR_PHY_RTT_SW_RTT_TABLE_ACCESS_S 0
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#define AR_PHY_RTT_SW_RTT_TABLE_WRITE 0x00000002
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#define AR_PHY_RTT_SW_RTT_TABLE_WRITE_S 1
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#define AR_PHY_RTT_SW_RTT_TABLE_ADDR 0x0000001C
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#define AR_PHY_RTT_SW_RTT_TABLE_ADDR_S 2
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#define AR_PHY_RTT_SW_RTT_TABLE_DATA 0xFFFFFFF0
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#define AR_PHY_RTT_SW_RTT_TABLE_DATA_S 4
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#define AR_PHY_TX_IQCAL_CONTROL_0_ENABLE_TXIQ_CAL 0x80000000
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#define AR_PHY_TX_IQCAL_CONTROL_0_ENABLE_TXIQ_CAL_S 31
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#define AR_PHY_TX_IQCAL_CONTROL_1_IQCORR_I_Q_COFF_DELPT 0x01fc0000
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@ -919,6 +931,10 @@
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#define AR_PHY_AIC_SRAM_ADDR_B1 (AR_SM1_BASE + 0x5f0)
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#define AR_PHY_AIC_SRAM_DATA_B1 (AR_SM1_BASE + 0x5f4)
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#define AR_PHY_RTT_TABLE_SW_INTF_B(i) (0x384 + (i) ? \
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AR_SM1_BASE : AR_SM_BASE)
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#define AR_PHY_RTT_TABLE_SW_INTF_1_B(i) (0x388 + (i) ? \
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AR_SM1_BASE : AR_SM_BASE)
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/*
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* Channel 2 Register Map
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*/
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@ -0,0 +1,153 @@
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/*
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* Copyright (c) 2010-2011 Atheros Communications Inc.
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*/
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#include "hw.h"
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#include "ar9003_phy.h"
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#define RTT_RESTORE_TIMEOUT 1000
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#define RTT_ACCESS_TIMEOUT 100
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#define RTT_BAD_VALUE 0x0bad0bad
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/*
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* RTT (Radio Retention Table) hardware implementation information
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*
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* There is an internal table (i.e. the rtt) for each chain (or bank).
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* Each table contains 6 entries and each entry is corresponding to
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* a specific calibration parameter as depicted below.
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* 0~2 - DC offset DAC calibration: loop, low, high (offsetI/Q_...)
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* 3 - Filter cal (filterfc)
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* 4 - RX gain settings
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* 5 - Peak detector offset calibration (agc_caldac)
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*/
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void ar9003_hw_rtt_enable(struct ath_hw *ah)
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{
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REG_WRITE(ah, AR_PHY_RTT_CTRL, 1);
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}
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void ar9003_hw_rtt_disable(struct ath_hw *ah)
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{
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REG_WRITE(ah, AR_PHY_RTT_CTRL, 0);
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}
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void ar9003_hw_rtt_set_mask(struct ath_hw *ah, u32 rtt_mask)
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{
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REG_RMW_FIELD(ah, AR_PHY_RTT_CTRL,
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AR_PHY_RTT_CTRL_RESTORE_MASK, rtt_mask);
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}
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bool ar9003_hw_rtt_force_restore(struct ath_hw *ah)
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{
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if (!ath9k_hw_wait(ah, AR_PHY_RTT_CTRL,
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AR_PHY_RTT_CTRL_FORCE_RADIO_RESTORE,
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0, RTT_RESTORE_TIMEOUT))
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return false;
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REG_RMW_FIELD(ah, AR_PHY_RTT_CTRL,
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AR_PHY_RTT_CTRL_FORCE_RADIO_RESTORE, 1);
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if (!ath9k_hw_wait(ah, AR_PHY_RTT_CTRL,
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AR_PHY_RTT_CTRL_FORCE_RADIO_RESTORE,
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0, RTT_RESTORE_TIMEOUT))
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return false;
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return true;
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}
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static void ar9003_hw_rtt_load_hist_entry(struct ath_hw *ah, u8 chain,
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u32 index, u32 data28)
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{
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u32 val;
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val = SM(data28, AR_PHY_RTT_SW_RTT_TABLE_DATA);
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REG_WRITE(ah, AR_PHY_RTT_TABLE_SW_INTF_1_B(chain), val);
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val = SM(0, AR_PHY_RTT_SW_RTT_TABLE_ACCESS) |
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SM(1, AR_PHY_RTT_SW_RTT_TABLE_WRITE) |
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SM(index, AR_PHY_RTT_SW_RTT_TABLE_ADDR);
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REG_WRITE(ah, AR_PHY_RTT_TABLE_SW_INTF_B(chain), val);
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udelay(1);
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val |= SM(1, AR_PHY_RTT_SW_RTT_TABLE_ACCESS);
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REG_WRITE(ah, AR_PHY_RTT_TABLE_SW_INTF_B(chain), val);
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udelay(1);
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if (!ath9k_hw_wait(ah, AR_PHY_RTT_TABLE_SW_INTF_B(chain),
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AR_PHY_RTT_SW_RTT_TABLE_ACCESS, 0,
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RTT_ACCESS_TIMEOUT))
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return;
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val &= ~SM(1, AR_PHY_RTT_SW_RTT_TABLE_WRITE);
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REG_WRITE(ah, AR_PHY_RTT_TABLE_SW_INTF_B(chain), val);
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udelay(1);
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ath9k_hw_wait(ah, AR_PHY_RTT_TABLE_SW_INTF_B(chain),
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AR_PHY_RTT_SW_RTT_TABLE_ACCESS, 0,
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RTT_ACCESS_TIMEOUT);
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}
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void ar9003_hw_rtt_load_hist(struct ath_hw *ah, u8 chain, u32 *table)
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{
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int i;
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for (i = 0; i < MAX_RTT_TABLE_ENTRY; i++)
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ar9003_hw_rtt_load_hist_entry(ah, chain, i, table[i]);
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}
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static int ar9003_hw_rtt_fill_hist_entry(struct ath_hw *ah, u8 chain, u32 index)
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{
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u32 val;
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val = SM(0, AR_PHY_RTT_SW_RTT_TABLE_ACCESS) |
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SM(0, AR_PHY_RTT_SW_RTT_TABLE_WRITE) |
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SM(index, AR_PHY_RTT_SW_RTT_TABLE_ADDR);
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REG_WRITE(ah, AR_PHY_RTT_TABLE_SW_INTF_B(chain), val);
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udelay(1);
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val |= SM(1, AR_PHY_RTT_SW_RTT_TABLE_ACCESS);
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REG_WRITE(ah, AR_PHY_RTT_TABLE_SW_INTF_B(chain), val);
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udelay(1);
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if (!ath9k_hw_wait(ah, AR_PHY_RTT_TABLE_SW_INTF_B(chain),
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AR_PHY_RTT_SW_RTT_TABLE_ACCESS, 0,
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RTT_ACCESS_TIMEOUT))
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return RTT_BAD_VALUE;
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val = REG_READ(ah, AR_PHY_RTT_TABLE_SW_INTF_1_B(chain));
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return val;
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}
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void ar9003_hw_rtt_fill_hist(struct ath_hw *ah, u8 chain, u32 *table)
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{
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int i;
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for (i = 0; i < MAX_RTT_TABLE_ENTRY; i++)
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table[i] = ar9003_hw_rtt_fill_hist_entry(ah, chain, i);
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}
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void ar9003_hw_rtt_clear_hist(struct ath_hw *ah)
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{
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int i, j;
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for (i = 0; i < AR9300_MAX_CHAINS; i++) {
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if (!(ah->rxchainmask & (1 << i)))
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continue;
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for (j = 0; j < MAX_RTT_TABLE_ENTRY; j++)
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ar9003_hw_rtt_load_hist_entry(ah, i, j, 0);
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}
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}
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@ -0,0 +1,28 @@
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/*
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* Copyright (c) 2010-2011 Atheros Communications Inc.
|
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*
|
||||
* Permission to use, copy, modify, and/or distribute this software for any
|
||||
* purpose with or without fee is hereby granted, provided that the above
|
||||
* copyright notice and this permission notice appear in all copies.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
|
||||
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
|
||||
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
|
||||
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
|
||||
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
|
||||
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
|
||||
*/
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#ifndef AR9003_RTT_H
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#define AR9003_RTT_H
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void ar9003_hw_rtt_enable(struct ath_hw *ah);
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void ar9003_hw_rtt_disable(struct ath_hw *ah);
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void ar9003_hw_rtt_set_mask(struct ath_hw *ah, u32 rtt_mask);
|
||||
bool ar9003_hw_rtt_force_restore(struct ath_hw *ah);
|
||||
void ar9003_hw_rtt_load_hist(struct ath_hw *ah, u8 chain, u32 *table);
|
||||
void ar9003_hw_rtt_fill_hist(struct ath_hw *ah, u8 chain, u32 *table);
|
||||
void ar9003_hw_rtt_clear_hist(struct ath_hw *ah);
|
||||
|
||||
#endif
|
||||
|
|
@ -1709,6 +1709,7 @@ int ath9k_hw_reset(struct ath_hw *ah, struct ath9k_channel *chan,
|
|||
if (caldata) {
|
||||
caldata->done_txiqcal_once = false;
|
||||
caldata->done_txclcal_once = false;
|
||||
caldata->rtt_hist.num_readings = 0;
|
||||
}
|
||||
if (!ath9k_hw_init_cal(ah, chan))
|
||||
return -EIO;
|
||||
|
|
@ -2319,6 +2320,9 @@ int ath9k_hw_fill_cap_info(struct ath_hw *ah)
|
|||
if (!AR_SREV_9330(ah))
|
||||
ah->enabled_cals |= TX_IQ_ON_AGC_CAL;
|
||||
}
|
||||
if (AR_SREV_9480(ah))
|
||||
pCap->hw_caps |= ATH9K_HW_CAP_RTT;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -202,6 +202,7 @@ enum ath9k_hw_caps {
|
|||
ATH9K_HW_CAP_2GHZ = BIT(13),
|
||||
ATH9K_HW_CAP_5GHZ = BIT(14),
|
||||
ATH9K_HW_CAP_APM = BIT(15),
|
||||
ATH9K_HW_CAP_RTT = BIT(16),
|
||||
};
|
||||
|
||||
struct ath9k_hw_capabilities {
|
||||
|
|
@ -337,6 +338,13 @@ enum ath9k_int {
|
|||
CHANNEL_HT40PLUS | \
|
||||
CHANNEL_HT40MINUS)
|
||||
|
||||
#define MAX_RTT_TABLE_ENTRY 6
|
||||
#define RTT_HIST_MAX 3
|
||||
struct ath9k_rtt_hist {
|
||||
u32 table[AR9300_MAX_CHAINS][RTT_HIST_MAX][MAX_RTT_TABLE_ENTRY];
|
||||
u8 num_readings;
|
||||
};
|
||||
|
||||
#define MAX_IQCAL_MEASUREMENT 8
|
||||
#define MAX_CL_TAB_ENTRY 16
|
||||
|
||||
|
|
@ -357,6 +365,7 @@ struct ath9k_hw_cal_data {
|
|||
int tx_corr_coeff[MAX_IQCAL_MEASUREMENT][AR9300_MAX_CHAINS];
|
||||
u32 tx_clcal[AR9300_MAX_CHAINS][MAX_CL_TAB_ENTRY];
|
||||
struct ath9k_nfcal_hist nfCalHist[NUM_NF_READINGS];
|
||||
struct ath9k_rtt_hist rtt_hist;
|
||||
};
|
||||
|
||||
struct ath9k_channel {
|
||||
|
|
|
|||
|
|
@ -1933,6 +1933,7 @@ enum {
|
|||
#define AR_PHY_AGC_CONTROL_NO_UPDATE_NF 0x00020000 /* don't update noise floor automatically */
|
||||
#define AR_PHY_AGC_CONTROL_EXT_NF_PWR_MEAS 0x00040000 /* extend noise floor power measurement */
|
||||
#define AR_PHY_AGC_CONTROL_CLC_SUCCESS 0x00080000 /* carrier leak calibration done */
|
||||
#define AR_PHY_AGC_CONTROL_PKDET_CAL 0x00100000
|
||||
#define AR_PHY_AGC_CONTROL_YCOK_MAX 0x000003c0
|
||||
#define AR_PHY_AGC_CONTROL_YCOK_MAX_S 6
|
||||
|
||||
|
|
|
|||
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