usb: xhci: Remove unused function
Now that we replaced the xhci_create_usb3_bos_desc() function. We can remove it along with the static usb_bos_descriptor structure. Acked-by: Mathias Nyman <mathias.nyman@linux.intel.com> Signed-off-by: Thinh Nguyen <Thinh.Nguyen@synopsys.com> Link: https://lore.kernel.org/r/ce0acbbd0bd3c3c3a08e6418ab3bdb431a44bbfd.1615432770.git.Thinh.Nguyen@synopsys.com Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
This commit is contained in:
Thinh Nguyen
Greg Kroah-Hartman
Родитель
eb02aaf21f
Коммит
325c3b9a0b
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@ -20,39 +20,6 @@
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#define PORT_RWC_BITS (PORT_CSC | PORT_PEC | PORT_WRC | PORT_OCC | \
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PORT_RC | PORT_PLC | PORT_PE)
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/* USB 3 BOS descriptor and a capability descriptors, combined.
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* Fields will be adjusted and added later in xhci_create_usb3_bos_desc()
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*/
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static u8 usb_bos_descriptor [] = {
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USB_DT_BOS_SIZE, /* __u8 bLength, 5 bytes */
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USB_DT_BOS, /* __u8 bDescriptorType */
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0x0F, 0x00, /* __le16 wTotalLength, 15 bytes */
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0x1, /* __u8 bNumDeviceCaps */
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/* First device capability, SuperSpeed */
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USB_DT_USB_SS_CAP_SIZE, /* __u8 bLength, 10 bytes */
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USB_DT_DEVICE_CAPABILITY, /* Device Capability */
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USB_SS_CAP_TYPE, /* bDevCapabilityType, SUPERSPEED_USB */
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0x00, /* bmAttributes, LTM off by default */
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USB_5GBPS_OPERATION, 0x00, /* wSpeedsSupported, 5Gbps only */
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0x03, /* bFunctionalitySupport,
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USB 3.0 speed only */
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0x00, /* bU1DevExitLat, set later. */
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0x00, 0x00, /* __le16 bU2DevExitLat, set later. */
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/* Second device capability, SuperSpeedPlus */
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0x1c, /* bLength 28, will be adjusted later */
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USB_DT_DEVICE_CAPABILITY, /* Device Capability */
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USB_SSP_CAP_TYPE, /* bDevCapabilityType SUPERSPEED_PLUS */
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0x00, /* bReserved 0 */
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0x23, 0x00, 0x00, 0x00, /* bmAttributes, SSAC=3 SSIC=1 */
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0x01, 0x00, /* wFunctionalitySupport */
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0x00, 0x00, /* wReserved 0 */
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/* Default Sublink Speed Attributes, overwrite if custom PSI exists */
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0x34, 0x00, 0x05, 0x00, /* 5Gbps, symmetric, rx, ID = 4 */
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0xb4, 0x00, 0x05, 0x00, /* 5Gbps, symmetric, tx, ID = 4 */
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0x35, 0x40, 0x0a, 0x00, /* 10Gbps, SSP, symmetric, rx, ID = 5 */
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0xb5, 0x40, 0x0a, 0x00, /* 10Gbps, SSP, symmetric, tx, ID = 5 */
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};
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/* Default sublink speed attribute of each lane */
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static u32 ssp_cap_default_ssa[] = {
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0x00050034, /* USB 3.0 SS Gen1x1 id:4 symmetric rx 5Gbps */
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@ -285,120 +252,6 @@ out:
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return le16_to_cpu(bos->wTotalLength);
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}
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static __maybe_unused int xhci_create_usb3_bos_desc(struct xhci_hcd *xhci, char *buf,
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u16 wLength)
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{
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struct xhci_port_cap *port_cap = NULL;
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int i, ssa_count;
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u32 temp;
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u16 desc_size, ssp_cap_size, ssa_size = 0;
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bool usb3_1 = false;
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desc_size = USB_DT_BOS_SIZE + USB_DT_USB_SS_CAP_SIZE;
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ssp_cap_size = sizeof(usb_bos_descriptor) - desc_size;
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/* does xhci support USB 3.1 Enhanced SuperSpeed */
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for (i = 0; i < xhci->num_port_caps; i++) {
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if (xhci->port_caps[i].maj_rev == 0x03 &&
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xhci->port_caps[i].min_rev >= 0x01) {
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usb3_1 = true;
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port_cap = &xhci->port_caps[i];
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break;
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}
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}
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if (usb3_1) {
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/* does xhci provide a PSI table for SSA speed attributes? */
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if (port_cap->psi_count) {
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/* two SSA entries for each unique PSI ID, RX and TX */
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ssa_count = port_cap->psi_uid_count * 2;
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ssa_size = ssa_count * sizeof(u32);
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ssp_cap_size -= 16; /* skip copying the default SSA */
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}
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desc_size += ssp_cap_size;
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}
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memcpy(buf, &usb_bos_descriptor, min(desc_size, wLength));
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if (usb3_1) {
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/* modify bos descriptor bNumDeviceCaps and wTotalLength */
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buf[4] += 1;
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put_unaligned_le16(desc_size + ssa_size, &buf[2]);
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}
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if (wLength < USB_DT_BOS_SIZE + USB_DT_USB_SS_CAP_SIZE)
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return wLength;
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/* Indicate whether the host has LTM support. */
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temp = readl(&xhci->cap_regs->hcc_params);
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if (HCC_LTC(temp))
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buf[8] |= USB_LTM_SUPPORT;
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/* Set the U1 and U2 exit latencies. */
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if ((xhci->quirks & XHCI_LPM_SUPPORT)) {
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temp = readl(&xhci->cap_regs->hcs_params3);
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buf[12] = HCS_U1_LATENCY(temp);
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put_unaligned_le16(HCS_U2_LATENCY(temp), &buf[13]);
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}
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/* If PSI table exists, add the custom speed attributes from it */
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if (usb3_1 && port_cap->psi_count) {
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u32 ssp_cap_base, bm_attrib, psi, psi_mant, psi_exp;
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int offset;
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ssp_cap_base = USB_DT_BOS_SIZE + USB_DT_USB_SS_CAP_SIZE;
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if (wLength < desc_size)
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return wLength;
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buf[ssp_cap_base] = ssp_cap_size + ssa_size;
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/* attribute count SSAC bits 4:0 and ID count SSIC bits 8:5 */
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bm_attrib = (ssa_count - 1) & 0x1f;
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bm_attrib |= (port_cap->psi_uid_count - 1) << 5;
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put_unaligned_le32(bm_attrib, &buf[ssp_cap_base + 4]);
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if (wLength < desc_size + ssa_size)
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return wLength;
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/*
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* Create the Sublink Speed Attributes (SSA) array.
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* The xhci PSI field and USB 3.1 SSA fields are very similar,
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* but link type bits 7:6 differ for values 01b and 10b.
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* xhci has also only one PSI entry for a symmetric link when
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* USB 3.1 requires two SSA entries (RX and TX) for every link
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*/
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offset = desc_size;
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for (i = 0; i < port_cap->psi_count; i++) {
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psi = port_cap->psi[i];
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psi &= ~USB_SSP_SUBLINK_SPEED_RSVD;
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psi_exp = XHCI_EXT_PORT_PSIE(psi);
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psi_mant = XHCI_EXT_PORT_PSIM(psi);
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/* Shift to Gbps and set SSP Link BIT(14) if 10Gpbs */
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for (; psi_exp < 3; psi_exp++)
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psi_mant /= 1000;
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if (psi_mant >= 10)
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psi |= BIT(14);
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if ((psi & PLT_MASK) == PLT_SYM) {
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/* Symmetric, create SSA RX and TX from one PSI entry */
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put_unaligned_le32(psi, &buf[offset]);
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psi |= 1 << 7; /* turn entry to TX */
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offset += 4;
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if (offset >= desc_size + ssa_size)
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return desc_size + ssa_size;
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} else if ((psi & PLT_MASK) == PLT_ASYM_RX) {
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/* Asymetric RX, flip bits 7:6 for SSA */
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psi ^= PLT_MASK;
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}
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put_unaligned_le32(psi, &buf[offset]);
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offset += 4;
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if (offset >= desc_size + ssa_size)
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return desc_size + ssa_size;
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}
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}
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/* ssa_size is 0 for other than usb 3.1 hosts */
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return desc_size + ssa_size;
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}
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static void xhci_common_hub_descriptor(struct xhci_hcd *xhci,
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struct usb_hub_descriptor *desc, int ports)
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{
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