[ARM] 3666/1: TRIZEPS4 [1/5] core
Patch from Jrgen Schindele This patch adds support for Trizeps4 SoM and ConXS-evalboard from "Keith und Koep" This DIMM-module is based on PXA270. Signed-off-by: Jrgen Schindele <linux@schindele.name> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
This commit is contained in:
Jrgen Schindele
Russell King
Родитель
a144a5633c
Коммит
326764a85b
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@ -547,7 +547,7 @@ config LEDS
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ARCH_LUBBOCK || MACH_MAINSTONE || ARCH_NETWINDER || \
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ARCH_OMAP || ARCH_P720T || ARCH_PXA_IDP || \
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ARCH_SA1100 || ARCH_SHARK || ARCH_VERSATILE || \
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ARCH_AT91RM9200
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ARCH_AT91RM9200 || MACH_TRIZEPS4
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help
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If you say Y here, the LEDs on your machine will be used
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to provide useful information about your current system status.
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Разница между файлами не показана из-за своего большого размера
Загрузить разницу
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@ -35,6 +35,10 @@ config PXA_SHARPSL
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SL-C3000 (Spitz), SL-C3100 (Borzoi) or SL-C6000x (Tosa)
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handheld computer.
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config MACH_TRIZEPS4
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bool "Keith und Koep Trizeps4 DIMM-Module"
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select PXA27x
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endchoice
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if PXA_SHARPSL
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@ -55,6 +59,21 @@ endchoice
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endif
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if MACH_TRIZEPS4
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choice
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prompt "Select base board for Trizeps 4 module"
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config MACH_TRIZEPS4_CONXS
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bool "ConXS Eval Board"
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config MACH_TRIZEPS4_ANY
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bool "another Board"
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endchoice
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endif
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endmenu
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config MACH_POODLE
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@ -12,6 +12,7 @@ obj-$(CONFIG_ARCH_LUBBOCK) += lubbock.o
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obj-$(CONFIG_MACH_LOGICPD_PXA270) += lpd270.o
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obj-$(CONFIG_MACH_MAINSTONE) += mainstone.o
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obj-$(CONFIG_ARCH_PXA_IDP) += idp.o
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obj-$(CONFIG_MACH_TRIZEPS4) += trizeps4.o
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obj-$(CONFIG_PXA_SHARP_C7xx) += corgi.o corgi_ssp.o corgi_lcd.o sharpsl_pm.o corgi_pm.o
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obj-$(CONFIG_PXA_SHARP_Cxx00) += spitz.o corgi_ssp.o corgi_lcd.o sharpsl_pm.o spitz_pm.o
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obj-$(CONFIG_MACH_AKITA) += akita-ioexp.o
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@ -23,6 +24,7 @@ led-y := leds.o
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led-$(CONFIG_ARCH_LUBBOCK) += leds-lubbock.o
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led-$(CONFIG_MACH_MAINSTONE) += leds-mainstone.o
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led-$(CONFIG_ARCH_PXA_IDP) += leds-idp.o
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led-$(CONFIG_MACH_TRIZEPS4) += leds-trizeps4.o
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obj-$(CONFIG_LEDS) += $(led-y)
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@ -0,0 +1,134 @@
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/*
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* linux/arch/arm/mach-pxa/leds-trizeps4.c
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*
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* Author: Jürgen Schindele
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* Created: 20 02, 2006
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* Copyright: Jürgen Schindele
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include <linux/config.h>
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#include <linux/init.h>
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#include <asm/hardware.h>
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#include <asm/system.h>
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#include <asm/types.h>
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#include <asm/leds.h>
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#include <asm/arch/pxa-regs.h>
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#include <asm/arch/trizeps4.h>
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#include "leds.h"
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#define LED_STATE_ENABLED 1
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#define LED_STATE_CLAIMED 2
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#define SYS_BUSY 0x01
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#define HEARTBEAT 0x02
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#define BLINK 0x04
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static unsigned int led_state;
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static unsigned int hw_led_state;
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void trizeps4_leds_event(led_event_t evt)
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{
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unsigned long flags;
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local_irq_save(flags);
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switch (evt) {
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case led_start:
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hw_led_state = 0;
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pxa_gpio_mode( GPIO_SYS_BUSY_LED | GPIO_OUT); /* LED1 */
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pxa_gpio_mode( GPIO_HEARTBEAT_LED | GPIO_OUT); /* LED2 */
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led_state = LED_STATE_ENABLED;
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break;
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case led_stop:
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led_state &= ~LED_STATE_ENABLED;
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break;
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case led_claim:
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led_state |= LED_STATE_CLAIMED;
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hw_led_state = 0;
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break;
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case led_release:
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led_state &= ~LED_STATE_CLAIMED;
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hw_led_state = 0;
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break;
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#ifdef CONFIG_LEDS_TIMER
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case led_timer:
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hw_led_state ^= HEARTBEAT;
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break;
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#endif
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#ifdef CONFIG_LEDS_CPU
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case led_idle_start:
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hw_led_state &= ~SYS_BUSY;
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break;
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case led_idle_end:
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hw_led_state |= SYS_BUSY;
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break;
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#endif
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case led_halted:
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break;
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case led_green_on:
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hw_led_state |= BLINK;
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break;
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case led_green_off:
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hw_led_state &= ~BLINK;
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break;
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case led_amber_on:
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break;
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case led_amber_off:
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break;
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case led_red_on:
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break;
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case led_red_off:
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break;
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default:
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break;
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}
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if (led_state & LED_STATE_ENABLED) {
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switch (hw_led_state) {
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case 0:
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GPSR(GPIO_SYS_BUSY_LED) |= GPIO_bit(GPIO_SYS_BUSY_LED);
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GPSR(GPIO_HEARTBEAT_LED) |= GPIO_bit(GPIO_HEARTBEAT_LED);
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break;
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case 1:
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GPCR(GPIO_SYS_BUSY_LED) |= GPIO_bit(GPIO_SYS_BUSY_LED);
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GPSR(GPIO_HEARTBEAT_LED) |= GPIO_bit(GPIO_HEARTBEAT_LED);
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break;
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case 2:
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GPSR(GPIO_SYS_BUSY_LED) |= GPIO_bit(GPIO_SYS_BUSY_LED);
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GPCR(GPIO_HEARTBEAT_LED) |= GPIO_bit(GPIO_HEARTBEAT_LED);
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break;
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case 3:
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GPCR(GPIO_SYS_BUSY_LED) |= GPIO_bit(GPIO_SYS_BUSY_LED);
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GPCR(GPIO_HEARTBEAT_LED) |= GPIO_bit(GPIO_HEARTBEAT_LED);
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break;
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}
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}
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else {
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/* turn all off */
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GPSR(GPIO_SYS_BUSY_LED) |= GPIO_bit(GPIO_SYS_BUSY_LED);
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GPSR(GPIO_HEARTBEAT_LED) |= GPIO_bit(GPIO_HEARTBEAT_LED);
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}
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local_irq_restore(flags);
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}
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@ -24,6 +24,8 @@ pxa_leds_init(void)
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leds_event = mainstone_leds_event;
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if (machine_is_pxa_idp())
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leds_event = idp_leds_event;
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if (machine_is_trizeps4())
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leds_event = trizeps4_leds_event;
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leds_event(led_start);
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return 0;
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@ -10,3 +10,4 @@
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extern void idp_leds_event(led_event_t evt);
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extern void lubbock_leds_event(led_event_t evt);
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extern void mainstone_leds_event(led_event_t evt);
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extern void trizeps4_leds_event(led_event_t evt);
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@ -0,0 +1,471 @@
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/*
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* linux/arch/arm/mach-pxa/trizeps4.c
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*
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* Support for the Keith und Koep Trizeps4 Module Platform.
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*
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* Author: Jürgen Schindele
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* Created: 20 02, 2006
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* Copyright: Jürgen Schindele
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include <linux/init.h>
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#include <linux/kernel.h>
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#include <linux/platform_device.h>
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#include <linux/sysdev.h>
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#include <linux/interrupt.h>
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#include <linux/sched.h>
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#include <linux/bitops.h>
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#include <linux/fb.h>
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#include <linux/ioport.h>
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#include <linux/delay.h>
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#include <linux/serial_8250.h>
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#include <linux/mtd/mtd.h>
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#include <linux/mtd/partitions.h>
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#include <asm/types.h>
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#include <asm/setup.h>
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#include <asm/memory.h>
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#include <asm/mach-types.h>
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#include <asm/hardware.h>
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#include <asm/irq.h>
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#include <asm/sizes.h>
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#include <asm/mach/arch.h>
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#include <asm/mach/map.h>
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#include <asm/mach/irq.h>
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#include <asm/mach/flash.h>
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#include <asm/arch/pxa-regs.h>
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#include <asm/arch/trizeps4.h>
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#include <asm/arch/audio.h>
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#include <asm/arch/pxafb.h>
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#include <asm/arch/mmc.h>
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#include <asm/arch/irda.h>
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#include <asm/arch/ohci.h>
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#include "generic.h"
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/********************************************************************************************
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* ONBOARD FLASH
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********************************************************************************************/
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static struct mtd_partition trizeps4_partitions[] = {
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{
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.name = "Bootloader",
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.size = 0x00040000,
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.offset = 0,
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.mask_flags = MTD_WRITEABLE /* force read-only */
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},{
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.name = "Kernel",
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.size = 0x00400000,
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.offset = 0x00040000
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},{
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.name = "Filesystem",
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.size = MTDPART_SIZ_FULL,
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.offset = 0x00440000
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}
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};
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static struct flash_platform_data trizeps4_flash_data[] = {
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{
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.map_name = "cfi_probe",
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.parts = trizeps4_partitions,
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.nr_parts = ARRAY_SIZE(trizeps4_partitions)
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}
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};
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static struct resource flash_resource = {
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.start = PXA_CS0_PHYS,
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.end = PXA_CS0_PHYS + SZ_64M - 1,
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.flags = IORESOURCE_MEM,
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};
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static struct platform_device flash_device = {
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.name = "pxa2xx-flash",
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.id = 0,
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.dev = {
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.platform_data = &trizeps4_flash_data,
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},
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.resource = &flash_resource,
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.num_resources = 1,
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};
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/********************************************************************************************
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* DAVICOM DM9000 Ethernet
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********************************************************************************************/
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static struct resource dm9000_resources[] = {
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[0] = {
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.start = TRIZEPS4_ETH_PHYS+0x300,
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.end = TRIZEPS4_ETH_PHYS+0x400-1,
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.flags = IORESOURCE_MEM,
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},
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[1] = {
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.start = TRIZEPS4_ETH_PHYS+0x8300,
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.end = TRIZEPS4_ETH_PHYS+0x8400-1,
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.flags = IORESOURCE_MEM,
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},
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[2] = {
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.start = TRIZEPS4_ETH_IRQ,
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.end = TRIZEPS4_ETH_IRQ,
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.flags = (IORESOURCE_IRQ | IRQT_RISING),
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},
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};
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static struct platform_device dm9000_device = {
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.name = "dm9000",
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.id = -1,
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.num_resources = ARRAY_SIZE(dm9000_resources),
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.resource = dm9000_resources,
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};
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/********************************************************************************************
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* PXA270 serial ports
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********************************************************************************************/
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static struct plat_serial8250_port tri_serial_ports[] = {
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#ifdef CONFIG_SERIAL_PXA
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/* this uses the own PXA driver */
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{
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0,
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},
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#else
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/* this uses the generic 8520 driver */
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[0] = {
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.membase = (void *)&FFUART,
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.irq = IRQ_FFUART,
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.flags = UPF_BOOT_AUTOCONF,
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.iotype = UPIO_MEM32,
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.regshift = 2,
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.uartclk = (921600*16),
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},
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[1] = {
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.membase = (void *)&BTUART,
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.irq = IRQ_BTUART,
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.flags = UPF_BOOT_AUTOCONF,
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.iotype = UPIO_MEM32,
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.regshift = 2,
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.uartclk = (921600*16),
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},
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{
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0,
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},
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#endif
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};
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static struct platform_device uart_devices = {
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.name = "serial8250",
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.id = 0,
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.dev = {
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.platform_data = tri_serial_ports,
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},
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.num_resources = 0,
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.resource = NULL,
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};
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/********************************************************************************************
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* PXA270 ac97 sound codec
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********************************************************************************************/
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static struct platform_device ac97_audio_device = {
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.name = "pxa2xx-ac97",
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.id = -1,
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};
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static struct platform_device * trizeps4_devices[] __initdata = {
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&flash_device,
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&uart_devices,
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&dm9000_device,
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&ac97_audio_device,
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};
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#ifdef CONFIG_MACH_TRIZEPS4_CONXS
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static short trizeps_conxs_bcr;
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/* PCCARD power switching supports only 3,3V */
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void board_pcmcia_power(int power)
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{
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if (power) {
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/* switch power on, put in reset and enable buffers */
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trizeps_conxs_bcr |= power;
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trizeps_conxs_bcr |= ConXS_BCR_CF_RESET;
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trizeps_conxs_bcr &= ~(ConXS_BCR_CF_BUF_EN);
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ConXS_BCR = trizeps_conxs_bcr;
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/* wait a little */
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udelay(2000);
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/* take reset away */
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trizeps_conxs_bcr &= ~(ConXS_BCR_CF_RESET);
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ConXS_BCR = trizeps_conxs_bcr;
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udelay(2000);
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} else {
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/* put in reset */
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trizeps_conxs_bcr |= ConXS_BCR_CF_RESET;
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ConXS_BCR = trizeps_conxs_bcr;
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udelay(1000);
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/* switch power off */
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trizeps_conxs_bcr &= ~(0xf);
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ConXS_BCR = trizeps_conxs_bcr;
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}
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pr_debug("%s: o%s 0x%x\n", __FUNCTION__, power ? "n": "ff", trizeps_conxs_bcr);
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}
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/* backlight power switching for LCD panel */
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static void board_backlight_power(int on)
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{
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if (on) {
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trizeps_conxs_bcr |= ConXS_BCR_L_DISP;
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} else {
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trizeps_conxs_bcr &= ~ConXS_BCR_L_DISP;
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}
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pr_debug("%s: o%s 0x%x\n", __FUNCTION__, on ? "n" : "ff", trizeps_conxs_bcr);
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ConXS_BCR = trizeps_conxs_bcr;
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}
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/* Powersupply for MMC/SD cardslot */
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static void board_mci_power(struct device *dev, unsigned int vdd)
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{
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struct pxamci_platform_data* p_d = dev->platform_data;
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if (( 1 << vdd) & p_d->ocr_mask) {
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pr_debug("%s: on\n", __FUNCTION__);
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/* FIXME fill in values here */
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} else {
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pr_debug("%s: off\n", __FUNCTION__);
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/* FIXME fill in values here */
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}
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}
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static short trizeps_conxs_ircr;
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/* Switch modes and Power for IRDA receiver */
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static void board_irda_mode(struct device *dev, int mode)
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{
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unsigned long flags;
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|
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local_irq_save(flags);
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if (mode & IR_SIRMODE) {
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/* Slow mode */
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trizeps_conxs_ircr &= ~ConXS_IRCR_MODE;
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} else if (mode & IR_FIRMODE) {
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/* Fast mode */
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trizeps_conxs_ircr |= ConXS_IRCR_MODE;
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}
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if (mode & IR_OFF) {
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trizeps_conxs_ircr |= ConXS_IRCR_SD;
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} else {
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trizeps_conxs_ircr &= ~ConXS_IRCR_SD;
|
||||
}
|
||||
/* FIXME write values to register */
|
||||
local_irq_restore(flags);
|
||||
}
|
||||
|
||||
#else
|
||||
/* for other baseboards define dummies */
|
||||
void board_pcmcia_power(int power) {;}
|
||||
#define board_backlight_power NULL
|
||||
#define board_mci_power NULL
|
||||
#define board_irda_mode NULL
|
||||
|
||||
#endif /* CONFIG_MACH_TRIZEPS4_CONXS */
|
||||
EXPORT_SYMBOL(board_pcmcia_power);
|
||||
|
||||
static int trizeps4_mci_init(struct device *dev, irqreturn_t (*mci_detect_int)(int, void *, struct pt_regs *), void *data)
|
||||
{
|
||||
int err;
|
||||
/* setup GPIO for PXA27x MMC controller */
|
||||
pxa_gpio_mode(GPIO32_MMCCLK_MD);
|
||||
pxa_gpio_mode(GPIO112_MMCCMD_MD);
|
||||
pxa_gpio_mode(GPIO92_MMCDAT0_MD);
|
||||
pxa_gpio_mode(GPIO109_MMCDAT1_MD);
|
||||
pxa_gpio_mode(GPIO110_MMCDAT2_MD);
|
||||
pxa_gpio_mode(GPIO111_MMCDAT3_MD);
|
||||
|
||||
pxa_gpio_mode(GPIO_MMC_DET | GPIO_IN);
|
||||
|
||||
err = request_irq(TRIZEPS4_MMC_IRQ, mci_detect_int, SA_INTERRUPT | SA_TRIGGER_RISING, "MMC card detect", data);
|
||||
if (err) {
|
||||
printk(KERN_ERR "trizeps4_mci_init: MMC/SD: can't request MMC card detect IRQ\n");
|
||||
return -1;
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void trizeps4_mci_exit(struct device *dev, void *data)
|
||||
{
|
||||
free_irq(TRIZEPS4_MMC_IRQ, data);
|
||||
}
|
||||
|
||||
static struct pxamci_platform_data trizeps4_mci_platform_data = {
|
||||
.ocr_mask = MMC_VDD_32_33|MMC_VDD_33_34,
|
||||
.init = trizeps4_mci_init,
|
||||
.exit = trizeps4_mci_exit,
|
||||
.setpower = board_mci_power,
|
||||
};
|
||||
|
||||
static struct pxaficp_platform_data trizeps4_ficp_platform_data = {
|
||||
.transceiver_cap = IR_SIRMODE | IR_FIRMODE | IR_OFF,
|
||||
.transceiver_mode = board_irda_mode,
|
||||
};
|
||||
|
||||
static int trizeps4_ohci_init(struct device *dev)
|
||||
{
|
||||
/* setup Port1 GPIO pin. */
|
||||
pxa_gpio_mode( 88 | GPIO_ALT_FN_1_IN); /* USBHPWR1 */
|
||||
pxa_gpio_mode( 89 | GPIO_ALT_FN_2_OUT); /* USBHPEN1 */
|
||||
|
||||
/* Set the Power Control Polarity Low and Power Sense
|
||||
Polarity Low to active low. */
|
||||
UHCHR = (UHCHR | UHCHR_PCPL | UHCHR_PSPL) &
|
||||
~(UHCHR_SSEP1 | UHCHR_SSEP2 | UHCHR_SSEP3 | UHCHR_SSE);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void trizeps4_ohci_exit(struct device *dev)
|
||||
{
|
||||
;
|
||||
}
|
||||
|
||||
static struct pxaohci_platform_data trizeps4_ohci_platform_data = {
|
||||
.port_mode = PMM_PERPORT_MODE,
|
||||
.init = trizeps4_ohci_init,
|
||||
.exit = trizeps4_ohci_exit,
|
||||
};
|
||||
|
||||
static struct map_desc trizeps4_io_desc[] __initdata = {
|
||||
{ /* ConXS CFSR */
|
||||
.virtual = TRIZEPS4_CFSR_VIRT,
|
||||
.pfn = __phys_to_pfn(TRIZEPS4_CFSR_PHYS),
|
||||
.length = 0x00001000,
|
||||
.type = MT_DEVICE
|
||||
},
|
||||
{ /* ConXS BCR */
|
||||
.virtual = TRIZEPS4_BOCR_VIRT,
|
||||
.pfn = __phys_to_pfn(TRIZEPS4_BOCR_PHYS),
|
||||
.length = 0x00001000,
|
||||
.type = MT_DEVICE
|
||||
},
|
||||
{ /* ConXS IRCR */
|
||||
.virtual = TRIZEPS4_IRCR_VIRT,
|
||||
.pfn = __phys_to_pfn(TRIZEPS4_IRCR_PHYS),
|
||||
.length = 0x00001000,
|
||||
.type = MT_DEVICE
|
||||
},
|
||||
{ /* ConXS DCR */
|
||||
.virtual = TRIZEPS4_DICR_VIRT,
|
||||
.pfn = __phys_to_pfn(TRIZEPS4_DICR_PHYS),
|
||||
.length = 0x00001000,
|
||||
.type = MT_DEVICE
|
||||
},
|
||||
{ /* ConXS UPSR */
|
||||
.virtual = TRIZEPS4_UPSR_VIRT,
|
||||
.pfn = __phys_to_pfn(TRIZEPS4_UPSR_PHYS),
|
||||
.length = 0x00001000,
|
||||
.type = MT_DEVICE
|
||||
}
|
||||
};
|
||||
|
||||
static struct pxafb_mach_info sharp_lcd __initdata = {
|
||||
.pixclock = 78000,
|
||||
.xres = 640,
|
||||
.yres = 480,
|
||||
.bpp = 8,
|
||||
.hsync_len = 4,
|
||||
.left_margin = 4,
|
||||
.right_margin = 4,
|
||||
.vsync_len = 2,
|
||||
.upper_margin = 0,
|
||||
.lower_margin = 0,
|
||||
.sync = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
|
||||
.cmap_greyscale = 0,
|
||||
.cmap_inverse = 0,
|
||||
.cmap_static = 0,
|
||||
.lccr0 = LCCR0_Color | LCCR0_Pas | LCCR0_Dual,
|
||||
.lccr3 = 0x0340ff02,
|
||||
.pxafb_backlight_power = board_backlight_power,
|
||||
};
|
||||
|
||||
static void __init trizeps4_fixup(struct machine_desc *desc, struct tag *tags, char **cmdline, struct meminfo *mi)
|
||||
{
|
||||
}
|
||||
|
||||
static void __init trizeps4_init(void)
|
||||
{
|
||||
platform_add_devices(trizeps4_devices, ARRAY_SIZE(trizeps4_devices));
|
||||
|
||||
set_pxa_fb_info(&sharp_lcd);
|
||||
|
||||
pxa_set_mci_info(&trizeps4_mci_platform_data);
|
||||
pxa_set_ficp_info(&trizeps4_ficp_platform_data);
|
||||
pxa_set_ohci_info(&trizeps4_ohci_platform_data);
|
||||
}
|
||||
|
||||
static void __init trizeps4_map_io(void)
|
||||
{
|
||||
pxa_map_io();
|
||||
iotable_init(trizeps4_io_desc, ARRAY_SIZE(trizeps4_io_desc));
|
||||
|
||||
/* for DiskOnChip */
|
||||
pxa_gpio_mode(GPIO15_nCS_1_MD);
|
||||
|
||||
/* for off-module PIC on ConXS board */
|
||||
pxa_gpio_mode(GPIO_PIC | GPIO_IN);
|
||||
|
||||
/* UCB1400 irq */
|
||||
pxa_gpio_mode(GPIO_UCB1400 | GPIO_IN);
|
||||
|
||||
/* for DM9000 LAN */
|
||||
pxa_gpio_mode(GPIO78_nCS_2_MD);
|
||||
pxa_gpio_mode(GPIO_DM9000 | GPIO_IN);
|
||||
|
||||
/* for PCMCIA device */
|
||||
pxa_gpio_mode(GPIO_PCD | GPIO_IN);
|
||||
pxa_gpio_mode(GPIO_PRDY | GPIO_IN);
|
||||
|
||||
/* for I2C adapter */
|
||||
pxa_gpio_mode(GPIO117_I2CSCL_MD);
|
||||
pxa_gpio_mode(GPIO118_I2CSDA_MD);
|
||||
|
||||
/* MMC_DET s.o. */
|
||||
pxa_gpio_mode(GPIO_MMC_DET | GPIO_IN);
|
||||
|
||||
/* whats that for ??? */
|
||||
pxa_gpio_mode(GPIO79_nCS_3_MD);
|
||||
|
||||
pxa_gpio_mode( GPIO_SYS_BUSY_LED | GPIO_OUT); /* LED1 */
|
||||
pxa_gpio_mode( GPIO_HEARTBEAT_LED | GPIO_OUT); /* LED2 */
|
||||
|
||||
#ifdef CONFIG_MACH_TRIZEPS4_CONXS
|
||||
#ifdef CONFIG_IDE_PXA_CF
|
||||
/* if boot direct from compact flash dont disable power */
|
||||
trizeps_conxs_bcr = 0x0009;
|
||||
#else
|
||||
/* this is the reset value */
|
||||
trizeps_conxs_bcr = 0x00A0;
|
||||
#endif
|
||||
ConXS_BCR = trizeps_conxs_bcr;
|
||||
#endif
|
||||
|
||||
PWER = 0x00000002;
|
||||
PFER = 0x00000000;
|
||||
PRER = 0x00000002;
|
||||
PGSR0 = 0x0158C000;
|
||||
PGSR1 = 0x00FF0080;
|
||||
PGSR2 = 0x0001C004;
|
||||
/* Stop 3.6MHz and drive HIGH to PCMCIA and CS */
|
||||
PCFR |= PCFR_OPDE;
|
||||
}
|
||||
|
||||
MACHINE_START(TRIZEPS4, "Keith und Koep Trizeps IV module")
|
||||
/* MAINTAINER("Jürgen Schindele") */
|
||||
.phys_io = 0x40000000,
|
||||
.io_pg_offst = (io_p2v(0x40000000) >> 18) & 0xfffc,
|
||||
.boot_params = TRIZEPS4_SDRAM_BASE + 0x100,
|
||||
.fixup = trizeps4_fixup,
|
||||
.init_machine = trizeps4_init,
|
||||
.map_io = trizeps4_map_io,
|
||||
.init_irq = pxa_init_irq,
|
||||
.timer = &pxa_timer,
|
||||
MACHINE_END
|
||||
|
||||
|
|
@ -1329,6 +1329,7 @@
|
|||
#define GPIO84_NSRXD 84 /* NSSP receive */
|
||||
#define GPIO85_nPCE_1 85 /* Card Enable for Card Space (PXA27x) */
|
||||
#define GPIO92_MMCDAT0 92 /* MMC DAT0 (PXA27x) */
|
||||
#define GPIO102_nPCE_1 102 /* PCMCIA (PXA27x) */
|
||||
#define GPIO109_MMCDAT1 109 /* MMC DAT1 (PXA27x) */
|
||||
#define GPIO110_MMCDAT2 110 /* MMC DAT2 (PXA27x) */
|
||||
#define GPIO110_MMCCS0 110 /* MMC Chip Select 0 (PXA27x) */
|
||||
|
|
@ -1471,6 +1472,7 @@
|
|||
#define GPIO84_NSSP_RX (84 | GPIO_ALT_FN_2_IN)
|
||||
#define GPIO85_nPCE_1_MD (85 | GPIO_ALT_FN_1_OUT)
|
||||
#define GPIO92_MMCDAT0_MD (92 | GPIO_ALT_FN_1_OUT)
|
||||
#define GPIO102_nPCE_1_MD (102 | GPIO_ALT_FN_1_OUT)
|
||||
#define GPIO104_pSKTSEL_MD (104 | GPIO_ALT_FN_1_OUT)
|
||||
#define GPIO109_MMCDAT1_MD (109 | GPIO_ALT_FN_1_OUT)
|
||||
#define GPIO110_MMCDAT2_MD (110 | GPIO_ALT_FN_1_OUT)
|
||||
|
|
|
|||
|
|
@ -0,0 +1,106 @@
|
|||
/************************************************************************
|
||||
* Include file for TRIZEPS4 SoM and ConXS eval-board
|
||||
* Copyright (c) Jürgen Schindele
|
||||
* 2006
|
||||
************************************************************************/
|
||||
|
||||
/*
|
||||
* Includes/Defines
|
||||
*/
|
||||
#ifndef _TRIPEPS4_H_
|
||||
#define _TRIPEPS4_H_
|
||||
|
||||
/* physical memory regions */
|
||||
#define TRIZEPS4_FLASH_PHYS (PXA_CS0_PHYS) /* Flash region */
|
||||
#define TRIZEPS4_DISK_PHYS (PXA_CS1_PHYS) /* Disk On Chip region */
|
||||
#define TRIZEPS4_ETH_PHYS (PXA_CS2_PHYS) /* Ethernet DM9000 region */
|
||||
#define TRIZEPS4_PIC_PHYS (PXA_CS3_PHYS) /* Logic chip on ConXS-Board */
|
||||
#define TRIZEPS4_SDRAM_BASE 0xa0000000 /* SDRAM region */
|
||||
|
||||
#define TRIZEPS4_CFSR_PHYS (PXA_CS3_PHYS) /* Logic chip on ConXS-Board CSFR register */
|
||||
#define TRIZEPS4_BOCR_PHYS (PXA_CS3_PHYS+0x02000000) /* Logic chip on ConXS-Board BOCR register */
|
||||
#define TRIZEPS4_IRCR_PHYS (PXA_CS3_PHYS+0x02400000) /* Logic chip on ConXS-Board IRCR register*/
|
||||
#define TRIZEPS4_UPSR_PHYS (PXA_CS3_PHYS+0x02800000) /* Logic chip on ConXS-Board UPSR register*/
|
||||
#define TRIZEPS4_DICR_PHYS (PXA_CS3_PHYS+0x03800000) /* Logic chip on ConXS-Board DICR register*/
|
||||
|
||||
/* virtual memory regions */
|
||||
#define TRIZEPS4_DISK_VIRT 0xF0000000 /* Disk On Chip region */
|
||||
|
||||
#define TRIZEPS4_PIC_VIRT 0xF0100000 /* not used */
|
||||
#define TRIZEPS4_CFSR_VIRT 0xF0100000
|
||||
#define TRIZEPS4_BOCR_VIRT 0xF0200000
|
||||
#define TRIZEPS4_DICR_VIRT 0xF0300000
|
||||
#define TRIZEPS4_IRCR_VIRT 0xF0400000
|
||||
#define TRIZEPS4_UPSR_VIRT 0xF0500000
|
||||
|
||||
/* size of flash */
|
||||
#define TRIZEPS4_FLASH_SIZE 0x02000000 /* Flash size 32 MB */
|
||||
|
||||
/* Ethernet Controller Davicom DM9000 */
|
||||
#define GPIO_DM9000 101
|
||||
#define TRIZEPS4_ETH_IRQ IRQ_GPIO(GPIO_DM9000)
|
||||
|
||||
/* UCB1400 audio / TS-controller */
|
||||
#define GPIO_UCB1400 1
|
||||
#define TRIZEPS4_UCB1400_IRQ IRQ_GPIO(GPIO_UCB1400)
|
||||
|
||||
/* PCMCIA socket Compact Flash */
|
||||
#define GPIO_PCD 11 /* PCMCIA Card Detect */
|
||||
#define TRIZEPS4_CD_IRQ IRQ_GPIO(GPIO_PCD)
|
||||
#define GPIO_PRDY 13 /* READY / nINT */
|
||||
#define TRIZEPS4_READY_NINT IRQ_GPIO(GPIO_PRDY)
|
||||
|
||||
/* MMC socket */
|
||||
#define GPIO_MMC_DET 12
|
||||
#define TRIZEPS4_MMC_IRQ IRQ_GPIO(GPIO_MMC_DET)
|
||||
|
||||
/* LEDS using tx2 / rx2 */
|
||||
#define GPIO_SYS_BUSY_LED 46
|
||||
#define GPIO_HEARTBEAT_LED 47
|
||||
|
||||
/* Off-module PIC on ConXS board */
|
||||
#define GPIO_PIC 0
|
||||
#define TRIZEPS4_PIC_IRQ IRQ_GPIO(GPIO_PIC)
|
||||
|
||||
#define CFSR_P2V(x) ((x) - TRIZEPS4_CFSR_PHYS + TRIZEPS4_CFSR_VIRT)
|
||||
#define CFSR_V2P(x) ((x) - TRIZEPS4_CFSR_VIRT + TRIZEPS4_CFSR_PHYS)
|
||||
|
||||
#define BCR_P2V(x) ((x) - TRIZEPS4_BOCR_PHYS + TRIZEPS4_BOCR_VIRT)
|
||||
#define BCR_V2P(x) ((x) - TRIZEPS4_BOCR_VIRT + TRIZEPS4_BOCR_PHYS)
|
||||
|
||||
#define DCR_P2V(x) ((x) - TRIZEPS4_DICR_PHYS + TRIZEPS4_DICR_VIRT)
|
||||
#define DCR_V2P(x) ((x) - TRIZEPS4_DICR_VIRT + TRIZEPS4_DICR_PHYS)
|
||||
|
||||
#ifndef __ASSEMBLY__
|
||||
#define ConXS_CFSR (*((volatile unsigned short *)CFSR_P2V(0x0C000000)))
|
||||
#define ConXS_BCR (*((volatile unsigned short *)BCR_P2V(0x0E000000)))
|
||||
#define ConXS_DCR (*((volatile unsigned short *)DCR_P2V(0x0F800000)))
|
||||
#else
|
||||
#define ConXS_CFSR CFSR_P2V(0x0C000000)
|
||||
#define ConXS_BCR BCR_P2V(0x0E000000)
|
||||
#define ConXS_DCR DCR_P2V(0x0F800000)
|
||||
#endif
|
||||
|
||||
#define ConXS_CFSR_BVD_MASK 0x0003
|
||||
#define ConXS_CFSR_BVD1 (1 << 0)
|
||||
#define ConXS_CFSR_BVD2 (1 << 1)
|
||||
#define ConXS_CFSR_VS_MASK 0x000C
|
||||
#define ConXS_CFSR_VS1 (1 << 2)
|
||||
#define ConXS_CFSR_VS2 (1 << 3)
|
||||
#define ConXS_CFSR_VS_5V (0x3 << 2)
|
||||
#define ConXS_CFSR_VS_3V3 0x0
|
||||
|
||||
#define ConXS_BCR_S0_POW_EN0 (1 << 0)
|
||||
#define ConXS_BCR_S0_POW_EN1 (1 << 1)
|
||||
#define ConXS_BCR_L_DISP (1 << 4)
|
||||
#define ConXS_BCR_CF_BUF_EN (1 << 5)
|
||||
#define ConXS_BCR_CF_RESET (1 << 7)
|
||||
#define ConXS_BCR_S0_VCC_3V3 0x1
|
||||
#define ConXS_BCR_S0_VCC_5V0 0x2
|
||||
#define ConXS_BCR_S0_VPP_12V 0x4
|
||||
#define ConXS_BCR_S0_VPP_3V3 0x8
|
||||
|
||||
#define ConXS_IRCR_MODE (1 << 0)
|
||||
#define ConXS_IRCR_SD (1 << 1)
|
||||
|
||||
#endif /* _TRIPEPS4_H_ */
|
||||
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