x86: multi-byte single instruction NOPs
Add support for and use the multi-byte NOPs recently documented to be available on all PentiumPro and later processors. This patch only applies cleanly on top of the "x86: misc. constifications" patch sent earlier. [ tglx: arch/x86 adaptation ] Signed-off-by: Jan Beulich <jbeulich@novell.com> Signed-off-by: Andi Kleen <ak@suse.de> Signed-off-by: Ingo Molnar <mingo@elte.hu> Signed-off-by: Thomas Gleixner <tglx@linutronix.de> arch/x86/kernel/alternative.c | 23 ++++++++++++++++++++++- include/asm-x86/processor_32.h | 22 ++++++++++++++++++++++ include/asm-x86/processor_64.h | 22 ++++++++++++++++++++++ 3 files changed, 66 insertions(+), 1 deletion(-)
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c861eff88c
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32c464f5d9
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@ -116,12 +116,31 @@ static const unsigned char *const k7_nops[ASM_NOP_MAX+1] = {
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};
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#endif
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#ifdef P6_NOP1
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asm("\t.section .rodata, \"a\"\np6nops: "
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P6_NOP1 P6_NOP2 P6_NOP3 P6_NOP4 P6_NOP5 P6_NOP6
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P6_NOP7 P6_NOP8);
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extern const unsigned char p6nops[];
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static const unsigned char *const p6_nops[ASM_NOP_MAX+1] = {
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NULL,
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p6nops,
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p6nops + 1,
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p6nops + 1 + 2,
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p6nops + 1 + 2 + 3,
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p6nops + 1 + 2 + 3 + 4,
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p6nops + 1 + 2 + 3 + 4 + 5,
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p6nops + 1 + 2 + 3 + 4 + 5 + 6,
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p6nops + 1 + 2 + 3 + 4 + 5 + 6 + 7,
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};
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#endif
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#ifdef CONFIG_X86_64
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extern char __vsyscall_0;
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static inline const unsigned char*const * find_nop_table(void)
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{
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return k8_nops;
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return boot_cpu_data.x86_vendor != X86_VENDOR_INTEL ||
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boot_cpu_data.x86 < 6 ? k8_nops : p6_nops;
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}
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#else /* CONFIG_X86_64 */
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@ -132,6 +151,8 @@ static const struct nop {
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} noptypes[] = {
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{ X86_FEATURE_K8, k8_nops },
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{ X86_FEATURE_K7, k7_nops },
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{ X86_FEATURE_P4, p6_nops },
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{ X86_FEATURE_P3, p6_nops },
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{ -1, NULL }
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};
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@ -677,6 +677,17 @@ static inline unsigned int cpuid_edx(unsigned int op)
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#define K7_NOP7 ".byte 0x8D,0x04,0x05,0,0,0,0\n"
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#define K7_NOP8 K7_NOP7 ASM_NOP1
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/* P6 nops */
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/* uses eax dependencies (Intel-recommended choice) */
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#define P6_NOP1 GENERIC_NOP1
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#define P6_NOP2 ".byte 0x66,0x90\n"
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#define P6_NOP3 ".byte 0x0f,0x1f,0x00\n"
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#define P6_NOP4 ".byte 0x0f,0x1f,0x40,0\n"
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#define P6_NOP5 ".byte 0x0f,0x1f,0x44,0x00,0\n"
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#define P6_NOP6 ".byte 0x66,0x0f,0x1f,0x44,0x00,0\n"
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#define P6_NOP7 ".byte 0x0f,0x1f,0x80,0,0,0,0\n"
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#define P6_NOP8 ".byte 0x0f,0x1f,0x84,0x00,0,0,0,0\n"
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#ifdef CONFIG_MK8
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#define ASM_NOP1 K8_NOP1
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#define ASM_NOP2 K8_NOP2
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@ -695,6 +706,17 @@ static inline unsigned int cpuid_edx(unsigned int op)
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#define ASM_NOP6 K7_NOP6
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#define ASM_NOP7 K7_NOP7
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#define ASM_NOP8 K7_NOP8
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#elif defined(CONFIG_M686) || defined(CONFIG_MPENTIUMII) || \
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defined(CONFIG_MPENTIUMIII) || defined(CONFIG_MPENTIUMM) || \
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defined(CONFIG_MCORE2) || defined(CONFIG_PENTIUM4)
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#define ASM_NOP1 P6_NOP1
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#define ASM_NOP2 P6_NOP2
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#define ASM_NOP3 P6_NOP3
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#define ASM_NOP4 P6_NOP4
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#define ASM_NOP5 P6_NOP5
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#define ASM_NOP6 P6_NOP6
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#define ASM_NOP7 P6_NOP7
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#define ASM_NOP8 P6_NOP8
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#else
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#define ASM_NOP1 GENERIC_NOP1
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#define ASM_NOP2 GENERIC_NOP2
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@ -334,6 +334,16 @@ struct extended_sigtable {
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};
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#if defined(CONFIG_MPSC) || defined(CONFIG_MCORE2)
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#define ASM_NOP1 P6_NOP1
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#define ASM_NOP2 P6_NOP2
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#define ASM_NOP3 P6_NOP3
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#define ASM_NOP4 P6_NOP4
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#define ASM_NOP5 P6_NOP5
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#define ASM_NOP6 P6_NOP6
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#define ASM_NOP7 P6_NOP7
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#define ASM_NOP8 P6_NOP8
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#else
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#define ASM_NOP1 K8_NOP1
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#define ASM_NOP2 K8_NOP2
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#define ASM_NOP3 K8_NOP3
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@ -342,6 +352,7 @@ struct extended_sigtable {
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#define ASM_NOP6 K8_NOP6
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#define ASM_NOP7 K8_NOP7
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#define ASM_NOP8 K8_NOP8
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#endif
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/* Opteron nops */
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#define K8_NOP1 ".byte 0x90\n"
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@ -353,6 +364,17 @@ struct extended_sigtable {
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#define K8_NOP7 K8_NOP4 K8_NOP3
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#define K8_NOP8 K8_NOP4 K8_NOP4
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/* P6 nops */
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/* uses eax dependencies (Intel-recommended choice) */
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#define P6_NOP1 ".byte 0x90\n"
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#define P6_NOP2 ".byte 0x66,0x90\n"
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#define P6_NOP3 ".byte 0x0f,0x1f,0x00\n"
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#define P6_NOP4 ".byte 0x0f,0x1f,0x40,0\n"
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#define P6_NOP5 ".byte 0x0f,0x1f,0x44,0x00,0\n"
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#define P6_NOP6 ".byte 0x66,0x0f,0x1f,0x44,0x00,0\n"
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#define P6_NOP7 ".byte 0x0f,0x1f,0x80,0,0,0,0\n"
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#define P6_NOP8 ".byte 0x0f,0x1f,0x84,0x00,0,0,0,0\n"
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#define ASM_NOP_MAX 8
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/* REP NOP (PAUSE) is a good thing to insert into busy-wait loops. */
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