The i.MX SoC update for 3.19:
- Update i.MX6 suspend code to check DDR instead of CPU type, as the
difference we need to handle is between LPDDR2 and DDR3, not SoCs.
- Set anatop properly for LPDDR2 in DSM mode
- Add support for new SoC LS1021A which integrates dual Cortex-A7
- Add ENET initialization for i.MX6SX platform
- Add cpufreq support for i.MX53 platform
- Add a SNVS based poweroff driver for i.MX6 platforms
- Use ARM Global Timer as clocksource on VF610
Note: the change set is built on top of tag imx-fixes-3.18-2 to resolve
a conflict on file arch/arm/mach-imx/clk-vf610.c.
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Merge tag 'imx-soc-3.19' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux into next/soc
Pull "The i.MX SoC update for 3.19" from Shawn Guo
- Update i.MX6 suspend code to check DDR instead of CPU type, as the
difference we need to handle is between LPDDR2 and DDR3, not SoCs.
- Set anatop properly for LPDDR2 in DSM mode
- Add support for new SoC LS1021A which integrates dual Cortex-A7
- Add ENET initialization for i.MX6SX platform
- Add cpufreq support for i.MX53 platform
- Add a SNVS based poweroff driver for i.MX6 platforms
- Use ARM Global Timer as clocksource on VF610
Note: the change set is built on top of tag imx-fixes-3.18-2 to resolve
a conflict on file arch/arm/mach-imx/clk-vf610.c.
* tag 'imx-soc-3.19' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux:
power: reset: imx-snvs-poweroff: add power off driver for i.mx6
ARM: imx: temporarily remove CONFIG_SOC_FSL from LS1021A
ARM: imx: clk-vf610: get input clocks from assigned clocks
ARM: imx: Add Freescale LS1021A SMP support
ARM: imx: Add initial support for Freescale LS1021A
ARM: imx53: add cpufreq support
ARM: imx53: clk: add ARM clock
ARM: imx: add CPU clock type
ARM: imx5: add step clock, used when reprogramming PLL1
ARM: imx: add enet init for i.mx6sx
ARM: imx6sx: add imx6sx iomux-gpr field define
ARM: vf610: Add ARM Global Timer clocksource option
ARM: imx: add anatop settings for LPDDR2 when enter DSM mode
ARM: imx: replace cpu type check with ddr type check
ARM: imx: Fix the removal of CONFIG_SPI option
ARM: imx: clk-vf610: define PLL's clock tree
Signed-off-by; Arnd Bergmann <arnd@arndb.de>
This commit is contained in:
Arnd Bergmann
Коммит
32e049ad79
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@ -0,0 +1,23 @@
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i.mx6 Poweroff Driver
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SNVS_LPCR in SNVS module can power off the whole system by pull
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PMIC_ON_REQ low if PMIC_ON_REQ is connected with external PMIC.
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If you don't want to use PMIC_ON_REQ as power on/off control,
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please set status='disabled' to disable this driver.
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Required Properties:
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-compatible: "fsl,sec-v4.0-poweroff"
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-reg: Specifies the physical address of the SNVS_LPCR register
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Example:
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snvs@020cc000 {
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compatible = "fsl,sec-v4.0-mon", "simple-bus";
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0 0x020cc000 0x4000>;
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.....
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snvs_poweroff: snvs-poweroff@38 {
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compatible = "fsl,sec-v4.0-poweroff";
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reg = <0x38 0x4>;
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};
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}
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@ -97,6 +97,7 @@ CONFIG_SERIAL_IMX_CONSOLE=y
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# CONFIG_HW_RANDOM is not set
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CONFIG_I2C_CHARDEV=y
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CONFIG_I2C_IMX=y
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CONFIG_SPI=y
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CONFIG_SPI_IMX=y
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CONFIG_SPI_SPIDEV=y
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CONFIG_GPIO_SYSFS=y
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@ -158,6 +158,7 @@ CONFIG_I2C_CHARDEV=y
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CONFIG_I2C_ALGOPCF=m
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CONFIG_I2C_ALGOPCA=m
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CONFIG_I2C_IMX=y
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CONFIG_SPI=y
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CONFIG_SPI_IMX=y
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CONFIG_GPIO_SYSFS=y
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CONFIG_GPIO_MC9S08DZ60=y
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@ -633,12 +633,41 @@ config SOC_VF610
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bool "Vybrid Family VF610 support"
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select ARM_GIC
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select PINCTRL_VF610
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select VF_PIT_TIMER
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select PL310_ERRATA_769419 if CACHE_L2X0
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help
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This enable support for Freescale Vybrid VF610 processor.
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choice
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prompt "Clocksource for scheduler clock"
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depends on SOC_VF610
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default VF_USE_ARM_GLOBAL_TIMER
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config VF_USE_ARM_GLOBAL_TIMER
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bool "Use ARM Global Timer"
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select ARM_GLOBAL_TIMER
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select CLKSRC_ARM_GLOBAL_TIMER_SCHED_CLOCK
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help
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Use the ARM Global Timer as clocksource
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config VF_USE_PIT_TIMER
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bool "Use PIT timer"
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select VF_PIT_TIMER
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help
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Use SoC Periodic Interrupt Timer (PIT) as clocksource
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endchoice
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config SOC_LS1021A
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bool "Freescale LS1021A support"
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select ARM_GIC
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select HAVE_ARM_ARCH_TIMER
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select PCI_DOMAINS if PCI
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select ZONE_DMA if ARM_LPAE
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help
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This enable support for Freescale LS1021A processor.
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endif
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source "arch/arm/mach-imx/devices/Kconfig"
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@ -12,7 +12,7 @@ obj-$(CONFIG_SOC_IMX31) += mm-imx3.o cpu-imx31.o clk-imx31.o iomux-imx31.o ehci-
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obj-$(CONFIG_SOC_IMX35) += mm-imx3.o cpu-imx35.o clk-imx35.o ehci-imx35.o pm-imx3.o
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imx5-pm-$(CONFIG_PM) += pm-imx5.o
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obj-$(CONFIG_SOC_IMX5) += cpu-imx5.o clk-imx51-imx53.o $(imx5-pm-y)
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obj-$(CONFIG_SOC_IMX5) += cpu-imx5.o clk-imx51-imx53.o clk-cpu.o $(imx5-pm-y)
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obj-$(CONFIG_COMMON_CLK) += clk-pllv1.o clk-pllv2.o clk-pllv3.o clk-gate2.o \
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clk-pfd.o clk-busy.o clk.o \
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@ -89,7 +89,7 @@ obj-$(CONFIG_HAVE_IMX_ANATOP) += anatop.o
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obj-$(CONFIG_HAVE_IMX_GPC) += gpc.o
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obj-$(CONFIG_HAVE_IMX_MMDC) += mmdc.o
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obj-$(CONFIG_HAVE_IMX_SRC) += src.o
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ifdef CONFIG_SOC_IMX6
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ifneq ($(CONFIG_SOC_IMX6)$(CONFIG_SOC_LS1021A),)
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AFLAGS_headsmp.o :=-Wa,-march=armv7-a
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obj-$(CONFIG_SMP) += headsmp.o platsmp.o
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obj-$(CONFIG_HOTPLUG_CPU) += hotplug.o
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@ -110,4 +110,6 @@ obj-$(CONFIG_SOC_IMX53) += mach-imx53.o
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obj-$(CONFIG_SOC_VF610) += clk-vf610.o mach-vf610.o
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obj-$(CONFIG_SOC_LS1021A) += mach-ls1021a.o
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obj-y += devices/
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@ -30,8 +30,11 @@
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#define ANADIG_DIGPROG_IMX6SL 0x280
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#define BM_ANADIG_REG_2P5_ENABLE_WEAK_LINREG 0x40000
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#define BM_ANADIG_REG_2P5_ENABLE_PULLDOWN 0x8
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#define BM_ANADIG_REG_CORE_FET_ODRIVE 0x20000000
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#define BM_ANADIG_ANA_MISC0_STOP_MODE_CONFIG 0x1000
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/* Below MISC0_DISCON_HIGH_SNVS is only for i.MX6SL */
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#define BM_ANADIG_ANA_MISC0_DISCON_HIGH_SNVS 0x2000
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#define BM_ANADIG_USB_CHRG_DETECT_CHK_CHRG_B 0x80000
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#define BM_ANADIG_USB_CHRG_DETECT_EN_B 0x100000
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@ -56,16 +59,43 @@ static void imx_anatop_enable_fet_odrive(bool enable)
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BM_ANADIG_REG_CORE_FET_ODRIVE);
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}
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static inline void imx_anatop_enable_2p5_pulldown(bool enable)
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{
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regmap_write(anatop, ANADIG_REG_2P5 + (enable ? REG_SET : REG_CLR),
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BM_ANADIG_REG_2P5_ENABLE_PULLDOWN);
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}
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static inline void imx_anatop_disconnect_high_snvs(bool enable)
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{
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regmap_write(anatop, ANADIG_ANA_MISC0 + (enable ? REG_SET : REG_CLR),
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BM_ANADIG_ANA_MISC0_DISCON_HIGH_SNVS);
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}
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void imx_anatop_pre_suspend(void)
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{
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imx_anatop_enable_weak2p5(true);
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if (imx_mmdc_get_ddr_type() == IMX_DDR_TYPE_LPDDR2)
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imx_anatop_enable_2p5_pulldown(true);
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else
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imx_anatop_enable_weak2p5(true);
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imx_anatop_enable_fet_odrive(true);
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if (cpu_is_imx6sl())
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imx_anatop_disconnect_high_snvs(true);
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}
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void imx_anatop_post_resume(void)
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{
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if (imx_mmdc_get_ddr_type() == IMX_DDR_TYPE_LPDDR2)
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imx_anatop_enable_2p5_pulldown(false);
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else
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imx_anatop_enable_weak2p5(false);
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imx_anatop_enable_fet_odrive(false);
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imx_anatop_enable_weak2p5(false);
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if (cpu_is_imx6sl())
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imx_anatop_disconnect_high_snvs(false);
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}
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static void imx_anatop_usb_chrg_detect_disable(void)
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@ -0,0 +1,107 @@
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/*
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* Copyright (c) 2014 Lucas Stach <l.stach@pengutronix.de>, Pengutronix
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* http://www.opensource.org/licenses/gpl-license.html
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* http://www.gnu.org/copyleft/gpl.html
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*/
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#include <linux/clk.h>
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#include <linux/clk-provider.h>
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#include <linux/slab.h>
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struct clk_cpu {
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struct clk_hw hw;
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struct clk *div;
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struct clk *mux;
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struct clk *pll;
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struct clk *step;
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};
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static inline struct clk_cpu *to_clk_cpu(struct clk_hw *hw)
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{
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return container_of(hw, struct clk_cpu, hw);
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}
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static unsigned long clk_cpu_recalc_rate(struct clk_hw *hw,
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unsigned long parent_rate)
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{
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struct clk_cpu *cpu = to_clk_cpu(hw);
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return clk_get_rate(cpu->div);
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}
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static long clk_cpu_round_rate(struct clk_hw *hw, unsigned long rate,
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unsigned long *prate)
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{
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struct clk_cpu *cpu = to_clk_cpu(hw);
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return clk_round_rate(cpu->pll, rate);
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}
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static int clk_cpu_set_rate(struct clk_hw *hw, unsigned long rate,
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unsigned long parent_rate)
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{
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struct clk_cpu *cpu = to_clk_cpu(hw);
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int ret;
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/* switch to PLL bypass clock */
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ret = clk_set_parent(cpu->mux, cpu->step);
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if (ret)
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return ret;
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/* reprogram PLL */
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ret = clk_set_rate(cpu->pll, rate);
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if (ret) {
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clk_set_parent(cpu->mux, cpu->pll);
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return ret;
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}
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/* switch back to PLL clock */
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clk_set_parent(cpu->mux, cpu->pll);
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/* Ensure the divider is what we expect */
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clk_set_rate(cpu->div, rate);
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return 0;
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}
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static const struct clk_ops clk_cpu_ops = {
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.recalc_rate = clk_cpu_recalc_rate,
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.round_rate = clk_cpu_round_rate,
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.set_rate = clk_cpu_set_rate,
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};
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struct clk *imx_clk_cpu(const char *name, const char *parent_name,
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struct clk *div, struct clk *mux, struct clk *pll,
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struct clk *step)
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{
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struct clk_cpu *cpu;
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struct clk *clk;
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struct clk_init_data init;
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|
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cpu = kzalloc(sizeof(*cpu), GFP_KERNEL);
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if (!cpu)
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return ERR_PTR(-ENOMEM);
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cpu->div = div;
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cpu->mux = mux;
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cpu->pll = pll;
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cpu->step = step;
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|
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init.name = name;
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init.ops = &clk_cpu_ops;
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init.flags = 0;
|
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init.parent_names = &parent_name;
|
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init.num_parents = 1;
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|
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cpu->hw.init = &init;
|
||||
|
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clk = clk_register(NULL, &cpu->hw);
|
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if (IS_ERR(clk))
|
||||
kfree(cpu);
|
||||
|
||||
return clk;
|
||||
}
|
||||
|
|
@ -125,6 +125,8 @@ static const char *mx53_spdif_xtal_sel[] = { "osc", "ckih", "ckih2", "pll4_sw",
|
|||
static const char *spdif_sel[] = { "pll1_sw", "pll2_sw", "pll3_sw", "spdif_xtal_sel", };
|
||||
static const char *spdif0_com_sel[] = { "spdif0_podf", "ssi1_root_gate", };
|
||||
static const char *mx51_spdif1_com_sel[] = { "spdif1_podf", "ssi2_root_gate", };
|
||||
static const char *step_sels[] = { "lp_apm", };
|
||||
static const char *cpu_podf_sels[] = { "pll1_sw", "step_sel" };
|
||||
|
||||
static struct clk *clk[IMX5_CLK_END];
|
||||
static struct clk_onecell_data clk_data;
|
||||
|
|
@ -193,7 +195,9 @@ static void __init mx5_clocks_common_init(void __iomem *ccm_base)
|
|||
clk[IMX5_CLK_USB_PHY_PODF] = imx_clk_divider("usb_phy_podf", "usb_phy_pred", MXC_CCM_CDCDR, 0, 3);
|
||||
clk[IMX5_CLK_USB_PHY_SEL] = imx_clk_mux("usb_phy_sel", MXC_CCM_CSCMR1, 26, 1,
|
||||
usb_phy_sel_str, ARRAY_SIZE(usb_phy_sel_str));
|
||||
clk[IMX5_CLK_CPU_PODF] = imx_clk_divider("cpu_podf", "pll1_sw", MXC_CCM_CACRR, 0, 3);
|
||||
clk[IMX5_CLK_STEP_SEL] = imx_clk_mux("step_sel", MXC_CCM_CCSR, 7, 2, step_sels, ARRAY_SIZE(step_sels));
|
||||
clk[IMX5_CLK_CPU_PODF_SEL] = imx_clk_mux("cpu_podf_sel", MXC_CCM_CCSR, 2, 1, cpu_podf_sels, ARRAY_SIZE(cpu_podf_sels));
|
||||
clk[IMX5_CLK_CPU_PODF] = imx_clk_divider("cpu_podf", "cpu_podf_sel", MXC_CCM_CACRR, 0, 3);
|
||||
clk[IMX5_CLK_DI_PRED] = imx_clk_divider("di_pred", "pll3_sw", MXC_CCM_CDCDR, 6, 3);
|
||||
clk[IMX5_CLK_IIM_GATE] = imx_clk_gate2("iim_gate", "ipg", MXC_CCM_CCGR0, 30);
|
||||
clk[IMX5_CLK_UART1_IPG_GATE] = imx_clk_gate2("uart1_ipg_gate", "ipg", MXC_CCM_CCGR1, 6);
|
||||
|
|
@ -537,6 +541,11 @@ static void __init mx53_clocks_init(struct device_node *np)
|
|||
clk[IMX5_CLK_CKO2] = imx_clk_gate2("cko2", "cko2_podf", MXC_CCM_CCOSR, 24);
|
||||
clk[IMX5_CLK_SPDIF_XTAL_SEL] = imx_clk_mux("spdif_xtal_sel", MXC_CCM_CSCMR1, 2, 2,
|
||||
mx53_spdif_xtal_sel, ARRAY_SIZE(mx53_spdif_xtal_sel));
|
||||
clk[IMX5_CLK_ARM] = imx_clk_cpu("arm", "cpu_podf",
|
||||
clk[IMX5_CLK_CPU_PODF],
|
||||
clk[IMX5_CLK_CPU_PODF_SEL],
|
||||
clk[IMX5_CLK_PLL1_SW],
|
||||
clk[IMX5_CLK_STEP_SEL]);
|
||||
|
||||
imx_check_clocks(clk, ARRAY_SIZE(clk));
|
||||
|
||||
|
|
@ -551,6 +560,9 @@ static void __init mx53_clocks_init(struct device_node *np)
|
|||
/* move can bus clk to 24MHz */
|
||||
clk_set_parent(clk[IMX5_CLK_CAN_SEL], clk[IMX5_CLK_LP_APM]);
|
||||
|
||||
/* make sure step clock is running from 24MHz */
|
||||
clk_set_parent(clk[IMX5_CLK_STEP_SEL], clk[IMX5_CLK_LP_APM]);
|
||||
|
||||
clk_prepare_enable(clk[IMX5_CLK_IIM_GATE]);
|
||||
imx_print_silicon_rev("i.MX53", mx53_revision());
|
||||
clk_disable_unprepare(clk[IMX5_CLK_IIM_GATE]);
|
||||
|
|
|
|||
|
|
@ -58,8 +58,14 @@
|
|||
#define PFD_PLL1_BASE (anatop_base + 0x2b0)
|
||||
#define PFD_PLL2_BASE (anatop_base + 0x100)
|
||||
#define PFD_PLL3_BASE (anatop_base + 0xf0)
|
||||
#define PLL1_CTRL (anatop_base + 0x270)
|
||||
#define PLL2_CTRL (anatop_base + 0x30)
|
||||
#define PLL3_CTRL (anatop_base + 0x10)
|
||||
#define PLL4_CTRL (anatop_base + 0x70)
|
||||
#define PLL5_CTRL (anatop_base + 0xe0)
|
||||
#define PLL6_CTRL (anatop_base + 0xa0)
|
||||
#define PLL7_CTRL (anatop_base + 0x20)
|
||||
#define ANA_MISC1 (anatop_base + 0x160)
|
||||
|
||||
static void __iomem *anatop_base;
|
||||
static void __iomem *ccm_base;
|
||||
|
|
@ -67,25 +73,34 @@ static void __iomem *ccm_base;
|
|||
/* sources for multiplexer clocks, this is used multiple times */
|
||||
static const char *fast_sels[] = { "firc", "fxosc", };
|
||||
static const char *slow_sels[] = { "sirc_32k", "sxosc", };
|
||||
static const char *pll1_sels[] = { "pll1_main", "pll1_pfd1", "pll1_pfd2", "pll1_pfd3", "pll1_pfd4", };
|
||||
static const char *pll2_sels[] = { "pll2_main", "pll2_pfd1", "pll2_pfd2", "pll2_pfd3", "pll2_pfd4", };
|
||||
static const char *sys_sels[] = { "fast_clk_sel", "slow_clk_sel", "pll2_pfd_sel", "pll2_main", "pll1_pfd_sel", "pll3_main", };
|
||||
static const char *pll1_sels[] = { "pll1_sys", "pll1_pfd1", "pll1_pfd2", "pll1_pfd3", "pll1_pfd4", };
|
||||
static const char *pll2_sels[] = { "pll2_bus", "pll2_pfd1", "pll2_pfd2", "pll2_pfd3", "pll2_pfd4", };
|
||||
static const char *pll_bypass_src_sels[] = { "fast_clk_sel", "lvds1_in", };
|
||||
static const char *pll1_bypass_sels[] = { "pll1", "pll1_bypass_src", };
|
||||
static const char *pll2_bypass_sels[] = { "pll2", "pll2_bypass_src", };
|
||||
static const char *pll3_bypass_sels[] = { "pll3", "pll3_bypass_src", };
|
||||
static const char *pll4_bypass_sels[] = { "pll4", "pll4_bypass_src", };
|
||||
static const char *pll5_bypass_sels[] = { "pll5", "pll5_bypass_src", };
|
||||
static const char *pll6_bypass_sels[] = { "pll6", "pll6_bypass_src", };
|
||||
static const char *pll7_bypass_sels[] = { "pll7", "pll7_bypass_src", };
|
||||
static const char *sys_sels[] = { "fast_clk_sel", "slow_clk_sel", "pll2_pfd_sel", "pll2_bus", "pll1_pfd_sel", "pll3_usb_otg", };
|
||||
static const char *ddr_sels[] = { "pll2_pfd2", "sys_sel", };
|
||||
static const char *rmii_sels[] = { "enet_ext", "audio_ext", "enet_50m", "enet_25m", };
|
||||
static const char *enet_ts_sels[] = { "enet_ext", "fxosc", "audio_ext", "usb", "enet_ts", "enet_25m", "enet_50m", };
|
||||
static const char *esai_sels[] = { "audio_ext", "mlb", "spdif_rx", "pll4_main_div", };
|
||||
static const char *sai_sels[] = { "audio_ext", "mlb", "spdif_rx", "pll4_main_div", };
|
||||
static const char *esai_sels[] = { "audio_ext", "mlb", "spdif_rx", "pll4_audio_div", };
|
||||
static const char *sai_sels[] = { "audio_ext", "mlb", "spdif_rx", "pll4_audio_div", };
|
||||
static const char *nfc_sels[] = { "platform_bus", "pll1_pfd1", "pll3_pfd1", "pll3_pfd3", };
|
||||
static const char *qspi_sels[] = { "pll3_main", "pll3_pfd4", "pll2_pfd4", "pll1_pfd4", };
|
||||
static const char *esdhc_sels[] = { "pll3_main", "pll3_pfd3", "pll1_pfd3", "platform_bus", };
|
||||
static const char *dcu_sels[] = { "pll1_pfd2", "pll3_main", };
|
||||
static const char *qspi_sels[] = { "pll3_usb_otg", "pll3_pfd4", "pll2_pfd4", "pll1_pfd4", };
|
||||
static const char *esdhc_sels[] = { "pll3_usb_otg", "pll3_pfd3", "pll1_pfd3", "platform_bus", };
|
||||
static const char *dcu_sels[] = { "pll1_pfd2", "pll3_usb_otg", };
|
||||
static const char *gpu_sels[] = { "pll2_pfd2", "pll3_pfd2", };
|
||||
static const char *vadc_sels[] = { "pll6_main_div", "pll3_main_div", "pll3_main", };
|
||||
static const char *vadc_sels[] = { "pll6_video_div", "pll3_usb_otg_div", "pll3_usb_otg", };
|
||||
/* FTM counter clock source, not module clock */
|
||||
static const char *ftm_ext_sels[] = {"sirc_128k", "sxosc", "fxosc_half", "audio_ext", };
|
||||
static const char *ftm_fix_sels[] = { "sxosc", "ipg_bus", };
|
||||
|
||||
static struct clk_div_table pll4_main_div_table[] = {
|
||||
|
||||
static struct clk_div_table pll4_audio_div_table[] = {
|
||||
{ .val = 0, .div = 1 },
|
||||
{ .val = 1, .div = 2 },
|
||||
{ .val = 2, .div = 6 },
|
||||
|
|
@ -105,6 +120,17 @@ static unsigned int const clks_init_on[] __initconst = {
|
|||
VF610_CLK_DDR_SEL,
|
||||
};
|
||||
|
||||
static struct clk * __init vf610_get_fixed_clock(
|
||||
struct device_node *ccm_node, const char *name)
|
||||
{
|
||||
struct clk *clk = of_clk_get_by_name(ccm_node, name);
|
||||
|
||||
/* Backward compatibility if device tree is missing clks assignments */
|
||||
if (IS_ERR(clk))
|
||||
clk = imx_obtain_fixed_clock(name, 0);
|
||||
return clk;
|
||||
};
|
||||
|
||||
static void __init vf610_clocks_init(struct device_node *ccm_node)
|
||||
{
|
||||
struct device_node *np;
|
||||
|
|
@ -115,10 +141,13 @@ static void __init vf610_clocks_init(struct device_node *ccm_node)
|
|||
clk[VF610_CLK_SIRC_32K] = imx_clk_fixed("sirc_32k", 32000);
|
||||
clk[VF610_CLK_FIRC] = imx_clk_fixed("firc", 24000000);
|
||||
|
||||
clk[VF610_CLK_SXOSC] = imx_obtain_fixed_clock("sxosc", 0);
|
||||
clk[VF610_CLK_FXOSC] = imx_obtain_fixed_clock("fxosc", 0);
|
||||
clk[VF610_CLK_AUDIO_EXT] = imx_obtain_fixed_clock("audio_ext", 0);
|
||||
clk[VF610_CLK_ENET_EXT] = imx_obtain_fixed_clock("enet_ext", 0);
|
||||
clk[VF610_CLK_SXOSC] = vf610_get_fixed_clock(ccm_node, "sxosc");
|
||||
clk[VF610_CLK_FXOSC] = vf610_get_fixed_clock(ccm_node, "fxosc");
|
||||
clk[VF610_CLK_AUDIO_EXT] = vf610_get_fixed_clock(ccm_node, "audio_ext");
|
||||
clk[VF610_CLK_ENET_EXT] = vf610_get_fixed_clock(ccm_node, "enet_ext");
|
||||
|
||||
/* Clock source from external clock via LVDs PAD */
|
||||
clk[VF610_CLK_ANACLK1] = vf610_get_fixed_clock(ccm_node, "anaclk1");
|
||||
|
||||
clk[VF610_CLK_FXOSC_HALF] = imx_clk_fixed_factor("fxosc_half", "fxosc", 1, 2);
|
||||
|
||||
|
|
@ -133,31 +162,63 @@ static void __init vf610_clocks_init(struct device_node *ccm_node)
|
|||
clk[VF610_CLK_SLOW_CLK_SEL] = imx_clk_mux("slow_clk_sel", CCM_CCSR, 4, 1, slow_sels, ARRAY_SIZE(slow_sels));
|
||||
clk[VF610_CLK_FASK_CLK_SEL] = imx_clk_mux("fast_clk_sel", CCM_CCSR, 5, 1, fast_sels, ARRAY_SIZE(fast_sels));
|
||||
|
||||
clk[VF610_CLK_PLL1_MAIN] = imx_clk_fixed_factor("pll1_main", "fast_clk_sel", 22, 1);
|
||||
clk[VF610_CLK_PLL1_PFD1] = imx_clk_pfd("pll1_pfd1", "pll1_main", PFD_PLL1_BASE, 0);
|
||||
clk[VF610_CLK_PLL1_PFD2] = imx_clk_pfd("pll1_pfd2", "pll1_main", PFD_PLL1_BASE, 1);
|
||||
clk[VF610_CLK_PLL1_PFD3] = imx_clk_pfd("pll1_pfd3", "pll1_main", PFD_PLL1_BASE, 2);
|
||||
clk[VF610_CLK_PLL1_PFD4] = imx_clk_pfd("pll1_pfd4", "pll1_main", PFD_PLL1_BASE, 3);
|
||||
clk[VF610_CLK_PLL1_BYPASS_SRC] = imx_clk_mux("pll1_bypass_src", PLL1_CTRL, 14, 1, pll_bypass_src_sels, ARRAY_SIZE(pll_bypass_src_sels));
|
||||
clk[VF610_CLK_PLL2_BYPASS_SRC] = imx_clk_mux("pll2_bypass_src", PLL2_CTRL, 14, 1, pll_bypass_src_sels, ARRAY_SIZE(pll_bypass_src_sels));
|
||||
clk[VF610_CLK_PLL3_BYPASS_SRC] = imx_clk_mux("pll3_bypass_src", PLL3_CTRL, 14, 1, pll_bypass_src_sels, ARRAY_SIZE(pll_bypass_src_sels));
|
||||
clk[VF610_CLK_PLL4_BYPASS_SRC] = imx_clk_mux("pll4_bypass_src", PLL4_CTRL, 14, 1, pll_bypass_src_sels, ARRAY_SIZE(pll_bypass_src_sels));
|
||||
clk[VF610_CLK_PLL5_BYPASS_SRC] = imx_clk_mux("pll5_bypass_src", PLL5_CTRL, 14, 1, pll_bypass_src_sels, ARRAY_SIZE(pll_bypass_src_sels));
|
||||
clk[VF610_CLK_PLL6_BYPASS_SRC] = imx_clk_mux("pll6_bypass_src", PLL6_CTRL, 14, 1, pll_bypass_src_sels, ARRAY_SIZE(pll_bypass_src_sels));
|
||||
clk[VF610_CLK_PLL7_BYPASS_SRC] = imx_clk_mux("pll7_bypass_src", PLL7_CTRL, 14, 1, pll_bypass_src_sels, ARRAY_SIZE(pll_bypass_src_sels));
|
||||
|
||||
clk[VF610_CLK_PLL2_MAIN] = imx_clk_fixed_factor("pll2_main", "fast_clk_sel", 22, 1);
|
||||
clk[VF610_CLK_PLL2_PFD1] = imx_clk_pfd("pll2_pfd1", "pll2_main", PFD_PLL2_BASE, 0);
|
||||
clk[VF610_CLK_PLL2_PFD2] = imx_clk_pfd("pll2_pfd2", "pll2_main", PFD_PLL2_BASE, 1);
|
||||
clk[VF610_CLK_PLL2_PFD3] = imx_clk_pfd("pll2_pfd3", "pll2_main", PFD_PLL2_BASE, 2);
|
||||
clk[VF610_CLK_PLL2_PFD4] = imx_clk_pfd("pll2_pfd4", "pll2_main", PFD_PLL2_BASE, 3);
|
||||
clk[VF610_CLK_PLL1] = imx_clk_pllv3(IMX_PLLV3_GENERIC, "pll1", "pll1_bypass_src", PLL1_CTRL, 0x1);
|
||||
clk[VF610_CLK_PLL2] = imx_clk_pllv3(IMX_PLLV3_GENERIC, "pll2", "pll2_bypass_src", PLL2_CTRL, 0x1);
|
||||
clk[VF610_CLK_PLL3] = imx_clk_pllv3(IMX_PLLV3_USB, "pll3", "pll3_bypass_src", PLL3_CTRL, 0x1);
|
||||
clk[VF610_CLK_PLL4] = imx_clk_pllv3(IMX_PLLV3_AV, "pll4", "pll4_bypass_src", PLL4_CTRL, 0x7f);
|
||||
clk[VF610_CLK_PLL5] = imx_clk_pllv3(IMX_PLLV3_ENET, "pll5", "pll5_bypass_src", PLL5_CTRL, 0x3);
|
||||
clk[VF610_CLK_PLL6] = imx_clk_pllv3(IMX_PLLV3_AV, "pll6", "pll6_bypass_src", PLL6_CTRL, 0x7f);
|
||||
clk[VF610_CLK_PLL7] = imx_clk_pllv3(IMX_PLLV3_USB, "pll7", "pll7_bypass_src", PLL7_CTRL, 0x1);
|
||||
|
||||
clk[VF610_CLK_PLL3_MAIN] = imx_clk_fixed_factor("pll3_main", "fast_clk_sel", 20, 1);
|
||||
clk[VF610_CLK_PLL3_PFD1] = imx_clk_pfd("pll3_pfd1", "pll3_main", PFD_PLL3_BASE, 0);
|
||||
clk[VF610_CLK_PLL3_PFD2] = imx_clk_pfd("pll3_pfd2", "pll3_main", PFD_PLL3_BASE, 1);
|
||||
clk[VF610_CLK_PLL3_PFD3] = imx_clk_pfd("pll3_pfd3", "pll3_main", PFD_PLL3_BASE, 2);
|
||||
clk[VF610_CLK_PLL3_PFD4] = imx_clk_pfd("pll3_pfd4", "pll3_main", PFD_PLL3_BASE, 3);
|
||||
clk[VF610_PLL1_BYPASS] = imx_clk_mux_flags("pll1_bypass", PLL1_CTRL, 16, 1, pll1_bypass_sels, ARRAY_SIZE(pll1_bypass_sels), CLK_SET_RATE_PARENT);
|
||||
clk[VF610_PLL2_BYPASS] = imx_clk_mux_flags("pll2_bypass", PLL2_CTRL, 16, 1, pll2_bypass_sels, ARRAY_SIZE(pll2_bypass_sels), CLK_SET_RATE_PARENT);
|
||||
clk[VF610_PLL3_BYPASS] = imx_clk_mux_flags("pll3_bypass", PLL3_CTRL, 16, 1, pll3_bypass_sels, ARRAY_SIZE(pll3_bypass_sels), CLK_SET_RATE_PARENT);
|
||||
clk[VF610_PLL4_BYPASS] = imx_clk_mux_flags("pll4_bypass", PLL4_CTRL, 16, 1, pll4_bypass_sels, ARRAY_SIZE(pll4_bypass_sels), CLK_SET_RATE_PARENT);
|
||||
clk[VF610_PLL5_BYPASS] = imx_clk_mux_flags("pll5_bypass", PLL5_CTRL, 16, 1, pll5_bypass_sels, ARRAY_SIZE(pll5_bypass_sels), CLK_SET_RATE_PARENT);
|
||||
clk[VF610_PLL6_BYPASS] = imx_clk_mux_flags("pll6_bypass", PLL6_CTRL, 16, 1, pll6_bypass_sels, ARRAY_SIZE(pll6_bypass_sels), CLK_SET_RATE_PARENT);
|
||||
clk[VF610_PLL7_BYPASS] = imx_clk_mux_flags("pll7_bypass", PLL7_CTRL, 16, 1, pll7_bypass_sels, ARRAY_SIZE(pll7_bypass_sels), CLK_SET_RATE_PARENT);
|
||||
|
||||
clk[VF610_CLK_PLL4_MAIN] = imx_clk_fixed_factor("pll4_main", "fast_clk_sel", 25, 1);
|
||||
/* Enet pll: fixed 50Mhz */
|
||||
clk[VF610_CLK_PLL5_MAIN] = imx_clk_fixed_factor("pll5_main", "fast_clk_sel", 125, 6);
|
||||
/* pll6: default 960Mhz */
|
||||
clk[VF610_CLK_PLL6_MAIN] = imx_clk_fixed_factor("pll6_main", "fast_clk_sel", 40, 1);
|
||||
/* pll7: USB1 PLL at 480MHz */
|
||||
clk[VF610_CLK_PLL7_MAIN] = imx_clk_pllv3(IMX_PLLV3_USB, "pll7_main", "fast_clk_sel", PLL7_CTRL, 0x2);
|
||||
/* Do not bypass PLLs initially */
|
||||
clk_set_parent(clk[VF610_PLL1_BYPASS], clk[VF610_CLK_PLL1]);
|
||||
clk_set_parent(clk[VF610_PLL2_BYPASS], clk[VF610_CLK_PLL2]);
|
||||
clk_set_parent(clk[VF610_PLL3_BYPASS], clk[VF610_CLK_PLL3]);
|
||||
clk_set_parent(clk[VF610_PLL4_BYPASS], clk[VF610_CLK_PLL4]);
|
||||
clk_set_parent(clk[VF610_PLL5_BYPASS], clk[VF610_CLK_PLL5]);
|
||||
clk_set_parent(clk[VF610_PLL6_BYPASS], clk[VF610_CLK_PLL6]);
|
||||
clk_set_parent(clk[VF610_PLL7_BYPASS], clk[VF610_CLK_PLL7]);
|
||||
|
||||
clk[VF610_CLK_PLL1_SYS] = imx_clk_gate("pll1_sys", "pll1_bypass", PLL1_CTRL, 13);
|
||||
clk[VF610_CLK_PLL2_BUS] = imx_clk_gate("pll2_bus", "pll2_bypass", PLL2_CTRL, 13);
|
||||
clk[VF610_CLK_PLL3_USB_OTG] = imx_clk_gate("pll3_usb_otg", "pll3_bypass", PLL3_CTRL, 13);
|
||||
clk[VF610_CLK_PLL4_AUDIO] = imx_clk_gate("pll4_audio", "pll4_bypass", PLL4_CTRL, 13);
|
||||
clk[VF610_CLK_PLL5_ENET] = imx_clk_gate("pll5_enet", "pll5_bypass", PLL5_CTRL, 13);
|
||||
clk[VF610_CLK_PLL6_VIDEO] = imx_clk_gate("pll6_video", "pll6_bypass", PLL6_CTRL, 13);
|
||||
clk[VF610_CLK_PLL7_USB_HOST] = imx_clk_gate("pll7_usb_host", "pll7_bypass", PLL7_CTRL, 13);
|
||||
|
||||
clk[VF610_CLK_LVDS1_IN] = imx_clk_gate_exclusive("lvds1_in", "anaclk1", ANA_MISC1, 12, BIT(10));
|
||||
|
||||
clk[VF610_CLK_PLL1_PFD1] = imx_clk_pfd("pll1_pfd1", "pll1_sys", PFD_PLL1_BASE, 0);
|
||||
clk[VF610_CLK_PLL1_PFD2] = imx_clk_pfd("pll1_pfd2", "pll1_sys", PFD_PLL1_BASE, 1);
|
||||
clk[VF610_CLK_PLL1_PFD3] = imx_clk_pfd("pll1_pfd3", "pll1_sys", PFD_PLL1_BASE, 2);
|
||||
clk[VF610_CLK_PLL1_PFD4] = imx_clk_pfd("pll1_pfd4", "pll1_sys", PFD_PLL1_BASE, 3);
|
||||
|
||||
clk[VF610_CLK_PLL2_PFD1] = imx_clk_pfd("pll2_pfd1", "pll2_bus", PFD_PLL2_BASE, 0);
|
||||
clk[VF610_CLK_PLL2_PFD2] = imx_clk_pfd("pll2_pfd2", "pll2_bus", PFD_PLL2_BASE, 1);
|
||||
clk[VF610_CLK_PLL2_PFD3] = imx_clk_pfd("pll2_pfd3", "pll2_bus", PFD_PLL2_BASE, 2);
|
||||
clk[VF610_CLK_PLL2_PFD4] = imx_clk_pfd("pll2_pfd4", "pll2_bus", PFD_PLL2_BASE, 3);
|
||||
|
||||
clk[VF610_CLK_PLL3_PFD1] = imx_clk_pfd("pll3_pfd1", "pll3_usb_otg", PFD_PLL3_BASE, 0);
|
||||
clk[VF610_CLK_PLL3_PFD2] = imx_clk_pfd("pll3_pfd2", "pll3_usb_otg", PFD_PLL3_BASE, 1);
|
||||
clk[VF610_CLK_PLL3_PFD3] = imx_clk_pfd("pll3_pfd3", "pll3_usb_otg", PFD_PLL3_BASE, 2);
|
||||
clk[VF610_CLK_PLL3_PFD4] = imx_clk_pfd("pll3_pfd4", "pll3_usb_otg", PFD_PLL3_BASE, 3);
|
||||
|
||||
clk[VF610_CLK_PLL1_PFD_SEL] = imx_clk_mux("pll1_pfd_sel", CCM_CCSR, 16, 3, pll1_sels, 5);
|
||||
clk[VF610_CLK_PLL2_PFD_SEL] = imx_clk_mux("pll2_pfd_sel", CCM_CCSR, 19, 3, pll2_sels, 5);
|
||||
|
|
@ -167,12 +228,12 @@ static void __init vf610_clocks_init(struct device_node *ccm_node)
|
|||
clk[VF610_CLK_PLATFORM_BUS] = imx_clk_divider("platform_bus", "sys_bus", CCM_CACRR, 3, 3);
|
||||
clk[VF610_CLK_IPG_BUS] = imx_clk_divider("ipg_bus", "platform_bus", CCM_CACRR, 11, 2);
|
||||
|
||||
clk[VF610_CLK_PLL3_MAIN_DIV] = imx_clk_divider("pll3_main_div", "pll3_main", CCM_CACRR, 20, 1);
|
||||
clk[VF610_CLK_PLL4_MAIN_DIV] = clk_register_divider_table(NULL, "pll4_main_div", "pll4_main", 0, CCM_CACRR, 6, 3, 0, pll4_main_div_table, &imx_ccm_lock);
|
||||
clk[VF610_CLK_PLL6_MAIN_DIV] = imx_clk_divider("pll6_main_div", "pll6_main", CCM_CACRR, 21, 1);
|
||||
clk[VF610_CLK_PLL3_MAIN_DIV] = imx_clk_divider("pll3_usb_otg_div", "pll3_usb_otg", CCM_CACRR, 20, 1);
|
||||
clk[VF610_CLK_PLL4_MAIN_DIV] = clk_register_divider_table(NULL, "pll4_audio_div", "pll4_audio", 0, CCM_CACRR, 6, 3, 0, pll4_audio_div_table, &imx_ccm_lock);
|
||||
clk[VF610_CLK_PLL6_MAIN_DIV] = imx_clk_divider("pll6_video_div", "pll6_video", CCM_CACRR, 21, 1);
|
||||
|
||||
clk[VF610_CLK_USBPHY0] = imx_clk_gate("usbphy0", "pll3_main", PLL3_CTRL, 6);
|
||||
clk[VF610_CLK_USBPHY1] = imx_clk_gate("usbphy1", "pll7_main", PLL7_CTRL, 6);
|
||||
clk[VF610_CLK_USBPHY0] = imx_clk_gate("usbphy0", "pll3_usb_otg", PLL3_CTRL, 6);
|
||||
clk[VF610_CLK_USBPHY1] = imx_clk_gate("usbphy1", "pll7_usb_host", PLL7_CTRL, 6);
|
||||
|
||||
clk[VF610_CLK_USBC0] = imx_clk_gate2("usbc0", "ipg_bus", CCM_CCGR1, CCM_CCGRx_CGn(4));
|
||||
clk[VF610_CLK_USBC1] = imx_clk_gate2("usbc1", "ipg_bus", CCM_CCGR7, CCM_CCGRx_CGn(4));
|
||||
|
|
@ -191,8 +252,8 @@ static void __init vf610_clocks_init(struct device_node *ccm_node)
|
|||
clk[VF610_CLK_QSPI1_X1_DIV] = imx_clk_divider("qspi1_x1", "qspi1_x2", CCM_CSCDR3, 11, 1);
|
||||
clk[VF610_CLK_QSPI1] = imx_clk_gate2("qspi1", "qspi1_x1", CCM_CCGR8, CCM_CCGRx_CGn(4));
|
||||
|
||||
clk[VF610_CLK_ENET_50M] = imx_clk_fixed_factor("enet_50m", "pll5_main", 1, 10);
|
||||
clk[VF610_CLK_ENET_25M] = imx_clk_fixed_factor("enet_25m", "pll5_main", 1, 20);
|
||||
clk[VF610_CLK_ENET_50M] = imx_clk_fixed_factor("enet_50m", "pll5_enet", 1, 10);
|
||||
clk[VF610_CLK_ENET_25M] = imx_clk_fixed_factor("enet_25m", "pll5_enet", 1, 20);
|
||||
clk[VF610_CLK_ENET_SEL] = imx_clk_mux("enet_sel", CCM_CSCMR2, 4, 2, rmii_sels, 4);
|
||||
clk[VF610_CLK_ENET_TS_SEL] = imx_clk_mux("enet_ts_sel", CCM_CSCMR2, 0, 3, enet_ts_sels, 7);
|
||||
clk[VF610_CLK_ENET] = imx_clk_gate("enet", "enet_sel", CCM_CSCDR1, 24);
|
||||
|
|
|
|||
|
|
@ -131,4 +131,8 @@ static inline struct clk *imx_clk_fixed_factor(const char *name,
|
|||
CLK_SET_RATE_PARENT, mult, div);
|
||||
}
|
||||
|
||||
struct clk *imx_clk_cpu(const char *name, const char *parent_name,
|
||||
struct clk *div, struct clk *mux, struct clk *pll,
|
||||
struct clk *step);
|
||||
|
||||
#endif
|
||||
|
|
|
|||
|
|
@ -116,6 +116,7 @@ void imx_anatop_post_resume(void);
|
|||
int imx6q_set_lpm(enum mxc_cpu_pwr_mode mode);
|
||||
void imx6q_set_int_mem_clk_lpm(bool enable);
|
||||
void imx6sl_set_wait_clk(bool enter);
|
||||
int imx_mmdc_get_ddr_type(void);
|
||||
|
||||
void imx_cpu_die(unsigned int cpu);
|
||||
int imx_cpu_kill(unsigned int cpu);
|
||||
|
|
@ -157,5 +158,6 @@ static inline void imx_init_l2cache(void) {}
|
|||
#endif
|
||||
|
||||
extern struct smp_operations imx_smp_ops;
|
||||
extern struct smp_operations ls1021a_smp_ops;
|
||||
|
||||
#endif
|
||||
|
|
|
|||
|
|
@ -41,6 +41,8 @@ static void __init imx53_dt_init(void)
|
|||
static void __init imx53_init_late(void)
|
||||
{
|
||||
imx53_pm_init();
|
||||
|
||||
platform_device_register_simple("cpufreq-dt", -1, NULL, 0);
|
||||
}
|
||||
|
||||
static const char * const imx53_dt_board_compat[] __initconst = {
|
||||
|
|
|
|||
|
|
@ -8,12 +8,62 @@
|
|||
|
||||
#include <linux/irqchip.h>
|
||||
#include <linux/of_platform.h>
|
||||
#include <linux/phy.h>
|
||||
#include <linux/regmap.h>
|
||||
#include <linux/mfd/syscon.h>
|
||||
#include <linux/mfd/syscon/imx6q-iomuxc-gpr.h>
|
||||
#include <asm/mach/arch.h>
|
||||
#include <asm/mach/map.h>
|
||||
|
||||
#include "common.h"
|
||||
#include "cpuidle.h"
|
||||
|
||||
static int ar8031_phy_fixup(struct phy_device *dev)
|
||||
{
|
||||
u16 val;
|
||||
|
||||
/* Set RGMII IO voltage to 1.8V */
|
||||
phy_write(dev, 0x1d, 0x1f);
|
||||
phy_write(dev, 0x1e, 0x8);
|
||||
|
||||
/* introduce tx clock delay */
|
||||
phy_write(dev, 0x1d, 0x5);
|
||||
val = phy_read(dev, 0x1e);
|
||||
val |= 0x0100;
|
||||
phy_write(dev, 0x1e, val);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
#define PHY_ID_AR8031 0x004dd074
|
||||
static void __init imx6sx_enet_phy_init(void)
|
||||
{
|
||||
if (IS_BUILTIN(CONFIG_PHYLIB))
|
||||
phy_register_fixup_for_uid(PHY_ID_AR8031, 0xffffffff,
|
||||
ar8031_phy_fixup);
|
||||
}
|
||||
|
||||
static void __init imx6sx_enet_clk_sel(void)
|
||||
{
|
||||
struct regmap *gpr;
|
||||
|
||||
gpr = syscon_regmap_lookup_by_compatible("fsl,imx6sx-iomuxc-gpr");
|
||||
if (!IS_ERR(gpr)) {
|
||||
regmap_update_bits(gpr, IOMUXC_GPR1,
|
||||
IMX6SX_GPR1_FEC_CLOCK_MUX_SEL_MASK, 0);
|
||||
regmap_update_bits(gpr, IOMUXC_GPR1,
|
||||
IMX6SX_GPR1_FEC_CLOCK_PAD_DIR_MASK, 0);
|
||||
} else {
|
||||
pr_err("failed to find fsl,imx6sx-iomux-gpr regmap\n");
|
||||
}
|
||||
}
|
||||
|
||||
static inline void imx6sx_enet_init(void)
|
||||
{
|
||||
imx6sx_enet_phy_init();
|
||||
imx6sx_enet_clk_sel();
|
||||
}
|
||||
|
||||
static void __init imx6sx_init_machine(void)
|
||||
{
|
||||
struct device *parent;
|
||||
|
|
@ -26,6 +76,7 @@ static void __init imx6sx_init_machine(void)
|
|||
|
||||
of_platform_populate(NULL, of_default_bus_match_table, NULL, parent);
|
||||
|
||||
imx6sx_enet_init();
|
||||
imx_anatop_init();
|
||||
imx6sx_pm_init();
|
||||
}
|
||||
|
|
|
|||
|
|
@ -0,0 +1,22 @@
|
|||
/*
|
||||
* Copyright 2013-2014 Freescale Semiconductor, Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*/
|
||||
|
||||
#include <asm/mach/arch.h>
|
||||
|
||||
#include "common.h"
|
||||
|
||||
static const char * const ls1021a_dt_compat[] __initconst = {
|
||||
"fsl,ls1021a",
|
||||
NULL,
|
||||
};
|
||||
|
||||
DT_MACHINE_START(LS1021A, "Freescale LS1021A")
|
||||
.smp = smp_ops(ls1021a_smp_ops),
|
||||
.dt_compat = ls1021a_dt_compat,
|
||||
MACHINE_END
|
||||
|
|
@ -21,6 +21,12 @@
|
|||
#define BP_MMDC_MAPSR_PSD 0
|
||||
#define BP_MMDC_MAPSR_PSS 4
|
||||
|
||||
#define MMDC_MDMISC 0x18
|
||||
#define BM_MMDC_MDMISC_DDR_TYPE 0x18
|
||||
#define BP_MMDC_MDMISC_DDR_TYPE 0x3
|
||||
|
||||
static int ddr_type;
|
||||
|
||||
static int imx_mmdc_probe(struct platform_device *pdev)
|
||||
{
|
||||
struct device_node *np = pdev->dev.of_node;
|
||||
|
|
@ -31,6 +37,12 @@ static int imx_mmdc_probe(struct platform_device *pdev)
|
|||
mmdc_base = of_iomap(np, 0);
|
||||
WARN_ON(!mmdc_base);
|
||||
|
||||
reg = mmdc_base + MMDC_MDMISC;
|
||||
/* Get ddr type */
|
||||
val = readl_relaxed(reg);
|
||||
ddr_type = (val & BM_MMDC_MDMISC_DDR_TYPE) >>
|
||||
BP_MMDC_MDMISC_DDR_TYPE;
|
||||
|
||||
reg = mmdc_base + MMDC_MAPSR;
|
||||
|
||||
/* Enable automatic power saving */
|
||||
|
|
@ -51,6 +63,11 @@ static int imx_mmdc_probe(struct platform_device *pdev)
|
|||
return 0;
|
||||
}
|
||||
|
||||
int imx_mmdc_get_ddr_type(void)
|
||||
{
|
||||
return ddr_type;
|
||||
}
|
||||
|
||||
static struct of_device_id imx_mmdc_dt_ids[] = {
|
||||
{ .compatible = "fsl,imx6q-mmdc", },
|
||||
{ /* sentinel */ }
|
||||
|
|
|
|||
|
|
@ -55,6 +55,8 @@
|
|||
#define IMX_CHIP_REVISION_3_3 0x33
|
||||
#define IMX_CHIP_REVISION_UNKNOWN 0xff
|
||||
|
||||
#define IMX_DDR_TYPE_LPDDR2 1
|
||||
|
||||
#ifndef __ASSEMBLY__
|
||||
extern unsigned int __mxc_cpu_type;
|
||||
#endif
|
||||
|
|
|
|||
|
|
@ -11,7 +11,10 @@
|
|||
*/
|
||||
|
||||
#include <linux/init.h>
|
||||
#include <linux/of_address.h>
|
||||
#include <linux/of.h>
|
||||
#include <linux/smp.h>
|
||||
|
||||
#include <asm/cacheflush.h>
|
||||
#include <asm/page.h>
|
||||
#include <asm/smp_scu.h>
|
||||
|
|
@ -94,3 +97,33 @@ struct smp_operations imx_smp_ops __initdata = {
|
|||
.cpu_kill = imx_cpu_kill,
|
||||
#endif
|
||||
};
|
||||
|
||||
#define DCFG_CCSR_SCRATCHRW1 0x200
|
||||
|
||||
static int ls1021a_boot_secondary(unsigned int cpu, struct task_struct *idle)
|
||||
{
|
||||
arch_send_wakeup_ipi_mask(cpumask_of(cpu));
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void __init ls1021a_smp_prepare_cpus(unsigned int max_cpus)
|
||||
{
|
||||
struct device_node *np;
|
||||
void __iomem *dcfg_base;
|
||||
unsigned long paddr;
|
||||
|
||||
np = of_find_compatible_node(NULL, NULL, "fsl,ls1021a-dcfg");
|
||||
dcfg_base = of_iomap(np, 0);
|
||||
BUG_ON(!dcfg_base);
|
||||
|
||||
paddr = virt_to_phys(secondary_startup);
|
||||
writel_relaxed(cpu_to_be32(paddr), dcfg_base + DCFG_CCSR_SCRATCHRW1);
|
||||
|
||||
iounmap(dcfg_base);
|
||||
}
|
||||
|
||||
struct smp_operations ls1021a_smp_ops __initdata = {
|
||||
.smp_prepare_cpus = ls1021a_smp_prepare_cpus,
|
||||
.smp_boot_secondary = ls1021a_boot_secondary,
|
||||
};
|
||||
|
|
|
|||
|
|
@ -88,7 +88,7 @@ struct imx6_pm_base {
|
|||
};
|
||||
|
||||
struct imx6_pm_socdata {
|
||||
u32 cpu_type;
|
||||
u32 ddr_type;
|
||||
const char *mmdc_compat;
|
||||
const char *src_compat;
|
||||
const char *iomuxc_compat;
|
||||
|
|
@ -138,7 +138,6 @@ static const u32 imx6sx_mmdc_io_offset[] __initconst = {
|
|||
};
|
||||
|
||||
static const struct imx6_pm_socdata imx6q_pm_data __initconst = {
|
||||
.cpu_type = MXC_CPU_IMX6Q,
|
||||
.mmdc_compat = "fsl,imx6q-mmdc",
|
||||
.src_compat = "fsl,imx6q-src",
|
||||
.iomuxc_compat = "fsl,imx6q-iomuxc",
|
||||
|
|
@ -148,7 +147,6 @@ static const struct imx6_pm_socdata imx6q_pm_data __initconst = {
|
|||
};
|
||||
|
||||
static const struct imx6_pm_socdata imx6dl_pm_data __initconst = {
|
||||
.cpu_type = MXC_CPU_IMX6DL,
|
||||
.mmdc_compat = "fsl,imx6q-mmdc",
|
||||
.src_compat = "fsl,imx6q-src",
|
||||
.iomuxc_compat = "fsl,imx6dl-iomuxc",
|
||||
|
|
@ -158,7 +156,6 @@ static const struct imx6_pm_socdata imx6dl_pm_data __initconst = {
|
|||
};
|
||||
|
||||
static const struct imx6_pm_socdata imx6sl_pm_data __initconst = {
|
||||
.cpu_type = MXC_CPU_IMX6SL,
|
||||
.mmdc_compat = "fsl,imx6sl-mmdc",
|
||||
.src_compat = "fsl,imx6sl-src",
|
||||
.iomuxc_compat = "fsl,imx6sl-iomuxc",
|
||||
|
|
@ -168,7 +165,6 @@ static const struct imx6_pm_socdata imx6sl_pm_data __initconst = {
|
|||
};
|
||||
|
||||
static const struct imx6_pm_socdata imx6sx_pm_data __initconst = {
|
||||
.cpu_type = MXC_CPU_IMX6SX,
|
||||
.mmdc_compat = "fsl,imx6sx-mmdc",
|
||||
.src_compat = "fsl,imx6sx-src",
|
||||
.iomuxc_compat = "fsl,imx6sx-iomuxc",
|
||||
|
|
@ -187,7 +183,7 @@ static const struct imx6_pm_socdata imx6sx_pm_data __initconst = {
|
|||
struct imx6_cpu_pm_info {
|
||||
phys_addr_t pbase; /* The physical address of pm_info. */
|
||||
phys_addr_t resume_addr; /* The physical resume address for asm code */
|
||||
u32 cpu_type;
|
||||
u32 ddr_type;
|
||||
u32 pm_info_size; /* Size of pm_info. */
|
||||
struct imx6_pm_base mmdc_base;
|
||||
struct imx6_pm_base src_base;
|
||||
|
|
@ -522,7 +518,7 @@ static int __init imx6q_suspend_init(const struct imx6_pm_socdata *socdata)
|
|||
goto pl310_cache_map_failed;
|
||||
}
|
||||
|
||||
pm_info->cpu_type = socdata->cpu_type;
|
||||
pm_info->ddr_type = imx_mmdc_get_ddr_type();
|
||||
pm_info->mmdc_io_num = socdata->mmdc_io_num;
|
||||
mmdc_offset_array = socdata->mmdc_io_offset;
|
||||
|
||||
|
|
|
|||
|
|
@ -45,7 +45,7 @@
|
|||
*/
|
||||
#define PM_INFO_PBASE_OFFSET 0x0
|
||||
#define PM_INFO_RESUME_ADDR_OFFSET 0x4
|
||||
#define PM_INFO_CPU_TYPE_OFFSET 0x8
|
||||
#define PM_INFO_DDR_TYPE_OFFSET 0x8
|
||||
#define PM_INFO_PM_INFO_SIZE_OFFSET 0xC
|
||||
#define PM_INFO_MX6Q_MMDC_P_OFFSET 0x10
|
||||
#define PM_INFO_MX6Q_MMDC_V_OFFSET 0x14
|
||||
|
|
@ -110,7 +110,7 @@
|
|||
ldreq r11, [r0, #PM_INFO_MX6Q_MMDC_V_OFFSET]
|
||||
ldrne r11, [r0, #PM_INFO_MX6Q_MMDC_P_OFFSET]
|
||||
|
||||
cmp r3, #MXC_CPU_IMX6SL
|
||||
cmp r3, #IMX_DDR_TYPE_LPDDR2
|
||||
bne 4f
|
||||
|
||||
/* reset read FIFO, RST_RD_FIFO */
|
||||
|
|
@ -151,7 +151,7 @@
|
|||
ENTRY(imx6_suspend)
|
||||
ldr r1, [r0, #PM_INFO_PBASE_OFFSET]
|
||||
ldr r2, [r0, #PM_INFO_RESUME_ADDR_OFFSET]
|
||||
ldr r3, [r0, #PM_INFO_CPU_TYPE_OFFSET]
|
||||
ldr r3, [r0, #PM_INFO_DDR_TYPE_OFFSET]
|
||||
ldr r4, [r0, #PM_INFO_PM_INFO_SIZE_OFFSET]
|
||||
|
||||
/*
|
||||
|
|
@ -209,8 +209,8 @@ poll_dvfs_set:
|
|||
ldr r7, [r0, #PM_INFO_MMDC_IO_NUM_OFFSET]
|
||||
ldr r8, =PM_INFO_MMDC_IO_VAL_OFFSET
|
||||
add r8, r8, r0
|
||||
/* i.MX6SL's last 3 IOs need special setting */
|
||||
cmp r3, #MXC_CPU_IMX6SL
|
||||
/* LPDDR2's last 3 IOs need special setting */
|
||||
cmp r3, #IMX_DDR_TYPE_LPDDR2
|
||||
subeq r7, r7, #0x3
|
||||
set_mmdc_io_lpm:
|
||||
ldr r9, [r8], #0x8
|
||||
|
|
@ -218,7 +218,7 @@ set_mmdc_io_lpm:
|
|||
subs r7, r7, #0x1
|
||||
bne set_mmdc_io_lpm
|
||||
|
||||
cmp r3, #MXC_CPU_IMX6SL
|
||||
cmp r3, #IMX_DDR_TYPE_LPDDR2
|
||||
bne set_mmdc_io_lpm_done
|
||||
ldr r6, =0x1000
|
||||
ldr r9, [r8], #0x8
|
||||
|
|
@ -324,7 +324,7 @@ resume:
|
|||
str r7, [r11, #MX6Q_SRC_GPR1]
|
||||
str r7, [r11, #MX6Q_SRC_GPR2]
|
||||
|
||||
ldr r3, [r0, #PM_INFO_CPU_TYPE_OFFSET]
|
||||
ldr r3, [r0, #PM_INFO_DDR_TYPE_OFFSET]
|
||||
mov r5, #0x1
|
||||
resume_mmdc
|
||||
|
||||
|
|
|
|||
|
|
@ -71,6 +71,15 @@ config POWER_RESET_HISI
|
|||
help
|
||||
Reboot support for Hisilicon boards.
|
||||
|
||||
config POWER_RESET_IMX
|
||||
bool "IMX6 power-off driver"
|
||||
depends on POWER_RESET && SOC_IMX6
|
||||
help
|
||||
This driver support power off external PMIC by PMIC_ON_REQ on i.mx6
|
||||
boards.If you want to use other pin to control external power,please
|
||||
say N here or disable in dts to make sure pm_power_off never be
|
||||
overwrote wrongly by this driver.
|
||||
|
||||
config POWER_RESET_MSM
|
||||
bool "Qualcomm MSM power-off driver"
|
||||
depends on ARCH_QCOM
|
||||
|
|
|
|||
|
|
@ -6,6 +6,7 @@ obj-$(CONFIG_POWER_RESET_BRCMSTB) += brcmstb-reboot.o
|
|||
obj-$(CONFIG_POWER_RESET_GPIO) += gpio-poweroff.o
|
||||
obj-$(CONFIG_POWER_RESET_GPIO_RESTART) += gpio-restart.o
|
||||
obj-$(CONFIG_POWER_RESET_HISI) += hisi-reboot.o
|
||||
obj-$(CONFIG_POWER_RESET_IMX) += imx-snvs-poweroff.o
|
||||
obj-$(CONFIG_POWER_RESET_MSM) += msm-poweroff.o
|
||||
obj-$(CONFIG_POWER_RESET_LTC2952) += ltc2952-poweroff.o
|
||||
obj-$(CONFIG_POWER_RESET_QNAP) += qnap-poweroff.o
|
||||
|
|
|
|||
|
|
@ -0,0 +1,66 @@
|
|||
/* Power off driver for i.mx6
|
||||
* Copyright (c) 2014, FREESCALE CORPORATION. All rights reserved.
|
||||
*
|
||||
* based on msm-poweroff.c
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 and
|
||||
* only version 2 as published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
*/
|
||||
|
||||
#include <linux/err.h>
|
||||
#include <linux/init.h>
|
||||
#include <linux/io.h>
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/module.h>
|
||||
#include <linux/of.h>
|
||||
#include <linux/of_address.h>
|
||||
#include <linux/platform_device.h>
|
||||
|
||||
static void __iomem *snvs_base;
|
||||
|
||||
static void do_imx_poweroff(void)
|
||||
{
|
||||
u32 value = readl(snvs_base);
|
||||
|
||||
/* set TOP and DP_EN bit */
|
||||
writel(value | 0x60, snvs_base);
|
||||
}
|
||||
|
||||
static int imx_poweroff_probe(struct platform_device *pdev)
|
||||
{
|
||||
snvs_base = of_iomap(pdev->dev.of_node, 0);
|
||||
if (!snvs_base) {
|
||||
dev_err(&pdev->dev, "failed to get memory\n");
|
||||
return -ENODEV;
|
||||
}
|
||||
|
||||
pm_power_off = do_imx_poweroff;
|
||||
return 0;
|
||||
}
|
||||
|
||||
static const struct of_device_id of_imx_poweroff_match[] = {
|
||||
{ .compatible = "fsl,sec-v4.0-poweroff", },
|
||||
{},
|
||||
};
|
||||
MODULE_DEVICE_TABLE(of, of_imx_poweroff_match);
|
||||
|
||||
static struct platform_driver imx_poweroff_driver = {
|
||||
.probe = imx_poweroff_probe,
|
||||
.driver = {
|
||||
.name = "imx-snvs-poweroff",
|
||||
.of_match_table = of_match_ptr(of_imx_poweroff_match),
|
||||
},
|
||||
};
|
||||
|
||||
static int __init imx_poweroff_init(void)
|
||||
{
|
||||
return platform_driver_register(&imx_poweroff_driver);
|
||||
}
|
||||
device_initcall(imx_poweroff_init);
|
||||
|
|
@ -198,6 +198,9 @@
|
|||
#define IMX5_CLK_OCRAM 186
|
||||
#define IMX5_CLK_SAHARA_IPG_GATE 187
|
||||
#define IMX5_CLK_SATA_REF 188
|
||||
#define IMX5_CLK_END 189
|
||||
#define IMX5_CLK_STEP_SEL 189
|
||||
#define IMX5_CLK_CPU_PODF_SEL 190
|
||||
#define IMX5_CLK_ARM 191
|
||||
#define IMX5_CLK_END 192
|
||||
|
||||
#endif /* __DT_BINDINGS_CLOCK_IMX5_H */
|
||||
|
|
|
|||
|
|
@ -21,24 +21,24 @@
|
|||
#define VF610_CLK_FASK_CLK_SEL 8
|
||||
#define VF610_CLK_AUDIO_EXT 9
|
||||
#define VF610_CLK_ENET_EXT 10
|
||||
#define VF610_CLK_PLL1_MAIN 11
|
||||
#define VF610_CLK_PLL1_SYS 11
|
||||
#define VF610_CLK_PLL1_PFD1 12
|
||||
#define VF610_CLK_PLL1_PFD2 13
|
||||
#define VF610_CLK_PLL1_PFD3 14
|
||||
#define VF610_CLK_PLL1_PFD4 15
|
||||
#define VF610_CLK_PLL2_MAIN 16
|
||||
#define VF610_CLK_PLL2_BUS 16
|
||||
#define VF610_CLK_PLL2_PFD1 17
|
||||
#define VF610_CLK_PLL2_PFD2 18
|
||||
#define VF610_CLK_PLL2_PFD3 19
|
||||
#define VF610_CLK_PLL2_PFD4 20
|
||||
#define VF610_CLK_PLL3_MAIN 21
|
||||
#define VF610_CLK_PLL3_USB_OTG 21
|
||||
#define VF610_CLK_PLL3_PFD1 22
|
||||
#define VF610_CLK_PLL3_PFD2 23
|
||||
#define VF610_CLK_PLL3_PFD3 24
|
||||
#define VF610_CLK_PLL3_PFD4 25
|
||||
#define VF610_CLK_PLL4_MAIN 26
|
||||
#define VF610_CLK_PLL5_MAIN 27
|
||||
#define VF610_CLK_PLL6_MAIN 28
|
||||
#define VF610_CLK_PLL4_AUDIO 26
|
||||
#define VF610_CLK_PLL5_ENET 27
|
||||
#define VF610_CLK_PLL6_VIDEO 28
|
||||
#define VF610_CLK_PLL3_MAIN_DIV 29
|
||||
#define VF610_CLK_PLL4_MAIN_DIV 30
|
||||
#define VF610_CLK_PLL6_MAIN_DIV 31
|
||||
|
|
@ -166,9 +166,32 @@
|
|||
#define VF610_CLK_DMAMUX3 153
|
||||
#define VF610_CLK_FLEXCAN0_EN 154
|
||||
#define VF610_CLK_FLEXCAN1_EN 155
|
||||
#define VF610_CLK_PLL7_MAIN 156
|
||||
#define VF610_CLK_PLL7_USB_HOST 156
|
||||
#define VF610_CLK_USBPHY0 157
|
||||
#define VF610_CLK_USBPHY1 158
|
||||
#define VF610_CLK_END 159
|
||||
#define VF610_CLK_LVDS1_IN 159
|
||||
#define VF610_CLK_ANACLK1 160
|
||||
#define VF610_CLK_PLL1_BYPASS_SRC 161
|
||||
#define VF610_CLK_PLL2_BYPASS_SRC 162
|
||||
#define VF610_CLK_PLL3_BYPASS_SRC 163
|
||||
#define VF610_CLK_PLL4_BYPASS_SRC 164
|
||||
#define VF610_CLK_PLL5_BYPASS_SRC 165
|
||||
#define VF610_CLK_PLL6_BYPASS_SRC 166
|
||||
#define VF610_CLK_PLL7_BYPASS_SRC 167
|
||||
#define VF610_CLK_PLL1 168
|
||||
#define VF610_CLK_PLL2 169
|
||||
#define VF610_CLK_PLL3 170
|
||||
#define VF610_CLK_PLL4 171
|
||||
#define VF610_CLK_PLL5 172
|
||||
#define VF610_CLK_PLL6 173
|
||||
#define VF610_CLK_PLL7 174
|
||||
#define VF610_PLL1_BYPASS 175
|
||||
#define VF610_PLL2_BYPASS 176
|
||||
#define VF610_PLL3_BYPASS 177
|
||||
#define VF610_PLL4_BYPASS 178
|
||||
#define VF610_PLL5_BYPASS 179
|
||||
#define VF610_PLL6_BYPASS 180
|
||||
#define VF610_PLL7_BYPASS 181
|
||||
#define VF610_CLK_END 182
|
||||
|
||||
#endif /* __DT_BINDINGS_CLOCK_VF610_H */
|
||||
|
|
|
|||
|
|
@ -395,4 +395,43 @@
|
|||
#define IMX6SL_GPR1_FEC_CLOCK_MUX1_SEL_MASK (0x3 << 17)
|
||||
#define IMX6SL_GPR1_FEC_CLOCK_MUX2_SEL_MASK (0x1 << 14)
|
||||
|
||||
/* For imx6sx iomux gpr register field define */
|
||||
#define IMX6SX_GPR1_VDEC_SW_RST_MASK (0x1 << 20)
|
||||
#define IMX6SX_GPR1_VDEC_SW_RST_RESET (0x1 << 20)
|
||||
#define IMX6SX_GPR1_VDEC_SW_RST_RELEASE (0x0 << 20)
|
||||
#define IMX6SX_GPR1_VADC_SW_RST_MASK (0x1 << 19)
|
||||
#define IMX6SX_GPR1_VADC_SW_RST_RESET (0x1 << 19)
|
||||
#define IMX6SX_GPR1_VADC_SW_RST_RELEASE (0x0 << 19)
|
||||
#define IMX6SX_GPR1_FEC_CLOCK_MUX_SEL_MASK (0x3 << 13)
|
||||
#define IMX6SX_GPR1_FEC_CLOCK_PAD_DIR_MASK (0x3 << 17)
|
||||
#define IMX6SX_GPR1_FEC_CLOCK_MUX_SEL_EXT (0x3 << 13)
|
||||
|
||||
#define IMX6SX_GPR4_FEC_ENET1_STOP_REQ (0x1 << 3)
|
||||
#define IMX6SX_GPR4_FEC_ENET2_STOP_REQ (0x1 << 4)
|
||||
|
||||
#define IMX6SX_GPR5_DISP_MUX_LDB_CTRL_MASK (0x1 << 3)
|
||||
#define IMX6SX_GPR5_DISP_MUX_LDB_CTRL_LCDIF1 (0x0 << 3)
|
||||
#define IMX6SX_GPR5_DISP_MUX_LDB_CTRL_LCDIF2 (0x1 << 3)
|
||||
|
||||
#define IMX6SX_GPR5_CSI2_MUX_CTRL_MASK (0x3 << 27)
|
||||
#define IMX6SX_GPR5_CSI2_MUX_CTRL_EXT_PIN (0x0 << 27)
|
||||
#define IMX6SX_GPR5_CSI2_MUX_CTRL_CVD (0x1 << 27)
|
||||
#define IMX6SX_GPR5_CSI2_MUX_CTRL_VDAC_TO_CSI (0x2 << 27)
|
||||
#define IMX6SX_GPR5_CSI2_MUX_CTRL_GND (0x3 << 27)
|
||||
#define IMX6SX_GPR5_VADC_TO_CSI_CAPTURE_EN_MASK (0x1 << 26)
|
||||
#define IMX6SX_GPR5_VADC_TO_CSI_CAPTURE_EN_ENABLE (0x1 << 26)
|
||||
#define IMX6SX_GPR5_VADC_TO_CSI_CAPTURE_EN_DISABLE (0x0 << 26)
|
||||
#define IMX6SX_GPR5_CSI1_MUX_CTRL_MASK (0x3 << 4)
|
||||
#define IMX6SX_GPR5_CSI1_MUX_CTRL_EXT_PIN (0x0 << 4)
|
||||
#define IMX6SX_GPR5_CSI1_MUX_CTRL_CVD (0x1 << 4)
|
||||
#define IMX6SX_GPR5_CSI1_MUX_CTRL_VDAC_TO_CSI (0x2 << 4)
|
||||
#define IMX6SX_GPR5_CSI1_MUX_CTRL_GND (0x3 << 4)
|
||||
|
||||
#define IMX6SX_GPR5_DISP_MUX_DCIC2_LCDIF2 (0x0 << 2)
|
||||
#define IMX6SX_GPR5_DISP_MUX_DCIC2_LVDS (0x1 << 2)
|
||||
#define IMX6SX_GPR5_DISP_MUX_DCIC2_MASK (0x1 << 2)
|
||||
#define IMX6SX_GPR5_DISP_MUX_DCIC1_LCDIF1 (0x0 << 1)
|
||||
#define IMX6SX_GPR5_DISP_MUX_DCIC1_LVDS (0x1 << 1)
|
||||
#define IMX6SX_GPR5_DISP_MUX_DCIC1_MASK (0x1 << 1)
|
||||
|
||||
#endif /* __LINUX_IMX6Q_IOMUXC_GPR_H */
|
||||
|
|
|
|||
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