mlx5-next-2020-12-02
Low level mlx5 updates required by both netdev and rdma trees: net/mlx5: Treat host PF vport as other (non eswitch manager) vport net/mlx5: Enable host PF HCA after eswitch is initialized net/mlx5: Rename peer_pf to host_pf net/mlx5: Make API mlx5_core_is_ecpf accept const pointer net/mlx5: Export steering related functions net/mlx5: Expose other function ifc bits net/mlx5: Expose IP-in-IP TX and RX capability bits net/mlx5: Update the hardware interface definition for vhca state net/mlx5: Update the list of the PCI supported devices net/mlx5: Avoid exposing driver internal command helpers net/mlx5: Add ts_cqe_to_dest_cqn related bits net/mlx5: Add misc4 to mlx5_ifc_fte_match_param_bits net/mlx5: Check dr mask size against mlx5_match_param size net/mlx5: Add sampler destination type net/mlx5: Add sample offload hardware bits and structures Signed-off-by: Saeed Mahameed <saeedm@nvidia.com> -----BEGIN PGP SIGNATURE----- iQEzBAABCAAdFiEEGhZs6bAKwk/OTgTpSD+KveBX+j4FAl/IOZcACgkQSD+KveBX +j4J8wgAuxwflrYrbCWXV7LE08J7T7ZHRDE+jEbaZ0Zp9mOsYDDpcifpKwy2EVRf RKcpMYh/GzAljmEpeWIAlMxmlpXhKWXTDruWCx73r1jvdXf/RU24/zQHa6BjeiDo rMB8bgiW4a66+z4LcN/U6ahbVM5gScBNEt2sS1OIi9ZInngGVo9FgfhYMpERPNcH 3+mcHulCnGBNbbLwoTllOcgbxexn+xoByukg5Z0ddBJp007DMjzBIWDpDS0y2HaT jGo1LYONgRc3zoGVmdeu9F+tSsWBIgsaiyGxKj1T/8sZUaNz2TKj9VOiYIj9BLff cp6GRc88k7HWA4tImSHQiLbK6cx+yA== =mjvI -----END PGP SIGNATURE----- Merge tag 'mlx5-next-2020-12-02' of git://git.kernel.org/pub/scm/linux/kernel/git/mellanox/linux Saeed Mahameed says: ==================== mlx5-next-2020-12-02 Low level mlx5 updates required by both netdev and rdma trees. * tag 'mlx5-next-2020-12-02' of git://git.kernel.org/pub/scm/linux/kernel/git/mellanox/linux: net/mlx5: Treat host PF vport as other (non eswitch manager) vport net/mlx5: Enable host PF HCA after eswitch is initialized net/mlx5: Rename peer_pf to host_pf net/mlx5: Make API mlx5_core_is_ecpf accept const pointer net/mlx5: Export steering related functions net/mlx5: Expose other function ifc bits net/mlx5: Expose IP-in-IP TX and RX capability bits net/mlx5: Update the hardware interface definition for vhca state net/mlx5: Update the list of the PCI supported devices net/mlx5: Avoid exposing driver internal command helpers net/mlx5: Add ts_cqe_to_dest_cqn related bits net/mlx5: Add misc4 to mlx5_ifc_fte_match_param_bits net/mlx5: Check dr mask size against mlx5_match_param size net/mlx5: Add sampler destination type net/mlx5: Add sample offload hardware bits and structures ==================== Link: https://lore.kernel.org/r/20201203011010.213440-1-saeedm@nvidia.com Signed-off-by: Jakub Kicinski <kuba@kernel.org>
This commit is contained in:
Jakub Kicinski
Коммит
32e417024f
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@ -2142,7 +2142,6 @@ dma_pool_err:
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kvfree(cmd->stats);
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return err;
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}
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EXPORT_SYMBOL(mlx5_cmd_init);
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void mlx5_cmd_cleanup(struct mlx5_core_dev *dev)
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{
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@ -2155,11 +2154,9 @@ void mlx5_cmd_cleanup(struct mlx5_core_dev *dev)
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dma_pool_destroy(cmd->pool);
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kvfree(cmd->stats);
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}
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EXPORT_SYMBOL(mlx5_cmd_cleanup);
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void mlx5_cmd_set_state(struct mlx5_core_dev *dev,
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enum mlx5_cmdif_state cmdif_state)
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{
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dev->cmd.state = cmdif_state;
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}
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EXPORT_SYMBOL(mlx5_cmd_set_state);
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@ -247,6 +247,9 @@ const char *parse_fs_dst(struct trace_seq *p,
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case MLX5_FLOW_DESTINATION_TYPE_TIR:
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trace_seq_printf(p, "tir=%u\n", dst->tir_num);
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break;
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case MLX5_FLOW_DESTINATION_TYPE_FLOW_SAMPLER:
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trace_seq_printf(p, "sampler_id=%u\n", dst->sampler_id);
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break;
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case MLX5_FLOW_DESTINATION_TYPE_COUNTER:
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trace_seq_printf(p, "counter_id=%u\n", counter_id);
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break;
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@ -8,37 +8,66 @@ bool mlx5_read_embedded_cpu(struct mlx5_core_dev *dev)
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return (ioread32be(&dev->iseg->initializing) >> MLX5_ECPU_BIT_NUM) & 1;
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}
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static int mlx5_peer_pf_init(struct mlx5_core_dev *dev)
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static bool mlx5_ecpf_esw_admins_host_pf(const struct mlx5_core_dev *dev)
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{
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u32 in[MLX5_ST_SZ_DW(enable_hca_in)] = {};
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int err;
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/* In separate host mode, PF enables itself.
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* When ECPF is eswitch manager, eswitch enables host PF after
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* eswitch is setup.
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*/
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return mlx5_core_is_ecpf_esw_manager(dev);
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}
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int mlx5_cmd_host_pf_enable_hca(struct mlx5_core_dev *dev)
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{
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u32 out[MLX5_ST_SZ_DW(enable_hca_out)] = {};
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u32 in[MLX5_ST_SZ_DW(enable_hca_in)] = {};
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MLX5_SET(enable_hca_in, in, opcode, MLX5_CMD_OP_ENABLE_HCA);
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err = mlx5_cmd_exec_in(dev, enable_hca, in);
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MLX5_SET(enable_hca_in, in, function_id, 0);
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MLX5_SET(enable_hca_in, in, embedded_cpu_function, 0);
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return mlx5_cmd_exec(dev, &in, sizeof(in), &out, sizeof(out));
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}
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int mlx5_cmd_host_pf_disable_hca(struct mlx5_core_dev *dev)
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{
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u32 out[MLX5_ST_SZ_DW(disable_hca_out)] = {};
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u32 in[MLX5_ST_SZ_DW(disable_hca_in)] = {};
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MLX5_SET(disable_hca_in, in, opcode, MLX5_CMD_OP_DISABLE_HCA);
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MLX5_SET(disable_hca_in, in, function_id, 0);
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MLX5_SET(disable_hca_in, in, embedded_cpu_function, 0);
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return mlx5_cmd_exec(dev, in, sizeof(in), out, sizeof(out));
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}
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static int mlx5_host_pf_init(struct mlx5_core_dev *dev)
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{
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int err;
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if (mlx5_ecpf_esw_admins_host_pf(dev))
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return 0;
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/* ECPF shall enable HCA for host PF in the same way a PF
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* does this for its VFs when ECPF is not a eswitch manager.
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*/
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err = mlx5_cmd_host_pf_enable_hca(dev);
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if (err)
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mlx5_core_err(dev, "Failed to enable peer PF HCA err(%d)\n",
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err);
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mlx5_core_err(dev, "Failed to enable external host PF HCA err(%d)\n", err);
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return err;
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}
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static void mlx5_peer_pf_cleanup(struct mlx5_core_dev *dev)
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static void mlx5_host_pf_cleanup(struct mlx5_core_dev *dev)
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{
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u32 in[MLX5_ST_SZ_DW(disable_hca_in)] = {};
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int err;
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MLX5_SET(disable_hca_in, in, opcode, MLX5_CMD_OP_DISABLE_HCA);
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err = mlx5_cmd_exec_in(dev, disable_hca, in);
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if (mlx5_ecpf_esw_admins_host_pf(dev))
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return;
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err = mlx5_cmd_host_pf_disable_hca(dev);
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if (err) {
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mlx5_core_err(dev, "Failed to disable peer PF HCA err(%d)\n",
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err);
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mlx5_core_err(dev, "Failed to disable external host PF HCA err(%d)\n", err);
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return;
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}
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err = mlx5_wait_for_pages(dev, &dev->priv.peer_pf_pages);
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if (err)
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mlx5_core_warn(dev, "Timeout reclaiming peer PF pages err(%d)\n",
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err);
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}
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int mlx5_ec_init(struct mlx5_core_dev *dev)
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@ -46,16 +75,19 @@ int mlx5_ec_init(struct mlx5_core_dev *dev)
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if (!mlx5_core_is_ecpf(dev))
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return 0;
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/* ECPF shall enable HCA for peer PF in the same way a PF
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* does this for its VFs.
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*/
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return mlx5_peer_pf_init(dev);
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return mlx5_host_pf_init(dev);
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}
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void mlx5_ec_cleanup(struct mlx5_core_dev *dev)
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{
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int err;
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if (!mlx5_core_is_ecpf(dev))
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return;
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mlx5_peer_pf_cleanup(dev);
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mlx5_host_pf_cleanup(dev);
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err = mlx5_wait_for_pages(dev, &dev->priv.host_pf_pages);
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if (err)
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mlx5_core_warn(dev, "Timeout reclaiming external host PF pages err(%d)\n", err);
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}
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@ -17,6 +17,9 @@ bool mlx5_read_embedded_cpu(struct mlx5_core_dev *dev);
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int mlx5_ec_init(struct mlx5_core_dev *dev);
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void mlx5_ec_cleanup(struct mlx5_core_dev *dev);
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int mlx5_cmd_host_pf_enable_hca(struct mlx5_core_dev *dev);
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int mlx5_cmd_host_pf_disable_hca(struct mlx5_core_dev *dev);
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#else /* CONFIG_MLX5_ESWITCH */
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static inline bool
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@ -8,6 +8,7 @@
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struct mlx5_flow_table *
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esw_acl_table_create(struct mlx5_eswitch *esw, u16 vport_num, int ns, int size)
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{
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struct mlx5_flow_table_attr ft_attr = {};
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struct mlx5_core_dev *dev = esw->dev;
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struct mlx5_flow_namespace *root_ns;
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struct mlx5_flow_table *acl;
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@ -33,7 +34,9 @@ esw_acl_table_create(struct mlx5_eswitch *esw, u16 vport_num, int ns, int size)
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return ERR_PTR(-EOPNOTSUPP);
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}
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acl = mlx5_create_vport_flow_table(root_ns, 0, size, 0, vport_num);
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ft_attr.max_fte = size;
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ft_attr.flags = MLX5_FLOW_TABLE_OTHER_VPORT;
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acl = mlx5_create_vport_flow_table(root_ns, &ft_attr, vport_num);
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if (IS_ERR(acl)) {
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err = PTR_ERR(acl);
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esw_warn(dev, "vport[%d] create %s ACL table, err(%d)\n", vport_num,
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@ -1474,6 +1474,26 @@ vf_err:
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return err;
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}
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static int host_pf_enable_hca(struct mlx5_core_dev *dev)
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{
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if (!mlx5_core_is_ecpf(dev))
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return 0;
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/* Once vport and representor are ready, take out the external host PF
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* out of initializing state. Enabling HCA clears the iser->initializing
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* bit and host PF driver loading can progress.
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*/
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return mlx5_cmd_host_pf_enable_hca(dev);
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}
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static void host_pf_disable_hca(struct mlx5_core_dev *dev)
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{
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if (!mlx5_core_is_ecpf(dev))
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return;
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mlx5_cmd_host_pf_disable_hca(dev);
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}
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/* mlx5_eswitch_enable_pf_vf_vports() enables vports of PF, ECPF and VFs
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* whichever are present on the eswitch.
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*/
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@ -1488,6 +1508,11 @@ mlx5_eswitch_enable_pf_vf_vports(struct mlx5_eswitch *esw,
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if (ret)
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return ret;
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/* Enable external host PF HCA */
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ret = host_pf_enable_hca(esw->dev);
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if (ret)
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goto pf_hca_err;
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/* Enable ECPF vport */
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if (mlx5_ecpf_vport_exists(esw->dev)) {
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ret = mlx5_eswitch_load_vport(esw, MLX5_VPORT_ECPF, enabled_events);
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@ -1505,8 +1530,9 @@ mlx5_eswitch_enable_pf_vf_vports(struct mlx5_eswitch *esw,
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vf_err:
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if (mlx5_ecpf_vport_exists(esw->dev))
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mlx5_eswitch_unload_vport(esw, MLX5_VPORT_ECPF);
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ecpf_err:
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host_pf_disable_hca(esw->dev);
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pf_hca_err:
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mlx5_eswitch_unload_vport(esw, MLX5_VPORT_PF);
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return ret;
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}
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@ -1521,6 +1547,7 @@ void mlx5_eswitch_disable_pf_vf_vports(struct mlx5_eswitch *esw)
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if (mlx5_ecpf_vport_exists(esw->dev))
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mlx5_eswitch_unload_vport(esw, MLX5_VPORT_ECPF);
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host_pf_disable_hca(esw->dev);
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mlx5_eswitch_unload_vport(esw, MLX5_VPORT_PF);
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}
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@ -172,10 +172,9 @@ static int mlx5_cmd_update_root_ft(struct mlx5_flow_root_namespace *ns,
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MLX5_SET(set_flow_table_root_in, in, table_id, ft->id);
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MLX5_SET(set_flow_table_root_in, in, underlay_qpn, underlay_qpn);
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if (ft->vport) {
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MLX5_SET(set_flow_table_root_in, in, vport_number, ft->vport);
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MLX5_SET(set_flow_table_root_in, in, other_vport, 1);
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}
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MLX5_SET(set_flow_table_root_in, in, vport_number, ft->vport);
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MLX5_SET(set_flow_table_root_in, in, other_vport,
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!!(ft->flags & MLX5_FLOW_TABLE_OTHER_VPORT));
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return mlx5_cmd_exec_in(dev, set_flow_table_root, in);
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}
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@ -199,10 +198,9 @@ static int mlx5_cmd_create_flow_table(struct mlx5_flow_root_namespace *ns,
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MLX5_SET(create_flow_table_in, in, table_type, ft->type);
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MLX5_SET(create_flow_table_in, in, flow_table_context.level, ft->level);
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MLX5_SET(create_flow_table_in, in, flow_table_context.log_size, log_size);
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if (ft->vport) {
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MLX5_SET(create_flow_table_in, in, vport_number, ft->vport);
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MLX5_SET(create_flow_table_in, in, other_vport, 1);
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}
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MLX5_SET(create_flow_table_in, in, vport_number, ft->vport);
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MLX5_SET(create_flow_table_in, in, other_vport,
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!!(ft->flags & MLX5_FLOW_TABLE_OTHER_VPORT));
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MLX5_SET(create_flow_table_in, in, flow_table_context.decap_en,
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en_decap);
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@ -252,10 +250,9 @@ static int mlx5_cmd_destroy_flow_table(struct mlx5_flow_root_namespace *ns,
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MLX5_CMD_OP_DESTROY_FLOW_TABLE);
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MLX5_SET(destroy_flow_table_in, in, table_type, ft->type);
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MLX5_SET(destroy_flow_table_in, in, table_id, ft->id);
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if (ft->vport) {
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MLX5_SET(destroy_flow_table_in, in, vport_number, ft->vport);
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MLX5_SET(destroy_flow_table_in, in, other_vport, 1);
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}
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MLX5_SET(destroy_flow_table_in, in, vport_number, ft->vport);
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MLX5_SET(destroy_flow_table_in, in, other_vport,
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!!(ft->flags & MLX5_FLOW_TABLE_OTHER_VPORT));
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return mlx5_cmd_exec_in(dev, destroy_flow_table, in);
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}
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|
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@ -283,11 +280,9 @@ static int mlx5_cmd_modify_flow_table(struct mlx5_flow_root_namespace *ns,
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flow_table_context.lag_master_next_table_id, 0);
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}
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} else {
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if (ft->vport) {
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MLX5_SET(modify_flow_table_in, in, vport_number,
|
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ft->vport);
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MLX5_SET(modify_flow_table_in, in, other_vport, 1);
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}
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MLX5_SET(modify_flow_table_in, in, vport_number, ft->vport);
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MLX5_SET(modify_flow_table_in, in, other_vport,
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!!(ft->flags & MLX5_FLOW_TABLE_OTHER_VPORT));
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MLX5_SET(modify_flow_table_in, in, modify_field_select,
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MLX5_MODIFY_FLOW_TABLE_MISS_TABLE_ID);
|
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if (next_ft) {
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|
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@ -325,6 +320,9 @@ static int mlx5_cmd_create_flow_group(struct mlx5_flow_root_namespace *ns,
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MLX5_SET(create_flow_group_in, in, other_vport, 1);
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}
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|
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MLX5_SET(create_flow_group_in, in, vport_number, ft->vport);
|
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MLX5_SET(create_flow_group_in, in, other_vport,
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!!(ft->flags & MLX5_FLOW_TABLE_OTHER_VPORT));
|
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err = mlx5_cmd_exec_inout(dev, create_flow_group, in, out);
|
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if (!err)
|
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fg->id = MLX5_GET(create_flow_group_out, out,
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|
|
@ -344,11 +342,9 @@ static int mlx5_cmd_destroy_flow_group(struct mlx5_flow_root_namespace *ns,
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MLX5_SET(destroy_flow_group_in, in, table_type, ft->type);
|
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MLX5_SET(destroy_flow_group_in, in, table_id, ft->id);
|
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MLX5_SET(destroy_flow_group_in, in, group_id, fg->id);
|
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if (ft->vport) {
|
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MLX5_SET(destroy_flow_group_in, in, vport_number, ft->vport);
|
||||
MLX5_SET(destroy_flow_group_in, in, other_vport, 1);
|
||||
}
|
||||
|
||||
MLX5_SET(destroy_flow_group_in, in, vport_number, ft->vport);
|
||||
MLX5_SET(destroy_flow_group_in, in, other_vport,
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||||
!!(ft->flags & MLX5_FLOW_TABLE_OTHER_VPORT));
|
||||
return mlx5_cmd_exec_in(dev, destroy_flow_group, in);
|
||||
}
|
||||
|
||||
|
|
@ -427,10 +423,9 @@ static int mlx5_cmd_set_fte(struct mlx5_core_dev *dev,
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|||
MLX5_SET(set_fte_in, in, ignore_flow_level,
|
||||
!!(fte->action.flags & FLOW_ACT_IGNORE_FLOW_LEVEL));
|
||||
|
||||
if (ft->vport) {
|
||||
MLX5_SET(set_fte_in, in, vport_number, ft->vport);
|
||||
MLX5_SET(set_fte_in, in, other_vport, 1);
|
||||
}
|
||||
MLX5_SET(set_fte_in, in, vport_number, ft->vport);
|
||||
MLX5_SET(set_fte_in, in, other_vport,
|
||||
!!(ft->flags & MLX5_FLOW_TABLE_OTHER_VPORT));
|
||||
|
||||
in_flow_context = MLX5_ADDR_OF(set_fte_in, in, flow_context);
|
||||
MLX5_SET(flow_context, in_flow_context, group_id, group_id);
|
||||
|
|
@ -515,6 +510,9 @@ static int mlx5_cmd_set_fte(struct mlx5_core_dev *dev,
|
|||
dst->dest_attr.vport.pkt_reformat->id);
|
||||
}
|
||||
break;
|
||||
case MLX5_FLOW_DESTINATION_TYPE_FLOW_SAMPLER:
|
||||
id = dst->dest_attr.sampler_id;
|
||||
break;
|
||||
default:
|
||||
id = dst->dest_attr.tir_num;
|
||||
}
|
||||
|
|
@ -601,10 +599,9 @@ static int mlx5_cmd_delete_fte(struct mlx5_flow_root_namespace *ns,
|
|||
MLX5_SET(delete_fte_in, in, table_type, ft->type);
|
||||
MLX5_SET(delete_fte_in, in, table_id, ft->id);
|
||||
MLX5_SET(delete_fte_in, in, flow_index, fte->index);
|
||||
if (ft->vport) {
|
||||
MLX5_SET(delete_fte_in, in, vport_number, ft->vport);
|
||||
MLX5_SET(delete_fte_in, in, other_vport, 1);
|
||||
}
|
||||
MLX5_SET(delete_fte_in, in, vport_number, ft->vport);
|
||||
MLX5_SET(delete_fte_in, in, other_vport,
|
||||
!!(ft->flags & MLX5_FLOW_TABLE_OTHER_VPORT));
|
||||
|
||||
return mlx5_cmd_exec_in(dev, delete_fte, in);
|
||||
}
|
||||
|
|
|
|||
|
|
@ -1152,18 +1152,13 @@ struct mlx5_flow_table *mlx5_create_flow_table(struct mlx5_flow_namespace *ns,
|
|||
{
|
||||
return __mlx5_create_flow_table(ns, ft_attr, FS_FT_OP_MOD_NORMAL, 0);
|
||||
}
|
||||
EXPORT_SYMBOL(mlx5_create_flow_table);
|
||||
|
||||
struct mlx5_flow_table *mlx5_create_vport_flow_table(struct mlx5_flow_namespace *ns,
|
||||
int prio, int max_fte,
|
||||
u32 level, u16 vport)
|
||||
struct mlx5_flow_table *
|
||||
mlx5_create_vport_flow_table(struct mlx5_flow_namespace *ns,
|
||||
struct mlx5_flow_table_attr *ft_attr, u16 vport)
|
||||
{
|
||||
struct mlx5_flow_table_attr ft_attr = {};
|
||||
|
||||
ft_attr.max_fte = max_fte;
|
||||
ft_attr.level = level;
|
||||
ft_attr.prio = prio;
|
||||
|
||||
return __mlx5_create_flow_table(ns, &ft_attr, FS_FT_OP_MOD_NORMAL, vport);
|
||||
return __mlx5_create_flow_table(ns, ft_attr, FS_FT_OP_MOD_NORMAL, vport);
|
||||
}
|
||||
|
||||
struct mlx5_flow_table*
|
||||
|
|
@ -1243,6 +1238,7 @@ struct mlx5_flow_group *mlx5_create_flow_group(struct mlx5_flow_table *ft,
|
|||
|
||||
return fg;
|
||||
}
|
||||
EXPORT_SYMBOL(mlx5_create_flow_group);
|
||||
|
||||
static struct mlx5_flow_rule *alloc_rule(struct mlx5_flow_destination *dest)
|
||||
{
|
||||
|
|
@ -2146,6 +2142,7 @@ void mlx5_destroy_flow_group(struct mlx5_flow_group *fg)
|
|||
mlx5_core_warn(get_dev(&fg->node), "Flow group %d wasn't destroyed, refcount > 1\n",
|
||||
fg->id);
|
||||
}
|
||||
EXPORT_SYMBOL(mlx5_destroy_flow_group);
|
||||
|
||||
struct mlx5_flow_namespace *mlx5_get_fdb_sub_ns(struct mlx5_core_dev *dev,
|
||||
int n)
|
||||
|
|
|
|||
|
|
@ -194,7 +194,7 @@ struct mlx5_ft_underlay_qp {
|
|||
u32 qpn;
|
||||
};
|
||||
|
||||
#define MLX5_FTE_MATCH_PARAM_RESERVED reserved_at_a00
|
||||
#define MLX5_FTE_MATCH_PARAM_RESERVED reserved_at_c00
|
||||
/* Calculate the fte_match_param length and without the reserved length.
|
||||
* Make sure the reserved field is the last.
|
||||
*/
|
||||
|
|
|
|||
|
|
@ -1126,23 +1126,23 @@ static int mlx5_load(struct mlx5_core_dev *dev)
|
|||
goto err_sriov;
|
||||
}
|
||||
|
||||
err = mlx5_sriov_attach(dev);
|
||||
if (err) {
|
||||
mlx5_core_err(dev, "sriov init failed %d\n", err);
|
||||
goto err_sriov;
|
||||
}
|
||||
|
||||
err = mlx5_ec_init(dev);
|
||||
if (err) {
|
||||
mlx5_core_err(dev, "Failed to init embedded CPU\n");
|
||||
goto err_ec;
|
||||
}
|
||||
|
||||
err = mlx5_sriov_attach(dev);
|
||||
if (err) {
|
||||
mlx5_core_err(dev, "sriov init failed %d\n", err);
|
||||
goto err_sriov;
|
||||
}
|
||||
|
||||
return 0;
|
||||
|
||||
err_ec:
|
||||
mlx5_sriov_detach(dev);
|
||||
err_sriov:
|
||||
mlx5_ec_cleanup(dev);
|
||||
err_ec:
|
||||
mlx5_cleanup_fs(dev);
|
||||
err_fs:
|
||||
mlx5_accel_tls_cleanup(dev);
|
||||
|
|
@ -1168,8 +1168,8 @@ err_irq_table:
|
|||
|
||||
static void mlx5_unload(struct mlx5_core_dev *dev)
|
||||
{
|
||||
mlx5_ec_cleanup(dev);
|
||||
mlx5_sriov_detach(dev);
|
||||
mlx5_ec_cleanup(dev);
|
||||
mlx5_cleanup_fs(dev);
|
||||
mlx5_accel_ipsec_cleanup(dev);
|
||||
mlx5_accel_tls_cleanup(dev);
|
||||
|
|
@ -1594,6 +1594,7 @@ static const struct pci_device_id mlx5_core_pci_table[] = {
|
|||
{ PCI_VDEVICE(MELLANOX, 0xa2d2) }, /* BlueField integrated ConnectX-5 network controller */
|
||||
{ PCI_VDEVICE(MELLANOX, 0xa2d3), MLX5_PCI_DEV_IS_VF}, /* BlueField integrated ConnectX-5 network controller VF */
|
||||
{ PCI_VDEVICE(MELLANOX, 0xa2d6) }, /* BlueField-2 integrated ConnectX-6 Dx network controller */
|
||||
{ PCI_VDEVICE(MELLANOX, 0xa2dc) }, /* BlueField-3 integrated ConnectX-7 network controller */
|
||||
{ 0, }
|
||||
};
|
||||
|
||||
|
|
|
|||
|
|
@ -122,6 +122,10 @@ enum mlx5_semaphore_space_address {
|
|||
|
||||
int mlx5_query_hca_caps(struct mlx5_core_dev *dev);
|
||||
int mlx5_query_board_id(struct mlx5_core_dev *dev);
|
||||
int mlx5_cmd_init(struct mlx5_core_dev *dev);
|
||||
void mlx5_cmd_cleanup(struct mlx5_core_dev *dev);
|
||||
void mlx5_cmd_set_state(struct mlx5_core_dev *dev,
|
||||
enum mlx5_cmdif_state cmdif_state);
|
||||
int mlx5_cmd_init_hca(struct mlx5_core_dev *dev, uint32_t *sw_owner_id);
|
||||
int mlx5_cmd_teardown_hca(struct mlx5_core_dev *dev);
|
||||
int mlx5_cmd_force_teardown_hca(struct mlx5_core_dev *dev);
|
||||
|
|
|
|||
|
|
@ -374,7 +374,7 @@ retry:
|
|||
if (func_id)
|
||||
dev->priv.vfs_pages += npages;
|
||||
else if (mlx5_core_is_ecpf(dev) && !ec_function)
|
||||
dev->priv.peer_pf_pages += npages;
|
||||
dev->priv.host_pf_pages += npages;
|
||||
|
||||
mlx5_core_dbg(dev, "npages %d, ec_function %d, func_id 0x%x, err %d\n",
|
||||
npages, ec_function, func_id, err);
|
||||
|
|
@ -416,7 +416,7 @@ static void release_all_pages(struct mlx5_core_dev *dev, u32 func_id,
|
|||
if (func_id)
|
||||
dev->priv.vfs_pages -= npages;
|
||||
else if (mlx5_core_is_ecpf(dev) && !ec_function)
|
||||
dev->priv.peer_pf_pages -= npages;
|
||||
dev->priv.host_pf_pages -= npages;
|
||||
|
||||
mlx5_core_dbg(dev, "npages %d, ec_function %d, func_id 0x%x\n",
|
||||
npages, ec_function, func_id);
|
||||
|
|
@ -506,7 +506,7 @@ static int reclaim_pages(struct mlx5_core_dev *dev, u32 func_id, int npages,
|
|||
if (func_id)
|
||||
dev->priv.vfs_pages -= num_claimed;
|
||||
else if (mlx5_core_is_ecpf(dev) && !ec_function)
|
||||
dev->priv.peer_pf_pages -= num_claimed;
|
||||
dev->priv.host_pf_pages -= num_claimed;
|
||||
|
||||
out_free:
|
||||
kvfree(out);
|
||||
|
|
@ -661,9 +661,9 @@ int mlx5_reclaim_startup_pages(struct mlx5_core_dev *dev)
|
|||
WARN(dev->priv.vfs_pages,
|
||||
"VFs FW pages counter is %d after reclaiming all pages\n",
|
||||
dev->priv.vfs_pages);
|
||||
WARN(dev->priv.peer_pf_pages,
|
||||
"Peer PF FW pages counter is %d after reclaiming all pages\n",
|
||||
dev->priv.peer_pf_pages);
|
||||
WARN(dev->priv.host_pf_pages,
|
||||
"External host PF FW pages counter is %d after reclaiming all pages\n",
|
||||
dev->priv.host_pf_pages);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
|
|
|||
|
|
@ -643,7 +643,7 @@ static int dr_matcher_init(struct mlx5dr_matcher *matcher,
|
|||
}
|
||||
|
||||
if (mask) {
|
||||
if (mask->match_sz > sizeof(struct mlx5dr_match_param)) {
|
||||
if (mask->match_sz > DR_SZ_MATCH_PARAM) {
|
||||
mlx5dr_err(dmn, "Invalid match size attribute\n");
|
||||
return -EINVAL;
|
||||
}
|
||||
|
|
|
|||
|
|
@ -874,8 +874,7 @@ static bool dr_rule_verify(struct mlx5dr_matcher *matcher,
|
|||
u32 s_idx, e_idx;
|
||||
|
||||
if (!value_size ||
|
||||
(value_size > sizeof(struct mlx5dr_match_param) ||
|
||||
(value_size % sizeof(u32)))) {
|
||||
(value_size > DR_SZ_MATCH_PARAM || (value_size % sizeof(u32)))) {
|
||||
mlx5dr_err(matcher->tbl->dmn, "Rule parameters length is incorrect\n");
|
||||
return false;
|
||||
}
|
||||
|
|
|
|||
|
|
@ -17,6 +17,7 @@
|
|||
#define WIRE_PORT 0xFFFF
|
||||
#define DR_STE_SVLAN 0x1
|
||||
#define DR_STE_CVLAN 0x2
|
||||
#define DR_SZ_MATCH_PARAM (MLX5_ST_SZ_DW_MATCH_PARAM * 4)
|
||||
|
||||
#define mlx5dr_err(dmn, arg...) mlx5_core_err((dmn)->mdev, ##arg)
|
||||
#define mlx5dr_info(dmn, arg...) mlx5_core_info((dmn)->mdev, ##arg)
|
||||
|
|
|
|||
|
|
@ -346,6 +346,7 @@ enum mlx5_event {
|
|||
MLX5_EVENT_TYPE_NIC_VPORT_CHANGE = 0xd,
|
||||
|
||||
MLX5_EVENT_TYPE_ESW_FUNCTIONS_CHANGED = 0xe,
|
||||
MLX5_EVENT_TYPE_VHCA_STATE_CHANGE = 0xf,
|
||||
|
||||
MLX5_EVENT_TYPE_DCT_DRAINED = 0x1c,
|
||||
MLX5_EVENT_TYPE_DCT_KEY_VIOLATION = 0x1d,
|
||||
|
|
@ -717,6 +718,11 @@ struct mlx5_eqe_sync_fw_update {
|
|||
u8 sync_rst_state;
|
||||
};
|
||||
|
||||
struct mlx5_eqe_vhca_state {
|
||||
__be16 ec_function;
|
||||
__be16 function_id;
|
||||
} __packed;
|
||||
|
||||
union ev_data {
|
||||
__be32 raw[7];
|
||||
struct mlx5_eqe_cmd cmd;
|
||||
|
|
@ -736,6 +742,7 @@ union ev_data {
|
|||
struct mlx5_eqe_temp_warning temp_warning;
|
||||
struct mlx5_eqe_xrq_err xrq_err;
|
||||
struct mlx5_eqe_sync_fw_update sync_fw_update;
|
||||
struct mlx5_eqe_vhca_state vhca_state;
|
||||
} __packed;
|
||||
|
||||
struct mlx5_eqe {
|
||||
|
|
@ -1076,6 +1083,7 @@ enum {
|
|||
MLX5_MATCH_INNER_HEADERS = 1 << 2,
|
||||
MLX5_MATCH_MISC_PARAMETERS_2 = 1 << 3,
|
||||
MLX5_MATCH_MISC_PARAMETERS_3 = 1 << 4,
|
||||
MLX5_MATCH_MISC_PARAMETERS_4 = 1 << 5,
|
||||
};
|
||||
|
||||
enum {
|
||||
|
|
|
|||
|
|
@ -547,7 +547,7 @@ struct mlx5_priv {
|
|||
atomic_t reg_pages;
|
||||
struct list_head free_list;
|
||||
int vfs_pages;
|
||||
int peer_pf_pages;
|
||||
int host_pf_pages;
|
||||
|
||||
struct mlx5_core_health health;
|
||||
|
||||
|
|
@ -888,10 +888,6 @@ enum {
|
|||
CMD_ALLOWED_OPCODE_ALL,
|
||||
};
|
||||
|
||||
int mlx5_cmd_init(struct mlx5_core_dev *dev);
|
||||
void mlx5_cmd_cleanup(struct mlx5_core_dev *dev);
|
||||
void mlx5_cmd_set_state(struct mlx5_core_dev *dev,
|
||||
enum mlx5_cmdif_state cmdif_state);
|
||||
void mlx5_cmd_use_events(struct mlx5_core_dev *dev);
|
||||
void mlx5_cmd_use_polling(struct mlx5_core_dev *dev);
|
||||
void mlx5_cmd_allowed_opcode(struct mlx5_core_dev *dev, u16 opcode);
|
||||
|
|
@ -1137,7 +1133,7 @@ static inline bool mlx5_core_is_vf(const struct mlx5_core_dev *dev)
|
|||
return dev->coredev_type == MLX5_COREDEV_VF;
|
||||
}
|
||||
|
||||
static inline bool mlx5_core_is_ecpf(struct mlx5_core_dev *dev)
|
||||
static inline bool mlx5_core_is_ecpf(const struct mlx5_core_dev *dev)
|
||||
{
|
||||
return dev->caps.embedded_cpu;
|
||||
}
|
||||
|
|
|
|||
|
|
@ -50,6 +50,7 @@ enum {
|
|||
MLX5_FLOW_TABLE_TUNNEL_EN_DECAP = BIT(1),
|
||||
MLX5_FLOW_TABLE_TERMINATION = BIT(2),
|
||||
MLX5_FLOW_TABLE_UNMANAGED = BIT(3),
|
||||
MLX5_FLOW_TABLE_OTHER_VPORT = BIT(4),
|
||||
};
|
||||
|
||||
#define LEFTOVERS_RULE_NUM 2
|
||||
|
|
@ -132,6 +133,7 @@ struct mlx5_flow_destination {
|
|||
struct mlx5_pkt_reformat *pkt_reformat;
|
||||
u8 flags;
|
||||
} vport;
|
||||
u32 sampler_id;
|
||||
};
|
||||
};
|
||||
|
||||
|
|
@ -173,9 +175,7 @@ mlx5_create_auto_grouped_flow_table(struct mlx5_flow_namespace *ns,
|
|||
|
||||
struct mlx5_flow_table *
|
||||
mlx5_create_vport_flow_table(struct mlx5_flow_namespace *ns,
|
||||
int prio,
|
||||
int num_flow_table_entries,
|
||||
u32 level, u16 vport);
|
||||
struct mlx5_flow_table_attr *ft_attr, u16 vport);
|
||||
struct mlx5_flow_table *mlx5_create_lag_demux_flow_table(
|
||||
struct mlx5_flow_namespace *ns,
|
||||
int prio, u32 level);
|
||||
|
|
|
|||
|
|
@ -299,6 +299,8 @@ enum {
|
|||
MLX5_CMD_OP_CREATE_UMEM = 0xa08,
|
||||
MLX5_CMD_OP_DESTROY_UMEM = 0xa0a,
|
||||
MLX5_CMD_OP_SYNC_STEERING = 0xb00,
|
||||
MLX5_CMD_OP_QUERY_VHCA_STATE = 0xb0d,
|
||||
MLX5_CMD_OP_MODIFY_VHCA_STATE = 0xb0e,
|
||||
MLX5_CMD_OP_MAX
|
||||
};
|
||||
|
||||
|
|
@ -623,6 +625,26 @@ struct mlx5_ifc_fte_match_set_misc3_bits {
|
|||
u8 reserved_at_140[0xc0];
|
||||
};
|
||||
|
||||
struct mlx5_ifc_fte_match_set_misc4_bits {
|
||||
u8 prog_sample_field_value_0[0x20];
|
||||
|
||||
u8 prog_sample_field_id_0[0x20];
|
||||
|
||||
u8 prog_sample_field_value_1[0x20];
|
||||
|
||||
u8 prog_sample_field_id_1[0x20];
|
||||
|
||||
u8 prog_sample_field_value_2[0x20];
|
||||
|
||||
u8 prog_sample_field_id_2[0x20];
|
||||
|
||||
u8 prog_sample_field_value_3[0x20];
|
||||
|
||||
u8 prog_sample_field_id_3[0x20];
|
||||
|
||||
u8 reserved_at_100[0x100];
|
||||
};
|
||||
|
||||
struct mlx5_ifc_cmd_pas_bits {
|
||||
u8 pa_h[0x20];
|
||||
|
||||
|
|
@ -891,7 +913,10 @@ struct mlx5_ifc_per_protocol_networking_offload_caps_bits {
|
|||
u8 tunnel_stateless_ipv4_over_vxlan[0x1];
|
||||
u8 tunnel_stateless_ip_over_ip[0x1];
|
||||
u8 insert_trailer[0x1];
|
||||
u8 reserved_at_2b[0x5];
|
||||
u8 reserved_at_2b[0x1];
|
||||
u8 tunnel_stateless_ip_over_ip_rx[0x1];
|
||||
u8 tunnel_stateless_ip_over_ip_tx[0x1];
|
||||
u8 reserved_at_2e[0x2];
|
||||
u8 max_vxlan_udp_ports[0x8];
|
||||
u8 reserved_at_38[0x6];
|
||||
u8 max_geneve_opt_len[0x1];
|
||||
|
|
@ -1224,7 +1249,16 @@ enum mlx5_fc_bulk_alloc_bitmask {
|
|||
#define MLX5_FC_BULK_NUM_FCS(fc_enum) (MLX5_FC_BULK_SIZE_FACTOR * (fc_enum))
|
||||
|
||||
struct mlx5_ifc_cmd_hca_cap_bits {
|
||||
u8 reserved_at_0[0x30];
|
||||
u8 reserved_at_0[0x1f];
|
||||
u8 vhca_resource_manager[0x1];
|
||||
|
||||
u8 reserved_at_20[0x3];
|
||||
u8 event_on_vhca_state_teardown_request[0x1];
|
||||
u8 event_on_vhca_state_in_use[0x1];
|
||||
u8 event_on_vhca_state_active[0x1];
|
||||
u8 event_on_vhca_state_allocated[0x1];
|
||||
u8 event_on_vhca_state_invalid[0x1];
|
||||
u8 reserved_at_28[0x8];
|
||||
u8 vhca_id[0x10];
|
||||
|
||||
u8 reserved_at_40[0x40];
|
||||
|
|
@ -1241,7 +1275,9 @@ struct mlx5_ifc_cmd_hca_cap_bits {
|
|||
u8 ece_support[0x1];
|
||||
u8 reserved_at_a4[0x7];
|
||||
u8 log_max_srq[0x5];
|
||||
u8 reserved_at_b0[0x10];
|
||||
u8 reserved_at_b0[0x2];
|
||||
u8 ts_cqe_to_dest_cqn[0x1];
|
||||
u8 reserved_at_b3[0xd];
|
||||
|
||||
u8 max_sgl_for_optimized_performance[0x8];
|
||||
u8 log_max_cq_sz[0x8];
|
||||
|
|
@ -1512,7 +1548,8 @@ struct mlx5_ifc_cmd_hca_cap_bits {
|
|||
u8 disable_local_lb_uc[0x1];
|
||||
u8 disable_local_lb_mc[0x1];
|
||||
u8 log_min_hairpin_wq_data_sz[0x5];
|
||||
u8 reserved_at_3e8[0x3];
|
||||
u8 reserved_at_3e8[0x2];
|
||||
u8 vhca_state[0x1];
|
||||
u8 log_max_vlan_list[0x5];
|
||||
u8 reserved_at_3f0[0x3];
|
||||
u8 log_max_current_mc_list[0x5];
|
||||
|
|
@ -1580,7 +1617,7 @@ struct mlx5_ifc_cmd_hca_cap_bits {
|
|||
u8 max_num_of_monitor_counters[0x10];
|
||||
u8 num_ppcnt_monitor_counters[0x10];
|
||||
|
||||
u8 reserved_at_640[0x10];
|
||||
u8 max_num_sf[0x10];
|
||||
u8 num_q_monitor_counters[0x10];
|
||||
|
||||
u8 reserved_at_660[0x20];
|
||||
|
|
@ -1616,6 +1653,7 @@ enum mlx5_flow_destination_type {
|
|||
MLX5_FLOW_DESTINATION_TYPE_VPORT = 0x0,
|
||||
MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE = 0x1,
|
||||
MLX5_FLOW_DESTINATION_TYPE_TIR = 0x2,
|
||||
MLX5_FLOW_DESTINATION_TYPE_FLOW_SAMPLER = 0x6,
|
||||
|
||||
MLX5_FLOW_DESTINATION_TYPE_PORT = 0x99,
|
||||
MLX5_FLOW_DESTINATION_TYPE_COUNTER = 0x100,
|
||||
|
|
@ -1668,7 +1706,9 @@ struct mlx5_ifc_fte_match_param_bits {
|
|||
|
||||
struct mlx5_ifc_fte_match_set_misc3_bits misc_parameters_3;
|
||||
|
||||
u8 reserved_at_a00[0x600];
|
||||
struct mlx5_ifc_fte_match_set_misc4_bits misc_parameters_4;
|
||||
|
||||
u8 reserved_at_c00[0x400];
|
||||
};
|
||||
|
||||
enum {
|
||||
|
|
@ -3289,8 +3329,12 @@ struct mlx5_ifc_sqc_bits {
|
|||
u8 reserved_at_80[0x10];
|
||||
u8 hairpin_peer_vhca[0x10];
|
||||
|
||||
u8 reserved_at_a0[0x50];
|
||||
u8 reserved_at_a0[0x20];
|
||||
|
||||
u8 reserved_at_c0[0x8];
|
||||
u8 ts_cqe_to_dest_cqn[0x18];
|
||||
|
||||
u8 reserved_at_e0[0x10];
|
||||
u8 packet_pacing_rate_limit_index[0x10];
|
||||
u8 tis_lst_sz[0x10];
|
||||
u8 reserved_at_110[0x10];
|
||||
|
|
@ -4204,7 +4248,11 @@ struct mlx5_ifc_set_hca_cap_in_bits {
|
|||
u8 reserved_at_20[0x10];
|
||||
u8 op_mod[0x10];
|
||||
|
||||
u8 reserved_at_40[0x40];
|
||||
u8 other_function[0x1];
|
||||
u8 reserved_at_41[0xf];
|
||||
u8 function_id[0x10];
|
||||
|
||||
u8 reserved_at_60[0x20];
|
||||
|
||||
union mlx5_ifc_hca_cap_union_bits capability;
|
||||
};
|
||||
|
|
@ -5461,6 +5509,7 @@ enum {
|
|||
MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_INNER_HEADERS = 0x2,
|
||||
MLX5_QUERY_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS_2 = 0x3,
|
||||
MLX5_QUERY_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS_3 = 0x4,
|
||||
MLX5_QUERY_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS_4 = 0x5,
|
||||
};
|
||||
|
||||
struct mlx5_ifc_query_flow_group_out_bits {
|
||||
|
|
@ -10657,11 +10706,13 @@ struct mlx5_ifc_affiliated_event_header_bits {
|
|||
enum {
|
||||
MLX5_HCA_CAP_GENERAL_OBJECT_TYPES_ENCRYPTION_KEY = BIT(0xc),
|
||||
MLX5_HCA_CAP_GENERAL_OBJECT_TYPES_IPSEC = BIT(0x13),
|
||||
MLX5_HCA_CAP_GENERAL_OBJECT_TYPES_SAMPLER = BIT(0x20),
|
||||
};
|
||||
|
||||
enum {
|
||||
MLX5_GENERAL_OBJECT_TYPES_ENCRYPTION_KEY = 0xc,
|
||||
MLX5_GENERAL_OBJECT_TYPES_IPSEC = 0x13,
|
||||
MLX5_GENERAL_OBJECT_TYPES_SAMPLER = 0x20,
|
||||
};
|
||||
|
||||
enum {
|
||||
|
|
@ -10736,6 +10787,33 @@ struct mlx5_ifc_create_encryption_key_in_bits {
|
|||
struct mlx5_ifc_encryption_key_obj_bits encryption_key_object;
|
||||
};
|
||||
|
||||
struct mlx5_ifc_sampler_obj_bits {
|
||||
u8 modify_field_select[0x40];
|
||||
|
||||
u8 table_type[0x8];
|
||||
u8 level[0x8];
|
||||
u8 reserved_at_50[0xf];
|
||||
u8 ignore_flow_level[0x1];
|
||||
|
||||
u8 sample_ratio[0x20];
|
||||
|
||||
u8 reserved_at_80[0x8];
|
||||
u8 sample_table_id[0x18];
|
||||
|
||||
u8 reserved_at_a0[0x8];
|
||||
u8 default_table_id[0x18];
|
||||
|
||||
u8 sw_steering_icm_address_rx[0x40];
|
||||
u8 sw_steering_icm_address_tx[0x40];
|
||||
|
||||
u8 reserved_at_140[0xa0];
|
||||
};
|
||||
|
||||
struct mlx5_ifc_create_sampler_obj_in_bits {
|
||||
struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr;
|
||||
struct mlx5_ifc_sampler_obj_bits sampler_object;
|
||||
};
|
||||
|
||||
enum {
|
||||
MLX5_GENERAL_OBJECT_TYPE_ENCRYPTION_KEY_KEY_SIZE_128 = 0x0,
|
||||
MLX5_GENERAL_OBJECT_TYPE_ENCRYPTION_KEY_KEY_SIZE_256 = 0x1,
|
||||
|
|
|
|||
|
|
@ -232,7 +232,7 @@ enum mlx5_ib_device_query_context_attrs {
|
|||
MLX5_IB_ATTR_QUERY_CONTEXT_RESP_UCTX = (1U << UVERBS_ID_NS_SHIFT),
|
||||
};
|
||||
|
||||
#define MLX5_IB_DW_MATCH_PARAM 0x80
|
||||
#define MLX5_IB_DW_MATCH_PARAM 0x90
|
||||
|
||||
struct mlx5_ib_match_params {
|
||||
__u32 match_params[MLX5_IB_DW_MATCH_PARAM];
|
||||
|
|
|
|||
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