pinctrl: actions: Add gpio support for Actions S900 SoC
Add gpio support to pinctrl driver for Actions Semi S900 SoC. Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Reviewed-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
This commit is contained in:
Manivannan Sadhasivam
Linus Walleij
Родитель
b85bcc35e1
Коммит
33257f860a
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@ -4,6 +4,7 @@ config PINCTRL_OWL
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select PINMUX
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select PINCONF
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select GENERIC_PINCONF
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select GPIOLIB
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help
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Say Y here to enable Actions Semi OWL pinctrl driver
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@ -11,6 +11,7 @@
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#include <linux/clk.h>
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#include <linux/err.h>
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#include <linux/gpio/driver.h>
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#include <linux/io.h>
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#include <linux/module.h>
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#include <linux/of.h>
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@ -31,6 +32,7 @@
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* struct owl_pinctrl - pinctrl state of the device
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* @dev: device handle
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* @pctrldev: pinctrl handle
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* @chip: gpio chip
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* @lock: spinlock to protect registers
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* @soc: reference to soc_data
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* @base: pinctrl register base address
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@ -38,6 +40,7 @@
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struct owl_pinctrl {
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struct device *dev;
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struct pinctrl_dev *pctrldev;
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struct gpio_chip chip;
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raw_spinlock_t lock;
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struct clk *clk;
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const struct owl_pinctrl_soc_data *soc;
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@ -536,6 +539,190 @@ static struct pinctrl_desc owl_pinctrl_desc = {
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.owner = THIS_MODULE,
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};
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static const struct owl_gpio_port *
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owl_gpio_get_port(struct owl_pinctrl *pctrl, unsigned int *pin)
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{
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unsigned int start = 0, i;
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for (i = 0; i < pctrl->soc->nports; i++) {
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const struct owl_gpio_port *port = &pctrl->soc->ports[i];
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if (*pin >= start && *pin < start + port->pins) {
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*pin -= start;
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return port;
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}
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start += port->pins;
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}
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return NULL;
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}
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static void owl_gpio_update_reg(void __iomem *base, unsigned int pin, int flag)
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{
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u32 val;
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val = readl_relaxed(base);
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if (flag)
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val |= BIT(pin);
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else
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val &= ~BIT(pin);
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writel_relaxed(val, base);
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}
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static int owl_gpio_request(struct gpio_chip *chip, unsigned int offset)
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{
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struct owl_pinctrl *pctrl = gpiochip_get_data(chip);
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const struct owl_gpio_port *port;
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void __iomem *gpio_base;
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unsigned long flags;
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port = owl_gpio_get_port(pctrl, &offset);
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if (WARN_ON(port == NULL))
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return -ENODEV;
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gpio_base = pctrl->base + port->offset;
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/*
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* GPIOs have higher priority over other modules, so either setting
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* them as OUT or IN is sufficient
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*/
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raw_spin_lock_irqsave(&pctrl->lock, flags);
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owl_gpio_update_reg(gpio_base + port->outen, offset, true);
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raw_spin_unlock_irqrestore(&pctrl->lock, flags);
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return 0;
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}
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static void owl_gpio_free(struct gpio_chip *chip, unsigned int offset)
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{
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struct owl_pinctrl *pctrl = gpiochip_get_data(chip);
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const struct owl_gpio_port *port;
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void __iomem *gpio_base;
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unsigned long flags;
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port = owl_gpio_get_port(pctrl, &offset);
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if (WARN_ON(port == NULL))
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return;
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gpio_base = pctrl->base + port->offset;
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raw_spin_lock_irqsave(&pctrl->lock, flags);
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/* disable gpio output */
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owl_gpio_update_reg(gpio_base + port->outen, offset, false);
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/* disable gpio input */
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owl_gpio_update_reg(gpio_base + port->inen, offset, false);
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raw_spin_unlock_irqrestore(&pctrl->lock, flags);
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}
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static int owl_gpio_get(struct gpio_chip *chip, unsigned int offset)
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{
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struct owl_pinctrl *pctrl = gpiochip_get_data(chip);
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const struct owl_gpio_port *port;
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void __iomem *gpio_base;
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unsigned long flags;
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u32 val;
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port = owl_gpio_get_port(pctrl, &offset);
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if (WARN_ON(port == NULL))
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return -ENODEV;
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gpio_base = pctrl->base + port->offset;
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raw_spin_lock_irqsave(&pctrl->lock, flags);
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val = readl_relaxed(gpio_base + port->dat);
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raw_spin_unlock_irqrestore(&pctrl->lock, flags);
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return !!(val & BIT(offset));
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}
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static void owl_gpio_set(struct gpio_chip *chip, unsigned int offset, int value)
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{
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struct owl_pinctrl *pctrl = gpiochip_get_data(chip);
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const struct owl_gpio_port *port;
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void __iomem *gpio_base;
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unsigned long flags;
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port = owl_gpio_get_port(pctrl, &offset);
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if (WARN_ON(port == NULL))
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return;
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gpio_base = pctrl->base + port->offset;
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raw_spin_lock_irqsave(&pctrl->lock, flags);
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owl_gpio_update_reg(gpio_base + port->dat, offset, value);
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raw_spin_unlock_irqrestore(&pctrl->lock, flags);
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}
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static int owl_gpio_direction_input(struct gpio_chip *chip, unsigned int offset)
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{
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struct owl_pinctrl *pctrl = gpiochip_get_data(chip);
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const struct owl_gpio_port *port;
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void __iomem *gpio_base;
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unsigned long flags;
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port = owl_gpio_get_port(pctrl, &offset);
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if (WARN_ON(port == NULL))
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return -ENODEV;
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gpio_base = pctrl->base + port->offset;
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raw_spin_lock_irqsave(&pctrl->lock, flags);
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owl_gpio_update_reg(gpio_base + port->outen, offset, false);
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owl_gpio_update_reg(gpio_base + port->inen, offset, true);
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raw_spin_unlock_irqrestore(&pctrl->lock, flags);
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return 0;
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}
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static int owl_gpio_direction_output(struct gpio_chip *chip,
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unsigned int offset, int value)
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{
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struct owl_pinctrl *pctrl = gpiochip_get_data(chip);
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const struct owl_gpio_port *port;
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void __iomem *gpio_base;
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unsigned long flags;
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port = owl_gpio_get_port(pctrl, &offset);
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if (WARN_ON(port == NULL))
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return -ENODEV;
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gpio_base = pctrl->base + port->offset;
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raw_spin_lock_irqsave(&pctrl->lock, flags);
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owl_gpio_update_reg(gpio_base + port->inen, offset, false);
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owl_gpio_update_reg(gpio_base + port->outen, offset, true);
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owl_gpio_update_reg(gpio_base + port->dat, offset, value);
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raw_spin_unlock_irqrestore(&pctrl->lock, flags);
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return 0;
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}
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static int owl_gpio_init(struct owl_pinctrl *pctrl)
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{
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struct gpio_chip *chip;
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int ret;
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chip = &pctrl->chip;
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chip->base = -1;
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chip->ngpio = pctrl->soc->ngpios;
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chip->label = dev_name(pctrl->dev);
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chip->parent = pctrl->dev;
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chip->owner = THIS_MODULE;
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chip->of_node = pctrl->dev->of_node;
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ret = gpiochip_add_data(&pctrl->chip, pctrl);
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if (ret) {
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dev_err(pctrl->dev, "failed to register gpiochip\n");
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return ret;
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}
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return 0;
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}
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int owl_pinctrl_probe(struct platform_device *pdev,
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struct owl_pinctrl_soc_data *soc_data)
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{
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@ -571,6 +758,13 @@ int owl_pinctrl_probe(struct platform_device *pdev,
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owl_pinctrl_desc.pins = soc_data->pins;
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owl_pinctrl_desc.npins = soc_data->npins;
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pctrl->chip.direction_input = owl_gpio_direction_input;
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pctrl->chip.direction_output = owl_gpio_direction_output;
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pctrl->chip.get = owl_gpio_get;
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pctrl->chip.set = owl_gpio_set;
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pctrl->chip.request = owl_gpio_request;
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pctrl->chip.free = owl_gpio_free;
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pctrl->soc = soc_data;
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pctrl->dev = &pdev->dev;
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@ -581,6 +775,10 @@ int owl_pinctrl_probe(struct platform_device *pdev,
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return PTR_ERR(pctrl->pctrldev);
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}
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ret = owl_gpio_init(pctrl);
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if (ret)
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return ret;
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platform_set_drvdata(pdev, pctrl);
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return 0;
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@ -114,6 +114,22 @@ struct owl_pinmux_func {
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unsigned int ngroups;
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};
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/**
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* struct owl_gpio_port - Actions GPIO port info
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* @offset: offset of the GPIO port.
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* @pins: number of pins belongs to the GPIO port.
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* @outen: offset of the output enable register.
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* @inen: offset of the input enable register.
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* @dat: offset of the data register.
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*/
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struct owl_gpio_port {
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unsigned int offset;
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unsigned int pins;
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unsigned int outen;
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unsigned int inen;
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unsigned int dat;
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};
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/**
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* struct owl_pinctrl_soc_data - Actions pin controller driver configuration
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* @pins: array describing all pins of the pin controller.
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@ -124,6 +140,8 @@ struct owl_pinmux_func {
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* @ngroups: number of entries in @groups.
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* @padinfo: array describing the pad info of this SoC.
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* @ngpios: number of pingroups the driver should expose as GPIOs.
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* @port: array describing all GPIO ports of this SoC.
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* @nports: number of GPIO ports in this SoC.
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*/
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struct owl_pinctrl_soc_data {
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const struct pinctrl_pin_desc *pins;
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@ -134,6 +152,8 @@ struct owl_pinctrl_soc_data {
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unsigned int ngroups;
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const struct owl_padinfo *padinfo;
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unsigned int ngpios;
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const struct owl_gpio_port *ports;
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unsigned int nports;
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};
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int owl_pinctrl_probe(struct platform_device *pdev,
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@ -33,6 +33,13 @@
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#define PAD_SR1 (0x0274)
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#define PAD_SR2 (0x0278)
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#define OWL_GPIO_PORT_A 0
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#define OWL_GPIO_PORT_B 1
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#define OWL_GPIO_PORT_C 2
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#define OWL_GPIO_PORT_D 3
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#define OWL_GPIO_PORT_E 4
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#define OWL_GPIO_PORT_F 5
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#define _GPIOA(offset) (offset)
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#define _GPIOB(offset) (32 + (offset))
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#define _GPIOC(offset) (64 + (offset))
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@ -1814,6 +1821,24 @@ static struct owl_padinfo s900_padinfo[NUM_PADS] = {
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[SGPIO3] = PAD_INFO_PULLCTL_ST(SGPIO3)
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};
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#define OWL_GPIO_PORT(port, base, count, _outen, _inen, _dat) \
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[OWL_GPIO_PORT_##port] = { \
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.offset = base, \
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.pins = count, \
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.outen = _outen, \
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.inen = _inen, \
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.dat = _dat, \
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}
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static const struct owl_gpio_port s900_gpio_ports[] = {
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OWL_GPIO_PORT(A, 0x0000, 32, 0x0, 0x4, 0x8),
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OWL_GPIO_PORT(B, 0x000C, 32, 0x0, 0x4, 0x8),
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OWL_GPIO_PORT(C, 0x0018, 12, 0x0, 0x4, 0x8),
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OWL_GPIO_PORT(D, 0x0024, 30, 0x0, 0x4, 0x8),
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OWL_GPIO_PORT(E, 0x0030, 32, 0x0, 0x4, 0x8),
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OWL_GPIO_PORT(F, 0x00F0, 8, 0x0, 0x4, 0x8)
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};
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static struct owl_pinctrl_soc_data s900_pinctrl_data = {
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.padinfo = s900_padinfo,
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.pins = (const struct pinctrl_pin_desc *)s900_pads,
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@ -1822,7 +1847,9 @@ static struct owl_pinctrl_soc_data s900_pinctrl_data = {
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.nfunctions = ARRAY_SIZE(s900_functions),
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.groups = s900_groups,
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.ngroups = ARRAY_SIZE(s900_groups),
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.ngpios = NUM_GPIOS
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.ngpios = NUM_GPIOS,
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.ports = s900_gpio_ports,
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.nports = ARRAY_SIZE(s900_gpio_ports)
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};
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static int s900_pinctrl_probe(struct platform_device *pdev)
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