x86/oprofile: replace macros to calculate control register
This patch introduces op_x86_get_ctrl() to calculate the value of the performance control register. This is generic code usable for all models. The event and reserved masks are model specific and stored in struct op_x86_model_spec. 64 bit MSR functions are used now. The patch removes many hard to read macros used for ctrl calculation. The function op_x86_get_ctrl() is common code and the first step to further merge performance counter implementations for x86 models. Signed-off-by: Robert Richter <robert.richter@amd.com>
This commit is contained in:
Robert Richter
Родитель
ef8828ddf8
Коммит
3370d35856
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@ -31,6 +31,26 @@ static DEFINE_PER_CPU(unsigned long, saved_lvtpc);
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/* 0 == registered but off, 1 == registered and on */
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static int nmi_enabled = 0;
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/* common functions */
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u64 op_x86_get_ctrl(struct op_x86_model_spec const *model,
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struct op_counter_config *counter_config)
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{
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u64 val = 0;
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u16 event = (u16)counter_config->event;
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val |= ARCH_PERFMON_EVENTSEL_INT;
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val |= counter_config->user ? ARCH_PERFMON_EVENTSEL_USR : 0;
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val |= counter_config->kernel ? ARCH_PERFMON_EVENTSEL_OS : 0;
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val |= (counter_config->unit_mask & 0xFF) << 8;
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event &= model->event_mask ? model->event_mask : 0xFF;
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val |= event & 0xFF;
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val |= (event & 0x0F00) << 24;
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return val;
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}
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static int profile_exceptions_notify(struct notifier_block *self,
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unsigned long val, void *data)
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{
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@ -25,12 +25,11 @@
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#define NUM_COUNTERS 4
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#define NUM_CONTROLS 4
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#define OP_EVENT_MASK 0x0FFF
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#define MSR_AMD_EVENTSEL_RESERVED ((0xFFFFFCF0ULL<<32)|(1ULL<<21))
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#define CTR_OVERFLOWED(n) (!((n) & (1U<<31)))
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#define CTRL_CLEAR_LO(x) (x &= (1<<21))
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#define CTRL_CLEAR_HI(x) (x &= 0xfffffcf0)
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#define CTRL_SET_EVENT_LOW(val, e) (val |= (e & 0xff))
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#define CTRL_SET_EVENT_HIGH(val, e) (val |= ((e >> 8) & 0xf))
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static unsigned long reset_value[NUM_COUNTERS];
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@ -84,21 +83,19 @@ static void op_amd_fill_in_addresses(struct op_msrs * const msrs)
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}
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}
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static void op_amd_setup_ctrs(struct op_x86_model_spec const *model,
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struct op_msrs const * const msrs)
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{
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unsigned int low, high;
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u64 val;
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int i;
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/* clear all counters */
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for (i = 0 ; i < NUM_CONTROLS; ++i) {
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if (unlikely(!CTRL_IS_RESERVED(msrs, i)))
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continue;
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rdmsr(msrs->controls[i].addr, low, high);
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CTRL_CLEAR_LO(low);
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CTRL_CLEAR_HI(high);
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wrmsr(msrs->controls[i].addr, low, high);
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rdmsrl(msrs->controls[i].addr, val);
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val &= model->reserved;
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wrmsrl(msrs->controls[i].addr, val);
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}
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/* avoid a false detection of ctr overflows in NMI handler */
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@ -112,19 +109,11 @@ static void op_amd_setup_ctrs(struct op_x86_model_spec const *model,
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for (i = 0; i < NUM_COUNTERS; ++i) {
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if ((counter_config[i].enabled) && (CTR_IS_RESERVED(msrs, i))) {
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reset_value[i] = counter_config[i].count;
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wrmsr(msrs->counters[i].addr, -(unsigned int)counter_config[i].count, -1);
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rdmsr(msrs->controls[i].addr, low, high);
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CTRL_CLEAR_LO(low);
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CTRL_CLEAR_HI(high);
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CTRL_SET_ENABLE(low);
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CTRL_SET_USR(low, counter_config[i].user);
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CTRL_SET_KERN(low, counter_config[i].kernel);
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CTRL_SET_UM(low, counter_config[i].unit_mask);
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CTRL_SET_EVENT_LOW(low, counter_config[i].event);
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CTRL_SET_EVENT_HIGH(high, counter_config[i].event);
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wrmsr(msrs->controls[i].addr, low, high);
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rdmsrl(msrs->controls[i].addr, val);
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val &= model->reserved;
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val |= op_x86_get_ctrl(model, &counter_config[i]);
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wrmsrl(msrs->controls[i].addr, val);
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} else {
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reset_value[i] = 0;
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}
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@ -486,14 +475,16 @@ static void op_amd_exit(void) {}
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#endif /* CONFIG_OPROFILE_IBS */
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struct op_x86_model_spec const op_amd_spec = {
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.init = op_amd_init,
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.exit = op_amd_exit,
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.num_counters = NUM_COUNTERS,
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.num_controls = NUM_CONTROLS,
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.reserved = MSR_AMD_EVENTSEL_RESERVED,
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.event_mask = OP_EVENT_MASK,
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.init = op_amd_init,
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.exit = op_amd_exit,
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.fill_in_addresses = &op_amd_fill_in_addresses,
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.setup_ctrs = &op_amd_setup_ctrs,
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.check_ctrs = &op_amd_check_ctrs,
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.start = &op_amd_start,
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.stop = &op_amd_stop,
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.shutdown = &op_amd_shutdown
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.shutdown = &op_amd_shutdown,
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};
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@ -10,6 +10,7 @@
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* @author Philippe Elie
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* @author Graydon Hoare
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* @author Andi Kleen
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* @author Robert Richter <robert.richter@amd.com>
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*/
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#include <linux/oprofile.h>
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@ -26,8 +27,8 @@ static int num_counters = 2;
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static int counter_width = 32;
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#define CTR_OVERFLOWED(n) (!((n) & (1ULL<<(counter_width-1))))
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#define CTRL_CLEAR(x) (x &= (1<<21))
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#define CTRL_SET_EVENT(val, e) (val |= e)
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#define MSR_PPRO_EVENTSEL_RESERVED ((0xFFFFFFFFULL<<32)|(1ULL<<21))
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static u64 *reset_value;
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@ -54,7 +55,7 @@ static void ppro_fill_in_addresses(struct op_msrs * const msrs)
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static void ppro_setup_ctrs(struct op_x86_model_spec const *model,
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struct op_msrs const * const msrs)
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{
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unsigned int low, high;
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u64 val;
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int i;
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if (!reset_value) {
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@ -85,9 +86,9 @@ static void ppro_setup_ctrs(struct op_x86_model_spec const *model,
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for (i = 0 ; i < num_counters; ++i) {
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if (unlikely(!CTRL_IS_RESERVED(msrs, i)))
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continue;
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rdmsr(msrs->controls[i].addr, low, high);
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CTRL_CLEAR(low);
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wrmsr(msrs->controls[i].addr, low, high);
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rdmsrl(msrs->controls[i].addr, val);
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val &= model->reserved;
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wrmsrl(msrs->controls[i].addr, val);
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}
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/* avoid a false detection of ctr overflows in NMI handler */
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@ -101,17 +102,11 @@ static void ppro_setup_ctrs(struct op_x86_model_spec const *model,
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for (i = 0; i < num_counters; ++i) {
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if ((counter_config[i].enabled) && (CTR_IS_RESERVED(msrs, i))) {
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reset_value[i] = counter_config[i].count;
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wrmsrl(msrs->counters[i].addr, -reset_value[i]);
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rdmsr(msrs->controls[i].addr, low, high);
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CTRL_CLEAR(low);
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CTRL_SET_ENABLE(low);
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CTRL_SET_USR(low, counter_config[i].user);
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CTRL_SET_KERN(low, counter_config[i].kernel);
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CTRL_SET_UM(low, counter_config[i].unit_mask);
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CTRL_SET_EVENT(low, counter_config[i].event);
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wrmsr(msrs->controls[i].addr, low, high);
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rdmsrl(msrs->controls[i].addr, val);
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val &= model->reserved;
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val |= op_x86_get_ctrl(model, &counter_config[i]);
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wrmsrl(msrs->controls[i].addr, val);
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} else {
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reset_value[i] = 0;
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}
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@ -205,6 +200,7 @@ static void ppro_shutdown(struct op_msrs const * const msrs)
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struct op_x86_model_spec const op_ppro_spec = {
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.num_counters = 2,
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.num_controls = 2,
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.reserved = MSR_PPRO_EVENTSEL_RESERVED,
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.fill_in_addresses = &ppro_fill_in_addresses,
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.setup_ctrs = &ppro_setup_ctrs,
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.check_ctrs = &ppro_check_ctrs,
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@ -249,6 +245,7 @@ static int arch_perfmon_init(struct oprofile_operations *ignore)
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}
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struct op_x86_model_spec op_arch_perfmon_spec = {
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.reserved = MSR_PPRO_EVENTSEL_RESERVED,
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.init = &arch_perfmon_init,
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/* num_counters/num_controls filled in at runtime */
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.fill_in_addresses = &ppro_fill_in_addresses,
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@ -6,21 +6,19 @@
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* @remark Read the file COPYING
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*
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* @author Graydon Hoare
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* @author Robert Richter <robert.richter@amd.com>
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*/
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#ifndef OP_X86_MODEL_H
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#define OP_X86_MODEL_H
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#include <asm/types.h>
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#include <asm/intel_arch_perfmon.h>
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#define CTR_IS_RESERVED(msrs, c) ((msrs)->counters[(c)].addr ? 1 : 0)
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#define CTRL_IS_RESERVED(msrs, c) ((msrs)->controls[(c)].addr ? 1 : 0)
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#define CTRL_SET_ACTIVE(val) ((val) |= ARCH_PERFMON_EVENTSEL0_ENABLE)
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#define CTRL_SET_ENABLE(val) ((val) |= ARCH_PERFMON_EVENTSEL_INT)
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#define CTRL_SET_INACTIVE(val) ((val) &= ~ARCH_PERFMON_EVENTSEL0_ENABLE)
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#define CTRL_SET_KERN(val, k) ((val) |= ((k) ? ARCH_PERFMON_EVENTSEL_OS : 0))
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#define CTRL_SET_USR(val, u) ((val) |= ((u) ? ARCH_PERFMON_EVENTSEL_USR : 0))
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#define CTRL_SET_UM(val, m) ((val) |= ((m) << 8))
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struct op_saved_msr {
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unsigned int high;
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@ -39,12 +37,16 @@ struct op_msrs {
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struct pt_regs;
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struct oprofile_operations;
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/* The model vtable abstracts the differences between
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* various x86 CPU models' perfctr support.
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*/
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struct op_x86_model_spec {
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unsigned int num_counters;
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unsigned int num_controls;
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u64 reserved;
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u16 event_mask;
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int (*init)(struct oprofile_operations *ops);
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void (*exit)(void);
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void (*fill_in_addresses)(struct op_msrs * const msrs);
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@ -57,6 +59,11 @@ struct op_x86_model_spec {
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void (*shutdown)(struct op_msrs const * const msrs);
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};
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struct op_counter_config;
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extern u64 op_x86_get_ctrl(struct op_x86_model_spec const *model,
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struct op_counter_config *counter_config);
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extern struct op_x86_model_spec const op_ppro_spec;
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extern struct op_x86_model_spec const op_p4_spec;
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extern struct op_x86_model_spec const op_p4_ht2_spec;
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